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ba832ea2aacb4620830cdc2e187ac30fe5e32b50
[openwrt/staging/jow.git] / target / linux / mediatek / files-6.1 / arch / arm64 / boot / dts / mediatek / mt7981.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (c) 2020 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 * Author: Jianhui Zhao <zhaojh329@gmail.com>
6 */
7
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy.h>
11 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
12 #include <dt-bindings/reset/mt7986-resets.h>
13 #include <dt-bindings/pinctrl/mt65xx.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/input/linux-event-codes.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/mux/mux.h>
18
19 / {
20 compatible = "mediatek,mt7981";
21 interrupt-parent = <&gic>;
22 #address-cells = <2>;
23 #size-cells = <2>;
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 compatible = "arm,cortex-a53";
31 reg = <0x0>;
32 device_type = "cpu";
33 enable-method = "psci";
34 };
35
36 cpu@1 {
37 compatible = "arm,cortex-a53";
38 reg = <0x1>;
39 device_type = "cpu";
40 enable-method = "psci";
41 };
42 };
43
44 ice: ice_debug {
45 compatible = "mediatek,mt7981-ice_debug", "mediatek,mt2701-ice_debug";
46 clocks = <&infracfg CLK_INFRA_DBG_CK>;
47 clock-names = "ice_dbg";
48 };
49
50 clk40m: oscillator@0 {
51 compatible = "fixed-clock";
52 clock-frequency = <40000000>;
53 clock-output-names = "clkxtal";
54 #clock-cells = <0>;
55 };
56
57 psci {
58 compatible = "arm,psci-0.2";
59 method = "smc";
60 };
61
62 fan: pwm-fan {
63 compatible = "pwm-fan";
64 /* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */
65 cooling-levels = <0 63 95 127 159 191 223 255>;
66 #cooling-cells = <2>;
67 status = "disabled";
68 };
69
70 reg_3p3v: regulator-3p3v {
71 compatible = "regulator-fixed";
72 regulator-name = "fixed-3.3V";
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
75 regulator-boot-on;
76 regulator-always-on;
77 };
78
79 reserved-memory {
80 ranges;
81 #address-cells = <2>;
82 #size-cells = <2>;
83
84 /* 64 KiB reserved for ramoops/pstore */
85 ramoops@42ff0000 {
86 compatible = "ramoops";
87 reg = <0 0x42ff0000 0 0x10000>;
88 record-size = <0x1000>;
89 };
90
91 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
92 secmon_reserved: secmon@43000000 {
93 reg = <0 0x43000000 0 0x30000>;
94 no-map;
95 };
96
97 wmcpu_emi: wmcpu-reserved@47c80000 {
98 reg = <0 0x47c80000 0 0x100000>;
99 no-map;
100 };
101
102 wo_emi0: wo-emi@47d80000 {
103 reg = <0 0x47d80000 0 0x40000>;
104 no-map;
105 };
106
107 wo_data: wo-data@47dc0000 {
108 reg = <0 0x47dc0000 0 0x240000>;
109 no-map;
110 };
111 };
112
113 soc {
114 compatible = "simple-bus";
115 ranges;
116 #address-cells = <2>;
117 #size-cells = <2>;
118
119 gic: interrupt-controller@c000000 {
120 compatible = "arm,gic-v3";
121 reg = <0 0x0c000000 0 0x40000>, /* GICD */
122 <0 0x0c080000 0 0x200000>; /* GICR */
123 interrupt-parent = <&gic>;
124 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
125 interrupt-controller;
126 #interrupt-cells = <3>;
127 };
128
129 consys: consys@10000000 {
130 compatible = "mediatek,mt7981-consys";
131 reg = <0 0x10000000 0 0x8600000>;
132 memory-region = <&wmcpu_emi>;
133 };
134
135 infracfg: infracfg@10001000 {
136 compatible = "mediatek,mt7981-infracfg", "syscon";
137 reg = <0 0x10001000 0 0x1000>;
138 #clock-cells = <1>;
139 };
140
141 wed_pcie: wed_pcie@10003000 {
142 compatible = "mediatek,wed_pcie";
143 reg = <0 0x10003000 0 0x10>;
144 };
145
146 topckgen: topckgen@1001b000 {
147 compatible = "mediatek,mt7981-topckgen", "syscon";
148 reg = <0 0x1001b000 0 0x1000>;
149 #clock-cells = <1>;
150 };
151
152 watchdog: watchdog@1001c000 {
153 compatible = "mediatek,mt7986-wdt",
154 "mediatek,mt6589-wdt";
155 reg = <0 0x1001c000 0 0x1000>;
156 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
157 #reset-cells = <1>;
158 status = "disabled";
159 };
160
161 apmixedsys: apmixedsys@1001e000 {
162 compatible = "mediatek,mt7981-apmixedsys", "syscon";
163 reg = <0 0x1001e000 0 0x1000>;
164 #clock-cells = <1>;
165 };
166
167 pwm: pwm@10048000 {
168 compatible = "mediatek,mt7981-pwm";
169 reg = <0 0x10048000 0 0x1000>;
170 clocks = <&infracfg CLK_INFRA_PWM_STA>,
171 <&infracfg CLK_INFRA_PWM_HCK>,
172 <&infracfg CLK_INFRA_PWM1_CK>,
173 <&infracfg CLK_INFRA_PWM2_CK>,
174 <&infracfg CLK_INFRA_PWM3_CK>;
175 clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
176 #pwm-cells = <2>;
177 };
178
179 sgmiisys0: syscon@10060000 {
180 compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
181 reg = <0 0x10060000 0 0x1000>;
182 mediatek,pnswap;
183 #clock-cells = <1>;
184 };
185
186 sgmiisys1: syscon@10070000 {
187 compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
188 reg = <0 0x10070000 0 0x1000>;
189 #clock-cells = <1>;
190 };
191
192 crypto: crypto@10320000 {
193 compatible = "inside-secure,safexcel-eip97";
194 reg = <0 0x10320000 0 0x40000>;
195 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
199 interrupt-names = "ring0", "ring1", "ring2", "ring3";
200 clocks = <&topckgen CLK_TOP_EIP97B>;
201 clock-names = "top_eip97_ck";
202 assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
203 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
204 };
205
206 uart0: serial@11002000 {
207 compatible = "mediatek,mt6577-uart";
208 reg = <0 0x11002000 0 0x400>;
209 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
211 <&infracfg CLK_INFRA_UART0_CK>;
212 clock-names = "baud", "bus";
213 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
214 <&infracfg CLK_INFRA_UART0_SEL>;
215 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
216 <&topckgen CLK_TOP_UART_SEL>;
217 pinctrl-0 = <&uart0_pins>;
218 pinctrl-names = "default";
219 status = "disabled";
220 };
221
222 uart1: serial@11003000 {
223 compatible = "mediatek,mt6577-uart";
224 reg = <0 0x11003000 0 0x400>;
225 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
227 <&infracfg CLK_INFRA_UART1_CK>;
228 clock-names = "baud", "bus";
229 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
230 <&infracfg CLK_INFRA_UART1_SEL>;
231 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
232 <&topckgen CLK_TOP_UART_SEL>;
233 status = "disabled";
234 };
235
236 uart2: serial@11004000 {
237 compatible = "mediatek,mt6577-uart";
238 reg = <0 0x11004000 0 0x400>;
239 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
241 <&infracfg CLK_INFRA_UART2_CK>;
242 clock-names = "baud", "bus";
243 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
244 <&infracfg CLK_INFRA_UART2_SEL>;
245 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
246 <&topckgen CLK_TOP_UART_SEL>;
247 status = "disabled";
248 };
249
250 snand: snfi@11005000 {
251 compatible = "mediatek,mt7986-snand";
252 reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
253 reg-names = "nfi", "ecc";
254 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
256 <&infracfg CLK_INFRA_NFI1_CK>,
257 <&infracfg CLK_INFRA_NFI_HCK_CK>;
258 clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
259 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
260 <&topckgen CLK_TOP_NFI1X_SEL>;
261 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
262 <&topckgen CLK_TOP_CB_M_D8>;
263 #address-cells = <1>;
264 #size-cells = <0>;
265 status = "disabled";
266 };
267
268 i2c0: i2c@11007000 {
269 compatible = "mediatek,mt7981-i2c";
270 reg = <0 0x11007000 0 0x1000>,
271 <0 0x10217080 0 0x80>;
272 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
273 clock-div = <1>;
274 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
275 <&infracfg CLK_INFRA_AP_DMA_CK>,
276 <&infracfg CLK_INFRA_I2C_MCK_CK>,
277 <&infracfg CLK_INFRA_I2C_PCK_CK>;
278 clock-names = "main", "dma", "arb", "pmic";
279 #address-cells = <1>;
280 #size-cells = <0>;
281 status = "disabled";
282 };
283
284 spi2: spi@11009000 {
285 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
286 reg = <0 0x11009000 0 0x100>;
287 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&topckgen CLK_TOP_CB_M_D2>,
289 <&topckgen CLK_TOP_SPI_SEL>,
290 <&infracfg CLK_INFRA_SPI2_CK>,
291 <&infracfg CLK_INFRA_SPI2_HCK_CK>;
292 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
293 #address-cells = <1>;
294 #size-cells = <0>;
295 status = "disabled";
296 };
297
298 spi0: spi@1100a000 {
299 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
300 reg = <0 0x1100a000 0 0x100>;
301 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&topckgen CLK_TOP_CB_M_D2>,
303 <&topckgen CLK_TOP_SPI_SEL>,
304 <&infracfg CLK_INFRA_SPI0_CK>,
305 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
306 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
307 #address-cells = <1>;
308 #size-cells = <0>;
309 status = "disabled";
310 };
311
312 spi1: spi@1100b000 {
313 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
314 reg = <0 0x1100b000 0 0x100>;
315 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&topckgen CLK_TOP_CB_M_D2>,
317 <&topckgen CLK_TOP_SPIM_MST_SEL>,
318 <&infracfg CLK_INFRA_SPI1_CK>,
319 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
320 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
321 #address-cells = <1>;
322 #size-cells = <0>;
323 status = "disabled";
324 };
325
326 thermal: thermal@1100c800 {
327 compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
328 reg = <0 0x1100c800 0 0x800>;
329 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&infracfg CLK_INFRA_THERM_CK>,
331 <&infracfg CLK_INFRA_ADC_26M_CK>;
332 clock-names = "therm", "auxadc";
333 nvmem-cells = <&thermal_calibration>;
334 nvmem-cell-names = "calibration-data";
335 #thermal-sensor-cells = <1>;
336 mediatek,auxadc = <&auxadc>;
337 mediatek,apmixedsys = <&apmixedsys>;
338 };
339
340 auxadc: adc@1100d000 {
341 compatible = "mediatek,mt7981-auxadc",
342 "mediatek,mt7986-auxadc",
343 "mediatek,mt7622-auxadc";
344 reg = <0 0x1100d000 0 0x1000>;
345 clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
346 <&infracfg CLK_INFRA_ADC_FRC_CK>;
347 clock-names = "main", "32k";
348 #io-channel-cells = <1>;
349 };
350
351 xhci: usb@11200000 {
352 compatible = "mediatek,mt7986-xhci",
353 "mediatek,mtk-xhci";
354 reg = <0 0x11200000 0 0x2e00>,
355 <0 0x11203e00 0 0x0100>;
356 reg-names = "mac", "ippc";
357 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
359 <&infracfg CLK_INFRA_IUSB_CK>,
360 <&infracfg CLK_INFRA_IUSB_133_CK>,
361 <&infracfg CLK_INFRA_IUSB_66M_CK>,
362 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
363 clock-names = "sys_ck",
364 "ref_ck",
365 "mcu_ck",
366 "dma_ck",
367 "xhci_ck";
368 phys = <&u2port0 PHY_TYPE_USB2>,
369 <&u3port0 PHY_TYPE_USB3>;
370 vusb33-supply = <&reg_3p3v>;
371 status = "disabled";
372 };
373
374 afe: audio-controller@11210000 {
375 compatible = "mediatek,mt79xx-audio";
376 reg = <0 0x11210000 0 0x9000>;
377 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
379 <&infracfg CLK_INFRA_AUD_26M_CK>,
380 <&infracfg CLK_INFRA_AUD_L_CK>,
381 <&infracfg CLK_INFRA_AUD_AUD_CK>,
382 <&infracfg CLK_INFRA_AUD_EG2_CK>,
383 <&topckgen CLK_TOP_AUD_SEL>;
384 clock-names = "aud_bus_ck",
385 "aud_26m_ck",
386 "aud_l_ck",
387 "aud_aud_ck",
388 "aud_eg2_ck",
389 "aud_sel";
390 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
391 <&topckgen CLK_TOP_A1SYS_SEL>,
392 <&topckgen CLK_TOP_AUD_L_SEL>,
393 <&topckgen CLK_TOP_A_TUNER_SEL>;
394 assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
395 <&topckgen CLK_TOP_APLL2_D4>,
396 <&topckgen CLK_TOP_CB_APLL2_196M>,
397 <&topckgen CLK_TOP_APLL2_D4>;
398 status = "disabled";
399 };
400
401 mmc0: mmc@11230000 {
402 compatible = "mediatek,mt7986-mmc", "mediatek,mt7981-mmc";
403 reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
404 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&infracfg CLK_INFRA_MSDC_CK>,
406 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
407 <&infracfg CLK_INFRA_MSDC_66M_CK>,
408 <&infracfg CLK_INFRA_MSDC_133M_CK>;
409 assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
410 <&topckgen CLK_TOP_EMMC_400M_SEL>;
411 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
412 <&topckgen CLK_TOP_CB_NET2_D2>;
413 clock-names = "source", "hclk", "axi_cg", "ahb_cg";
414 status = "disabled";
415 };
416
417 pcie: pcie@11280000 {
418 compatible = "mediatek,mt7981-pcie",
419 "mediatek,mt7986-pcie";
420 reg = <0 0x11280000 0 0x4000>;
421 reg-names = "pcie-mac";
422 ranges = <0x82000000 0 0x20000000
423 0x0 0x20000000 0 0x10000000>;
424 device_type = "pci";
425 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
426 bus-range = <0x00 0xff>;
427 clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
428 <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
429 <&infracfg CLK_INFRA_IPCIER_CK>,
430 <&infracfg CLK_INFRA_IPCIEB_CK>;
431 phys = <&u3port0 PHY_TYPE_PCIE>;
432 phy-names = "pcie-phy";
433 interrupt-map-mask = <0 0 0 7>;
434 interrupt-map = <0 0 0 1 &pcie_intc 0>,
435 <0 0 0 2 &pcie_intc 1>,
436 <0 0 0 3 &pcie_intc 2>,
437 <0 0 0 4 &pcie_intc 3>;
438 #interrupt-cells = <1>;
439 #address-cells = <3>;
440 #size-cells = <2>;
441 status = "disabled";
442
443 pcie_intc: interrupt-controller {
444 interrupt-controller;
445 #interrupt-cells = <1>;
446 #address-cells = <0>;
447 };
448 };
449
450 pio: pinctrl@11d00000 {
451 compatible = "mediatek,mt7981-pinctrl";
452 reg = <0 0x11d00000 0 0x1000>,
453 <0 0x11c00000 0 0x1000>,
454 <0 0x11c10000 0 0x1000>,
455 <0 0x11d20000 0 0x1000>,
456 <0 0x11e00000 0 0x1000>,
457 <0 0x11e20000 0 0x1000>,
458 <0 0x11f00000 0 0x1000>,
459 <0 0x11f10000 0 0x1000>,
460 <0 0x1000b000 0 0x1000>;
461 reg-names = "gpio", "iocfg_rt", "iocfg_rm",
462 "iocfg_rb", "iocfg_lb", "iocfg_bl",
463 "iocfg_tm", "iocfg_tl", "eint";
464 gpio-controller;
465 #gpio-cells = <2>;
466 gpio-ranges = <&pio 0 0 56>;
467 interrupt-controller;
468 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
469 interrupt-parent = <&gic>;
470 #interrupt-cells = <2>;
471
472 mdio_pins: mdc-mdio-pins {
473 mux {
474 function = "eth";
475 groups = "smi_mdc_mdio";
476 };
477 };
478
479 uart0_pins: uart0-pins {
480 mux {
481 function = "uart";
482 groups = "uart0";
483 };
484 };
485
486 wifi_dbdc_pins: wifi-dbdc-pins {
487 mux {
488 function = "eth";
489 groups = "wf0_mode1";
490 };
491
492 conf {
493 pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
494 "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
495 "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
496 "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
497 "WF_CBA_RESETB", "WF_DIG_RESETB";
498 drive-strength = <4>;
499 };
500 };
501
502 gbe_led0_pins: gbe-led0-pins {
503 mux {
504 function = "led";
505 groups = "gbe_led0";
506 };
507 };
508
509 gbe_led1_pins: gbe-led1-pins {
510 mux {
511 function = "led";
512 groups = "gbe_led1";
513 };
514 };
515 };
516
517 topmisc: topmisc@11d10000 {
518 compatible = "mediatek,mt7981-topmisc", "syscon";
519 reg = <0 0x11d10000 0 0x10000>;
520 #clock-cells = <1>;
521 };
522
523 usb_phy: usb-phy@11e10000 {
524 compatible = "mediatek,mt7981",
525 "mediatek,generic-tphy-v2";
526 ranges = <0 0 0x11e10000 0x1700>;
527 #address-cells = <1>;
528 #size-cells = <1>;
529 status = "disabled";
530
531 u2port0: usb-phy@0 {
532 reg = <0x0 0x700>;
533 clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
534 clock-names = "ref";
535 #phy-cells = <1>;
536 };
537
538 u3port0: usb-phy@700 {
539 reg = <0x700 0x900>;
540 clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
541 clock-names = "ref";
542 #phy-cells = <1>;
543 mediatek,syscon-type = <&topmisc 0x218 0>;
544 status = "okay";
545 };
546 };
547
548 efuse: efuse@11f20000 {
549 compatible = "mediatek,mt7981-efuse",
550 "mediatek,efuse";
551 reg = <0 0x11f20000 0 0x1000>;
552 #address-cells = <1>;
553 #size-cells = <1>;
554 status = "okay";
555
556 thermal_calibration: thermal-calib@274 {
557 reg = <0x274 0xc>;
558 };
559
560 phy_calibration: phy-calib@8dc {
561 reg = <0x8dc 0x10>;
562 };
563
564 comb_rx_imp_p0: usb3-rx-imp@8c8 {
565 reg = <0x8c8 1>;
566 bits = <0 5>;
567 };
568
569 comb_tx_imp_p0: usb3-tx-imp@8c8 {
570 reg = <0x8c8 2>;
571 bits = <5 5>;
572 };
573
574 comb_intr_p0: usb3-intr@8c9 {
575 reg = <0x8c9 1>;
576 bits = <2 6>;
577 };
578 };
579
580 ethsys: syscon@15000000 {
581 compatible = "mediatek,mt7981-ethsys",
582 "syscon";
583 reg = <0 0x15000000 0 0x1000>;
584 #clock-cells = <1>;
585 #reset-cells = <1>;
586 #address-cells = <1>;
587 #size-cells = <1>;
588 };
589
590 wed: wed@15010000 {
591 compatible = "mediatek,mt7981-wed",
592 "mediatek,mt7986-wed",
593 "syscon";
594 reg = <0 0x15010000 0 0x1000>;
595 interrupt-parent = <&gic>;
596 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
597 memory-region = <&wo_emi0>, <&wo_data>;
598 memory-region-names = "wo-emi", "wo-data";
599 mediatek,wo-ccif = <&wo_ccif0>;
600 mediatek,wo-ilm = <&wo_ilm0>;
601 mediatek,wo-dlm = <&wo_dlm0>;
602 mediatek,wo-cpuboot = <&wo_cpuboot>;
603 };
604
605 eth: ethernet@15100000 {
606 compatible = "mediatek,mt7981-eth";
607 reg = <0 0x15100000 0 0x80000>;
608 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&ethsys CLK_ETH_FE_EN>,
613 <&ethsys CLK_ETH_GP2_EN>,
614 <&ethsys CLK_ETH_GP1_EN>,
615 <&ethsys CLK_ETH_WOCPU0_EN>,
616 <&sgmiisys0 CLK_SGM0_TX_EN>,
617 <&sgmiisys0 CLK_SGM0_RX_EN>,
618 <&sgmiisys0 CLK_SGM0_CK0_EN>,
619 <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
620 <&sgmiisys1 CLK_SGM1_TX_EN>,
621 <&sgmiisys1 CLK_SGM1_RX_EN>,
622 <&sgmiisys1 CLK_SGM1_CK1_EN>,
623 <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
624 <&topckgen CLK_TOP_SGM_REG>,
625 <&topckgen CLK_TOP_NETSYS_SEL>,
626 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
627 clock-names = "fe", "gp2", "gp1", "wocpu0",
628 "sgmii_tx250m", "sgmii_rx250m",
629 "sgmii_cdr_ref", "sgmii_cdr_fb",
630 "sgmii2_tx250m", "sgmii2_rx250m",
631 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
632 "sgmii_ck", "netsys0", "netsys1";
633 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
634 <&topckgen CLK_TOP_SGM_325M_SEL>;
635 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
636 <&topckgen CLK_TOP_CB_SGM_325M>;
637 mediatek,ethsys = <&ethsys>;
638 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
639 mediatek,infracfg = <&topmisc>;
640 mediatek,wed = <&wed>;
641 #reset-cells = <1>;
642 #address-cells = <1>;
643 #size-cells = <0>;
644 status = "disabled";
645
646 mdio_bus: mdio-bus {
647 #address-cells = <1>;
648 #size-cells = <0>;
649
650 int_gbe_phy: ethernet-phy@0 {
651 compatible = "ethernet-phy-ieee802.3-c22";
652 reg = <0>;
653 phy-mode = "gmii";
654 phy-is-integrated;
655 nvmem-cells = <&phy_calibration>;
656 nvmem-cell-names = "phy-cal-data";
657
658 leds {
659 #address-cells = <1>;
660 #size-cells = <0>;
661
662 int_gbe_phy_led0: int-gbe-phy-led0@0 {
663 reg = <0>;
664 function = LED_FUNCTION_LAN;
665 status = "disabled";
666 };
667
668 int_gbe_phy_led1: int-gbe-phy-led1@1 {
669 reg = <1>;
670 function = LED_FUNCTION_LAN;
671 status = "disabled";
672 };
673 };
674 };
675 };
676 };
677
678 wdma: wdma@15104800 {
679 compatible = "mediatek,wed-wdma";
680 reg = <0 0x15104800 0 0x400>,
681 <0 0x15104c00 0 0x400>;
682 };
683
684 wo_cpuboot: syscon@15194000 {
685 compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
686 reg = <0 0x15194000 0 0x1000>;
687 };
688
689 ap2woccif: ap2woccif@151a5000 {
690 compatible = "mediatek,ap2woccif";
691 reg = <0 0x151a5000 0 0x1000>,
692 <0 0x151ad000 0 0x1000>;
693 interrupt-parent = <&gic>;
694 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
696 };
697
698 wo_ccif0: syscon@151a5000 {
699 compatible = "mediatek,mt7986-wo-ccif", "syscon";
700 reg = <0 0x151a5000 0 0x1000>;
701 interrupt-parent = <&gic>;
702 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
703 };
704
705 wo_ilm0: syscon@151e0000 {
706 compatible = "mediatek,mt7986-wo-ilm", "syscon";
707 reg = <0 0x151e0000 0 0x8000>;
708 };
709
710 wo_dlm0: syscon@151e8000 {
711 compatible = "mediatek,mt7986-wo-dlm", "syscon";
712 reg = <0 0x151e8000 0 0x2000>;
713 };
714
715 wifi: wifi@18000000 {
716 compatible = "mediatek,mt7981-wmac";
717 reg = <0 0x18000000 0 0x1000000>,
718 <0 0x10003000 0 0x1000>,
719 <0 0x11d10000 0 0x1000>;
720 resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
721 reset-names = "consys";
722 pinctrl-0 = <&wifi_dbdc_pins>;
723 pinctrl-names = "dbdc";
724 clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
725 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
726 clock-names = "mcu", "ap2conn";
727 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
728 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
729 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
730 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
731 memory-region = <&wmcpu_emi>;
732 status = "disabled";
733 };
734 };
735
736 thermal-zones {
737 cpu_thermal: cpu-thermal {
738 polling-delay-passive = <1000>;
739 polling-delay = <1000>;
740 thermal-sensors = <&thermal 0>;
741
742 trips {
743 cpu_trip_active_highest: active-highest {
744 temperature = <70000>;
745 hysteresis = <2000>;
746 type = "active";
747 };
748
749 cpu_trip_active_high: active-high {
750 temperature = <60000>;
751 hysteresis = <2000>;
752 type = "active";
753 };
754
755 cpu_trip_active_med: active-med {
756 temperature = <50000>;
757 hysteresis = <2000>;
758 type = "active";
759 };
760
761 cpu_trip_active_low: active-low {
762 temperature = <45000>;
763 hysteresis = <2000>;
764 type = "active";
765 };
766
767 cpu_trip_active_lowest: active-lowest {
768 temperature = <40000>;
769 hysteresis = <2000>;
770 type = "active";
771 };
772 };
773
774 cooling-maps {
775 cpu-active-highest {
776 /* active: set fan to cooling level 7 */
777 cooling-device = <&fan 7 7>;
778 trip = <&cpu_trip_active_highest>;
779 };
780
781 cpu-active-high {
782 /* active: set fan to cooling level 5 */
783 cooling-device = <&fan 5 5>;
784 trip = <&cpu_trip_active_high>;
785 };
786
787 cpu-active-med {
788 /* active: set fan to cooling level 3 */
789 cooling-device = <&fan 3 3>;
790 trip = <&cpu_trip_active_med>;
791 };
792
793 cpu-active-low {
794 /* active: set fan to cooling level 2 */
795 cooling-device = <&fan 2 2>;
796 trip = <&cpu_trip_active_low>;
797 };
798
799 cpu-active-lowest {
800 /* active: set fan to cooling level 1 */
801 cooling-device = <&fan 1 1>;
802 trip = <&cpu_trip_active_lowest>;
803 };
804 };
805 };
806 };
807
808 timer {
809 compatible = "arm,armv8-timer";
810 interrupt-parent = <&gic>;
811 clock-frequency = <13000000>;
812 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
813 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
814 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
815 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
816
817 };
818
819 trng {
820 compatible = "mediatek,mt7981-rng";
821 };
822 };
Staging tree of Jo-Philipp Wich