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mediatek: add support for rtl8367c
[openwrt/staging/jow.git] / target / linux / mediatek / files-5.4 / drivers / net / phy / rtk / rtl8367c / rtk_switch.c
1 /*
2 * Copyright (C) 2013 Realtek Semiconductor Corp.
3 * All Rights Reserved.
4 *
5 * Unless you and Realtek execute a separate written software license
6 * agreement governing use of this software, this software is licensed
7 * to you under the terms of the GNU General Public License version 2,
8 * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
9 *
10 * $Revision: 76336 $
11 * $Date: 2017-03-09 10:41:21 +0800 (ι€±ε››, 09 δΈ‰ζœˆ 2017) $
12 *
13 * Purpose : RTK switch high-level API
14 * Feature : Here is a list of all functions and variables in this module.
15 *
16 */
17 #include <rtk_switch.h>
18 #include <rtk_error.h>
19 #include <string.h>
20
21 #include <rate.h>
22 #include <rtl8367c_asicdrv.h>
23 #include <rtl8367c_asicdrv_misc.h>
24 #include <rtl8367c_asicdrv_green.h>
25 #include <rtl8367c_asicdrv_lut.h>
26 #include <rtl8367c_asicdrv_rma.h>
27 #include <rtl8367c_asicdrv_mirror.h>
28
29 #if defined(FORCE_PROBE_RTL8367C)
30 static init_state_t init_state = INIT_COMPLETED;
31 #elif defined(FORCE_PROBE_RTL8370B)
32 static init_state_t init_state = INIT_COMPLETED;
33 #elif defined(FORCE_PROBE_RTL8364B)
34 static init_state_t init_state = INIT_COMPLETED;
35 #elif defined(FORCE_PROBE_RTL8363SC_VB)
36 static init_state_t init_state = INIT_COMPLETED;
37 #else
38 static init_state_t init_state = INIT_NOT_COMPLETED;
39 #endif
40
41 #define AUTO_PROBE (!defined(FORCE_PROBE_RTL8367C) && !defined(FORCE_PROBE_RTL8370B) && !defined(FORCE_PROBE_RTL8364B) && !defined(FORCE_PROBE_RTL8363SC_VB))
42
43 #if (AUTO_PROBE || defined(FORCE_PROBE_RTL8367C))
44 static rtk_switch_halCtrl_t rtl8367c_hal_Ctrl =
45 {
46 /* Switch Chip */
47 CHIP_RTL8367C,
48
49 /* Logical to Physical */
50 {0, 1, 2, 3, 4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
51 6, 7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
52
53 /* Physical to Logical */
54 {UTP_PORT0, UTP_PORT1, UTP_PORT2, UTP_PORT3, UTP_PORT4, UNDEFINE_PORT, EXT_PORT0, EXT_PORT1,
55 UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT,
56 UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT,
57 UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT},
58
59 /* Port Type */
60 {UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,
61 UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,
62 EXT_PORT, EXT_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,
63 UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT},
64
65 /* PTP port */
66 {1, 1, 1, 1, 1, 0, 0, 0,
67 0, 0, 0, 0, 0, 0, 0, 0,
68 0, 0, 0, 0, 0, 0, 0, 0,
69 0, 0, 0, 0, 0, 0, 0, 0 },
70
71 /* Valid port mask */
72 ( (0x1 << UTP_PORT0) | (0x1 << UTP_PORT1) | (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) | (0x1 << UTP_PORT4) | (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ),
73
74 /* Valid UTP port mask */
75 ( (0x1 << UTP_PORT0) | (0x1 << UTP_PORT1) | (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) | (0x1 << UTP_PORT4) ),
76
77 /* Valid EXT port mask */
78 ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ),
79
80 /* Valid CPU port mask */
81 0x00,
82
83 /* Minimum physical port number */
84 0,
85
86 /* Maxmum physical port number */
87 7,
88
89 /* Physical port mask */
90 0xDF,
91
92 /* Combo Logical port ID */
93 4,
94
95 /* HSG Logical port ID */
96 EXT_PORT0,
97
98 /* SGMII Logical portmask */
99 (0x1 << EXT_PORT0),
100
101 /* Max Meter ID */
102 31,
103
104 /* MAX LUT Address Number */
105 2112,
106
107 /* Trunk Group Mask */
108 0x03
109 };
110 #endif
111
112 #if (AUTO_PROBE || defined(FORCE_PROBE_RTL8370B))
113 static rtk_switch_halCtrl_t rtl8370b_hal_Ctrl =
114 {
115 /* Switch Chip */
116 CHIP_RTL8370B,
117
118 /* Logical to Physical */
119 {0, 1, 2, 3, 4, 5, 6, 7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
120 8, 9, 10, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
121
122 /* Physical to Logical */
123 {UTP_PORT0, UTP_PORT1, UTP_PORT2, UTP_PORT3, UTP_PORT4, UTP_PORT5, UTP_PORT6, UTP_PORT7,
124 EXT_PORT0, EXT_PORT1, EXT_PORT2, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT,
125 UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT,
126 UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT},
127
128 /* Port Type */
129 {UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT,
130 UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,
131 EXT_PORT, EXT_PORT, EXT_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,
132 UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT},
133
134 /* PTP port */
135 {1, 1, 1, 1, 1, 1, 1, 1,
136 0, 0, 0, 0, 0, 0, 0, 0,
137 1, 1, 0, 0, 0, 0, 0, 0,
138 0, 0, 0, 0, 0, 0, 0, 0 },
139
140 /* Valid port mask */
141 ( (0x1 << UTP_PORT0) | (0x1 << UTP_PORT1) | (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) | (0x1 << UTP_PORT4) | (0x1 << UTP_PORT5) | (0x1 << UTP_PORT6) | (0x1 << UTP_PORT7) | (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) | (0x1 << EXT_PORT2) ),
142
143 /* Valid UTP port mask */
144 ( (0x1 << UTP_PORT0) | (0x1 << UTP_PORT1) | (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) | (0x1 << UTP_PORT4) | (0x1 << UTP_PORT5) | (0x1 << UTP_PORT6) | (0x1 << UTP_PORT7) ),
145
146 /* Valid EXT port mask */
147 ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) | (0x1 << EXT_PORT2) ),
148
149 /* Valid CPU port mask */
150 (0x1 << EXT_PORT2),
151
152 /* Minimum physical port number */
153 0,
154
155 /* Maxmum physical port number */
156 10,
157
158 /* Physical port mask */
159 0x7FF,
160
161 /* Combo Logical port ID */
162 7,
163
164 /* HSG Logical port ID */
165 EXT_PORT1,
166
167 /* SGMII Logical portmask */
168 ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ),
169
170 /* Max Meter ID */
171 63,
172
173 /* MAX LUT Address Number 4096 + 64*/
174 4160,
175
176 /* Trunk Group Mask */
177 0x07
178 };
179 #endif
180
181 #if (AUTO_PROBE || defined(FORCE_PROBE_RTL8364B))
182 static rtk_switch_halCtrl_t rtl8364b_hal_Ctrl =
183 {
184 /* Switch Chip */
185 CHIP_RTL8364B,
186
187 /* Logical to Physical */
188 {0xFF, 1, 0xFF, 3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
189 6, 7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
190
191 /* Physical to Logical */
192 {UNDEFINE_PORT, UTP_PORT1, UNDEFINE_PORT, UTP_PORT3, UNDEFINE_PORT, UNDEFINE_PORT, EXT_PORT0, EXT_PORT1,
193 UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT,
194 UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT,
195 UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT},
196
197 /* Port Type */
198 {UNKNOWN_PORT, UTP_PORT, UNKNOWN_PORT, UTP_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,
199 UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,
200 EXT_PORT, EXT_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,
201 UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT},
202
203 /* PTP port */
204 {0, 0, 0, 0, 0, 0, 0, 0,
205 0, 0, 0, 0, 0, 0, 0, 0,
206 0, 0, 0, 0, 0, 0, 0, 0,
207 0, 0, 0, 0, 0, 0, 0, 0 },
208
209 /* Valid port mask */
210 ( (0x1 << UTP_PORT1) | (0x1 << UTP_PORT3) | (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ),
211
212 /* Valid UTP port mask */
213 ( (0x1 << UTP_PORT1) | (0x1 << UTP_PORT3) ),
214
215 /* Valid EXT port mask */
216 ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ),
217
218 /* Valid CPU port mask */
219 0x00,
220
221 /* Minimum physical port number */
222 0,
223
224 /* Maxmum physical port number */
225 7,
226
227 /* Physical port mask */
228 0xCA,
229
230 /* Combo Logical port ID */
231 4,
232
233 /* HSG Logical port ID */
234 EXT_PORT0,
235
236 /* SGMII Logical portmask */
237 ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ),
238
239 /* Max Meter ID */
240 32,
241
242 /* MAX LUT Address Number */
243 2112,
244
245 /* Trunk Group Mask */
246 0x01
247 };
248 #endif
249
250 #if (AUTO_PROBE || defined(FORCE_PROBE_RTL8363SC_VB))
251 static rtk_switch_halCtrl_t rtl8363sc_vb_hal_Ctrl =
252 {
253 /* Switch Chip */
254 CHIP_RTL8363SC_VB,
255
256 /* Logical to Physical */
257 {0xFF, 0xFF, 1, 3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
258 6, 7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
259
260 /* Physical to Logical */
261 {UNDEFINE_PORT, UTP_PORT2, UNDEFINE_PORT, UTP_PORT3, UNDEFINE_PORT, UNDEFINE_PORT, EXT_PORT0, EXT_PORT1,
262 UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT,
263 UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT,
264 UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT},
265
266 /* Port Type */
267 {UNKNOWN_PORT, UNKNOWN_PORT, UTP_PORT, UTP_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,
268 UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,
269 EXT_PORT, EXT_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,
270 UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT},
271
272 /* PTP port */
273 {0, 0, 0, 0, 0, 0, 0, 0,
274 0, 0, 0, 0, 0, 0, 0, 0,
275 0, 0, 0, 0, 0, 0, 0, 0,
276 0, 0, 0, 0, 0, 0, 0, 0 },
277
278 /* Valid port mask */
279 ( (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) | (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ),
280
281 /* Valid UTP port mask */
282 ( (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) ),
283
284 /* Valid EXT port mask */
285 ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ),
286
287 /* Valid CPU port mask */
288 0x00,
289
290 /* Minimum physical port number */
291 0,
292
293 /* Maxmum physical port number */
294 7,
295
296 /* Physical port mask */
297 0xCA,
298
299 /* Combo Logical port ID */
300 4,
301
302 /* HSG Logical port ID */
303 EXT_PORT0,
304
305 /* SGMII Logical portmask */
306 ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ),
307
308 /* Max Meter ID */
309 32,
310
311 /* MAX LUT Address Number */
312 2112,
313
314 /* Trunk Group Mask */
315 0x01
316 };
317 #endif
318
319 #if defined(FORCE_PROBE_RTL8367C)
320 static rtk_switch_halCtrl_t *halCtrl = &rtl8367c_hal_Ctrl;
321 #elif defined(FORCE_PROBE_RTL8370B)
322 static rtk_switch_halCtrl_t *halCtrl = &rtl8370b_hal_Ctrl;
323 #elif defined(FORCE_PROBE_RTL8364B)
324 static rtk_switch_halCtrl_t *halCtrl = &rtl8364b_hal_Ctrl;
325 #elif defined(FORCE_PROBE_RTL8363SC_VB)
326 static rtk_switch_halCtrl_t *halCtrl = &rtl8363sc_vb_hal_Ctrl;
327 #else
328 static rtk_switch_halCtrl_t *halCtrl = NULL;
329 #endif
330
331 static rtk_uint32 PatchChipData[210][2] =
332 {
333 {0xa436, 0x8028}, {0xa438, 0x6800}, {0xb82e, 0x0001}, {0xa436, 0xb820}, {0xa438, 0x0090}, {0xa436, 0xa012}, {0xa438, 0x0000}, {0xa436, 0xa014}, {0xa438, 0x2c04}, {0xa438, 0x2c6c},
334 {0xa438, 0x2c75}, {0xa438, 0x2c77}, {0xa438, 0x1414}, {0xa438, 0x1579}, {0xa438, 0x1536}, {0xa438, 0xc432}, {0xa438, 0x32c0}, {0xa438, 0x42d6}, {0xa438, 0x32b5}, {0xa438, 0x003e},
335 {0xa438, 0x614c}, {0xa438, 0x1569}, {0xa438, 0xd705}, {0xa438, 0x318c}, {0xa438, 0x42d6}, {0xa438, 0xd702}, {0xa438, 0x31ef}, {0xa438, 0x42d6}, {0xa438, 0x629c}, {0xa438, 0x2c04},
336 {0xa438, 0x653c}, {0xa438, 0x422a}, {0xa438, 0x5d83}, {0xa438, 0xd06a}, {0xa438, 0xd1b0}, {0xa438, 0x1536}, {0xa438, 0xc43a}, {0xa438, 0x32c0}, {0xa438, 0x42d6}, {0xa438, 0x32b5},
337 {0xa438, 0x003e}, {0xa438, 0x314a}, {0xa438, 0x42fe}, {0xa438, 0x337b}, {0xa438, 0x02d6}, {0xa438, 0x3063}, {0xa438, 0x0c1b}, {0xa438, 0x22fe}, {0xa438, 0xc435}, {0xa438, 0xd0be},
338 {0xa438, 0xd1f7}, {0xa438, 0xe0f0}, {0xa438, 0x1a40}, {0xa438, 0xa320}, {0xa438, 0xd702}, {0xa438, 0x154a}, {0xa438, 0xc434}, {0xa438, 0x32c0}, {0xa438, 0x42d6}, {0xa438, 0x32b5},
339 {0xa438, 0x003e}, {0xa438, 0x60ec}, {0xa438, 0x1569}, {0xa438, 0xd705}, {0xa438, 0x619f}, {0xa438, 0xd702}, {0xa438, 0x414f}, {0xa438, 0x2c2e}, {0xa438, 0x610a}, {0xa438, 0xd705},
340 {0xa438, 0x5e1f}, {0xa438, 0xc43f}, {0xa438, 0xc88b}, {0xa438, 0xd702}, {0xa438, 0x7fe0}, {0xa438, 0x22f3}, {0xa438, 0xd0a0}, {0xa438, 0xd1b2}, {0xa438, 0xd0c3}, {0xa438, 0xd1c3},
341 {0xa438, 0x8d01}, {0xa438, 0x1536}, {0xa438, 0xc438}, {0xa438, 0xe0f0}, {0xa438, 0x1a80}, {0xa438, 0xd706}, {0xa438, 0x60c0}, {0xa438, 0xd710}, {0xa438, 0x409e}, {0xa438, 0xa804},
342 {0xa438, 0xad01}, {0xa438, 0x8804}, {0xa438, 0xd702}, {0xa438, 0x32c0}, {0xa438, 0x42d6}, {0xa438, 0x32b5}, {0xa438, 0x003e}, {0xa438, 0x405b}, {0xa438, 0x1576}, {0xa438, 0x7c9c},
343 {0xa438, 0x60ec}, {0xa438, 0x1569}, {0xa438, 0xd702}, {0xa438, 0x5d43}, {0xa438, 0x31ef}, {0xa438, 0x02fe}, {0xa438, 0x22d6}, {0xa438, 0x590a}, {0xa438, 0xd706}, {0xa438, 0x5c80},
344 {0xa438, 0xd702}, {0xa438, 0x5c44}, {0xa438, 0x3063}, {0xa438, 0x02d6}, {0xa438, 0x5be2}, {0xa438, 0x22fb}, {0xa438, 0xa240}, {0xa438, 0xa104}, {0xa438, 0x8c03}, {0xa438, 0x8178},
345 {0xa438, 0xd701}, {0xa438, 0x31ad}, {0xa438, 0x4917}, {0xa438, 0x8102}, {0xa438, 0x2917}, {0xa438, 0xc302}, {0xa438, 0x268a}, {0xa436, 0xA01A}, {0xa438, 0x0000}, {0xa436, 0xA006},
346 {0xa438, 0x0fff}, {0xa436, 0xA004}, {0xa438, 0x0689}, {0xa436, 0xA002}, {0xa438, 0x0911}, {0xa436, 0xA000}, {0xa438, 0x7302}, {0xa436, 0xB820}, {0xa438, 0x0010}, {0xa436, 0x8412},
347 {0xa438, 0xaf84}, {0xa438, 0x1eaf}, {0xa438, 0x8427}, {0xa438, 0xaf84}, {0xa438, 0x27af}, {0xa438, 0x8427}, {0xa438, 0x0251}, {0xa438, 0x6802}, {0xa438, 0x8427}, {0xa438, 0xaf04},
348 {0xa438, 0x0af8}, {0xa438, 0xf9bf}, {0xa438, 0x5581}, {0xa438, 0x0255}, {0xa438, 0x27ef}, {0xa438, 0x310d}, {0xa438, 0x345b}, {0xa438, 0x0fa3}, {0xa438, 0x032a}, {0xa438, 0xe087},
349 {0xa438, 0xffac}, {0xa438, 0x2040}, {0xa438, 0xbf56}, {0xa438, 0x7402}, {0xa438, 0x5527}, {0xa438, 0xef31}, {0xa438, 0xef20}, {0xa438, 0xe787}, {0xa438, 0xfee6}, {0xa438, 0x87fd},
350 {0xa438, 0xd488}, {0xa438, 0x88bf}, {0xa438, 0x5674}, {0xa438, 0x0254}, {0xa438, 0xe3e0}, {0xa438, 0x87ff}, {0xa438, 0xf720}, {0xa438, 0xe487}, {0xa438, 0xffaf}, {0xa438, 0x847e},
351 {0xa438, 0xe087}, {0xa438, 0xffad}, {0xa438, 0x2016}, {0xa438, 0xe387}, {0xa438, 0xfee2}, {0xa438, 0x87fd}, {0xa438, 0xef45}, {0xa438, 0xbf56}, {0xa438, 0x7402}, {0xa438, 0x54e3},
352 {0xa438, 0xe087}, {0xa438, 0xfff6}, {0xa438, 0x20e4}, {0xa438, 0x87ff}, {0xa438, 0xfdfc}, {0xa438, 0x0400}, {0xa436, 0xb818}, {0xa438, 0x0407}, {0xa436, 0xb81a}, {0xa438, 0xfffd},
353 {0xa436, 0xb81c}, {0xa438, 0xfffd}, {0xa436, 0xb81e}, {0xa438, 0xfffd}, {0xa436, 0xb832}, {0xa438, 0x0001}, {0xb820, 0x0000}, {0xb82e, 0x0000}, {0xa436, 0x8028}, {0xa438, 0x0000}
354 };
355
356 static rtk_api_ret_t _rtk_switch_init_8367c(void)
357 {
358 rtk_port_t port;
359 rtk_uint32 retVal;
360 rtk_uint32 regData;
361 rtk_uint32 regValue;
362
363 if( (retVal = rtl8367c_setAsicReg(0x13c2, 0x0249)) != RT_ERR_OK)
364 return retVal;
365
366 if( (retVal = rtl8367c_getAsicReg(0x1301, &regValue)) != RT_ERR_OK)
367 return retVal;
368
369 if( (retVal = rtl8367c_setAsicReg(0x13c2, 0x0000)) != RT_ERR_OK)
370 return retVal;
371
372 RTK_SCAN_ALL_LOG_PORT(port)
373 {
374 if(rtk_switch_isUtpPort(port) == RT_ERR_OK)
375 {
376 if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_PORT0_EEECFG + (0x20 * port), RTL8367C_PORT0_EEECFG_EEE_100M_OFFSET, 1)) != RT_ERR_OK)
377 return retVal;
378
379 if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_PORT0_EEECFG + (0x20 * port), RTL8367C_PORT0_EEECFG_EEE_GIGA_500M_OFFSET, 1)) != RT_ERR_OK)
380 return retVal;
381
382 if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_PORT0_EEECFG + (0x20 * port), RTL8367C_PORT0_EEECFG_EEE_TX_OFFSET, 1)) != RT_ERR_OK)
383 return retVal;
384
385 if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_PORT0_EEECFG + (0x20 * port), RTL8367C_PORT0_EEECFG_EEE_RX_OFFSET, 1)) != RT_ERR_OK)
386 return retVal;
387
388 if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xA428, &regData)) != RT_ERR_OK)
389 return retVal;
390
391 regData &= ~(0x0200);
392 if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xA428, regData)) != RT_ERR_OK)
393 return retVal;
394
395 if((regValue & 0x00F0) == 0x00A0)
396 {
397 if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xA5D0, &regData)) != RT_ERR_OK)
398 return retVal;
399
400 regData |= 0x0006;
401 if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xA5D0, regData)) != RT_ERR_OK)
402 return retVal;
403 }
404 }
405 }
406
407 if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_UTP_FIB_DET, 0x15BB)) != RT_ERR_OK)
408 return retVal;
409
410 if((retVal = rtl8367c_setAsicReg(0x1303, 0x06D6)) != RT_ERR_OK)
411 return retVal;
412
413 if((retVal = rtl8367c_setAsicReg(0x1304, 0x0700)) != RT_ERR_OK)
414 return retVal;
415
416 if((retVal = rtl8367c_setAsicReg(0x13E2, 0x003F)) != RT_ERR_OK)
417 return retVal;
418
419 if((retVal = rtl8367c_setAsicReg(0x13F9, 0x0090)) != RT_ERR_OK)
420 return retVal;
421
422 if((retVal = rtl8367c_setAsicReg(0x121e, 0x03CA)) != RT_ERR_OK)
423 return retVal;
424
425 if((retVal = rtl8367c_setAsicReg(0x1233, 0x0352)) != RT_ERR_OK)
426 return retVal;
427
428 if((retVal = rtl8367c_setAsicReg(0x1237, 0x00a0)) != RT_ERR_OK)
429 return retVal;
430
431 if((retVal = rtl8367c_setAsicReg(0x123a, 0x0030)) != RT_ERR_OK)
432 return retVal;
433
434 if((retVal = rtl8367c_setAsicReg(0x1239, 0x0084)) != RT_ERR_OK)
435 return retVal;
436
437 if((retVal = rtl8367c_setAsicReg(0x0301, 0x1000)) != RT_ERR_OK)
438 return retVal;
439
440 if((retVal = rtl8367c_setAsicReg(0x1349, 0x001F)) != RT_ERR_OK)
441 return retVal;
442
443 if((retVal = rtl8367c_setAsicRegBit(0x18e0, 0, 0)) != RT_ERR_OK)
444 return retVal;
445
446 if((retVal = rtl8367c_setAsicRegBit(0x122b, 14, 1)) != RT_ERR_OK)
447 return retVal;
448
449 if((retVal = rtl8367c_setAsicRegBits(0x1305, 0xC000, 3)) != RT_ERR_OK)
450 return retVal;
451
452 return RT_ERR_OK;
453 }
454
455 static rtk_api_ret_t _rtk_switch_init_8370b(void)
456 {
457 ret_t retVal;
458 rtk_uint32 regData, tmp = 0;
459 rtk_uint32 i, prf, counter;
460 rtk_uint32 long_link[8] = {0x0210, 0x03e8, 0x0218, 0x03f0, 0x0220, 0x03f8, 0x0208, 0x03e0 };
461
462 if((retVal = rtl8367c_setAsicRegBits(0x1205, 0x0300, 3)) != RT_ERR_OK)
463 return retVal;
464
465
466 for(i=0; i<8; i++)
467 {
468 if ((retVal = rtl8367c_getAsicPHYOCPReg(i, 0xa420, &regData)) != RT_ERR_OK)
469 return retVal;
470 tmp = regData & 0x7 ;
471 if(tmp == 0x3)
472 {
473 prf = 1;
474 if((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xb83e, 0x6fa9)) != RT_ERR_OK)
475 return retVal;
476 if((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xb840, 0xa9)) != RT_ERR_OK)
477 return retVal;
478 for(counter = 0; counter < 10000; counter++); //delay
479
480 if ((retVal = rtl8367c_getAsicPHYOCPReg(i, 0xb820, &regData)) != RT_ERR_OK)
481 return retVal;
482 tmp = regData | 0x10;
483 if ((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xb820, tmp)) != RT_ERR_OK)
484 return retVal;
485 for(counter = 0; counter < 10000; counter++); //delay
486 counter = 0;
487 do{
488 counter = counter + 1;
489 if ((retVal = rtl8367c_getAsicPHYOCPReg(i, 0xb800, &regData)) != RT_ERR_OK)
490 return retVal;
491 tmp = regData & 0x40;
492 if(tmp != 0)
493 break;
494 } while (counter < 20); //Wait for patch ready = 1...
495 }
496 }
497 if ((retVal = rtl8367c_getAsicReg(0x1d01, &regData)) != RT_ERR_OK)
498 return retVal;
499 tmp = regData;
500 tmp = tmp | 0x3BE0; /*Broadcast port enable*/
501 tmp = tmp & 0xFFE0; /*Phy_id = 0 */
502 if((retVal = rtl8367c_setAsicReg(0x1d01, tmp)) != RT_ERR_OK)
503 return retVal;
504
505 for(i=0;i < 210; i++)
506 {
507 if((retVal = rtl8367c_setAsicPHYOCPReg(0, PatchChipData[i][0], PatchChipData[i][1])) != RT_ERR_OK)
508 return retVal;
509 }
510
511 if((retVal = rtl8367c_setAsicReg(0x1d01, regData)) != RT_ERR_OK)
512 return retVal;
513
514 for(i=0; i < 8; i++)
515 {
516 if((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xa4b4, long_link[i])) != RT_ERR_OK)
517 return retVal;
518 }
519
520 if (prf == 0x1)
521 {
522 for(i=0; i<8; i++)
523 {
524 if ((retVal = rtl8367c_getAsicPHYOCPReg(i, 0xb820, &regData)) != RT_ERR_OK)
525 return retVal;
526 tmp = regData & 0xFFEF;
527 if ((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xb820, tmp)) != RT_ERR_OK)
528 return retVal;
529
530 for(counter = 0; counter < 10000; counter++); //delay
531
532 counter = 0;
533 do{
534 counter = counter + 1;
535 if ((retVal = rtl8367c_getAsicPHYOCPReg(i, 0xb800, &regData)) != RT_ERR_OK)
536 return retVal;
537 tmp = regData & 0x40;
538 if( tmp == 0 )
539 break;
540 } while (counter < 20); //Wait for patch ready = 1...
541 if ((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xb83e, 0x6f48)) != RT_ERR_OK)
542 return retVal;
543 if ((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xb840, 0xfa)) != RT_ERR_OK)
544 return retVal;
545 }
546 }
547
548 /*Check phy link status*/
549 for(i=0; i<8; i++)
550 {
551 if ((retVal = rtl8367c_getAsicPHYOCPReg(i, 0xa400, &regData)) != RT_ERR_OK)
552 return retVal;
553 tmp = regData & 0x800;
554 if(tmp == 0x0)
555 {
556 tmp = regData | 0x200;
557 if ((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xa400, tmp)) != RT_ERR_OK)
558 return retVal;
559 }
560 }
561
562 for(counter = 0; counter < 10000; counter++); //delay
563
564 return RT_ERR_OK;
565 }
566
567 static rtk_api_ret_t _rtk_switch_init_8364b(void)
568 {
569 ret_t retVal;
570 rtk_uint32 regData;
571
572 /*enable EEE, include mac & phy*/
573
574 if ((retVal = rtl8367c_setAsicRegBits(0x38, 0x300, 3)) != RT_ERR_OK)
575 return retVal;
576 if ((retVal = rtl8367c_setAsicRegBits(0x78, 0x300, 3)) != RT_ERR_OK)
577 return retVal;
578 if ((retVal = rtl8367c_setAsicRegBits(0xd8, 0x300, 0)) != RT_ERR_OK)
579 return retVal;
580 if ((retVal = rtl8367c_setAsicRegBits(0xf8, 0x300, 0)) != RT_ERR_OK)
581 return retVal;
582
583 if ((retVal = rtl8367c_setAsicPHYOCPReg(1, 0xa5d0, 6)) != RT_ERR_OK)
584 return retVal;
585 if ((retVal = rtl8367c_setAsicPHYOCPReg(3, 0xa5d0, 6)) != RT_ERR_OK)
586 return retVal;
587
588 /*PAD para*/
589
590 /*EXT1 PAD Para*/
591 if ((retVal = rtl8367c_getAsicReg(0x1303, &regData)) != RT_ERR_OK)
592 return retVal;
593 regData &= 0xFFFFFFFE;
594 regData |= 0x250;
595 if((retVal = rtl8367c_setAsicReg(0x1303, regData)) != RT_ERR_OK)
596 return retVal;
597
598 if ((retVal = rtl8367c_setAsicRegBits(0x1304, 0x7000, 0)) != RT_ERR_OK)
599 return retVal;
600 if ((retVal = rtl8367c_setAsicRegBits(0x1304, 0x700, 7)) != RT_ERR_OK)
601 return retVal;
602 if ((retVal = rtl8367c_setAsicRegBits(0x13f9, 0x38, 0)) != RT_ERR_OK)
603 return retVal;
604
605 /*EXT2 PAD Para*/
606 if ((retVal = rtl8367c_setAsicRegBit(0x1303, 10, 1)) != RT_ERR_OK)
607 return retVal;
608 if ((retVal = rtl8367c_setAsicRegBits(0x13E2, 0x1ff, 0x26)) != RT_ERR_OK)
609 return retVal;
610 if ((retVal = rtl8367c_setAsicRegBits(0x13f9, 0x1c0, 0)) != RT_ERR_OK)
611 return retVal;
612
613
614 /*SDS PATCH*/
615 /*SP_CFG_EN_LINK_FIB1G*/
616 if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &regData)) != RT_ERR_OK)
617 return retVal;
618 regData |= 0x4;
619 if((retVal = rtl8367c_setAsicSdsReg(0,4,0, regData)) != RT_ERR_OK)
620 return retVal;
621
622 /*FIB100 Down-speed*/
623 if((retVal = rtl8367c_getAsicSdsReg(0, 1, 0, &regData)) != RT_ERR_OK)
624 return retVal;
625 regData |= 0x20;
626 if((retVal = rtl8367c_setAsicSdsReg(0,1,0, regData)) != RT_ERR_OK)
627 return retVal;
628
629 return RT_ERR_OK;
630 }
631
632 static rtk_api_ret_t _rtk_switch_init_8363sc_vb(void)
633 {
634
635 ret_t retVal;
636 rtk_uint32 regData;
637
638 /*enable EEE, include mac & phy*/
639
640 if ((retVal = rtl8367c_setAsicRegBits(0x38, 0x300, 3)) != RT_ERR_OK)
641 return retVal;
642 if ((retVal = rtl8367c_setAsicRegBits(0x78, 0x300, 3)) != RT_ERR_OK)
643 return retVal;
644 if ((retVal = rtl8367c_setAsicRegBits(0xd8, 0x300, 0)) != RT_ERR_OK)
645 return retVal;
646 if ((retVal = rtl8367c_setAsicRegBits(0xf8, 0x300, 0)) != RT_ERR_OK)
647 return retVal;
648
649 if ((retVal = rtl8367c_setAsicPHYOCPReg(1, 0xa5d0, 6)) != RT_ERR_OK)
650 return retVal;
651 if ((retVal = rtl8367c_setAsicPHYOCPReg(3, 0xa5d0, 6)) != RT_ERR_OK)
652 return retVal;
653
654 /*PAD para*/
655
656 /*EXT1 PAD Para*/
657 if ((retVal = rtl8367c_getAsicReg(0x1303, &regData)) != RT_ERR_OK)
658 return retVal;
659 regData &= 0xFFFFFFFE;
660 regData |= 0x250;
661 if((retVal = rtl8367c_setAsicReg(0x1303, regData)) != RT_ERR_OK)
662 return retVal;
663
664 if ((retVal = rtl8367c_setAsicRegBits(0x1304, 0x7000, 0)) != RT_ERR_OK)
665 return retVal;
666 if ((retVal = rtl8367c_setAsicRegBits(0x1304, 0x700, 7)) != RT_ERR_OK)
667 return retVal;
668 if ((retVal = rtl8367c_setAsicRegBits(0x13f9, 0x38, 0)) != RT_ERR_OK)
669 return retVal;
670
671 /*EXT2 PAD Para*/
672 if ((retVal = rtl8367c_setAsicRegBit(0x1303, 10, 1)) != RT_ERR_OK)
673 return retVal;
674 if ((retVal = rtl8367c_setAsicRegBits(0x13E2, 0x1ff, 0x26)) != RT_ERR_OK)
675 return retVal;
676 if ((retVal = rtl8367c_setAsicRegBits(0x13f9, 0x1c0, 0)) != RT_ERR_OK)
677 return retVal;
678
679
680 /*SDS PATCH*/
681 /*SP_CFG_EN_LINK_FIB1G*/
682 if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &regData)) != RT_ERR_OK)
683 return retVal;
684 regData |= 0x4;
685 if((retVal = rtl8367c_setAsicSdsReg(0,4,0, regData)) != RT_ERR_OK)
686 return retVal;
687
688 /*FIB100 Down-speed*/
689 if((retVal = rtl8367c_getAsicSdsReg(0, 1, 0, &regData)) != RT_ERR_OK)
690 return retVal;
691 regData |= 0x20;
692 if((retVal = rtl8367c_setAsicSdsReg(0,1,0, regData)) != RT_ERR_OK)
693 return retVal;
694
695 return RT_ERR_OK;
696 }
697
698 /* Function Name:
699 * rtk_switch_probe
700 * Description:
701 * Probe switch
702 * Input:
703 * None
704 * Output:
705 * None
706 * Return:
707 * RT_ERR_OK - Switch probed
708 * RT_ERR_FAILED - Switch Unprobed.
709 * Note:
710 *
711 */
712 rtk_api_ret_t rtk_switch_probe(switch_chip_t *pSwitchChip)
713 {
714 #if defined(FORCE_PROBE_RTL8367C)
715
716 *pSwitchChip = CHIP_RTL8367C;
717 halCtrl = &rtl8367c_hal_Ctrl;
718
719 #elif defined(FORCE_PROBE_RTL8370B)
720
721 *pSwitchChip = CHIP_RTL8370B;
722 halCtrl = &rtl8370b_hal_Ctrl;
723
724 #elif defined(FORCE_PROBE_RTL8364B)
725
726 *pSwitchChip = CHIP_RTL8364B;
727 halCtrl = &rtl8364b_hal_Ctrl;
728
729 #elif defined(FORCE_PROBE_RTL8363SC_VB)
730
731 *pSwitchChip = CHIP_RTL8363SC_VB;
732 halCtrl = &rtl8363sc_vb_hal_Ctrl;
733
734 #else
735 rtk_uint32 retVal;
736 rtk_uint32 data, regValue;
737
738 if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)
739 return retVal;
740
741 if((retVal = rtl8367c_getAsicReg(0x1300, &data)) != RT_ERR_OK)
742 return retVal;
743
744 if((retVal = rtl8367c_getAsicReg(0x1301, &regValue)) != RT_ERR_OK)
745 return retVal;
746
747 if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK)
748 return retVal;
749
750 switch (data)
751 {
752 case 0x0276:
753 case 0x0597:
754 case 0x6367:
755 *pSwitchChip = CHIP_RTL8367C;
756 halCtrl = &rtl8367c_hal_Ctrl;
757 break;
758 case 0x0652:
759 case 0x6368:
760 *pSwitchChip = CHIP_RTL8370B;
761 halCtrl = &rtl8370b_hal_Ctrl;
762 break;
763 case 0x0801:
764 case 0x6511:
765 if( (regValue & 0x00F0) == 0x0080)
766 {
767 *pSwitchChip = CHIP_RTL8363SC_VB;
768 halCtrl = &rtl8363sc_vb_hal_Ctrl;
769 }
770 else
771 {
772 *pSwitchChip = CHIP_RTL8364B;
773 halCtrl = &rtl8364b_hal_Ctrl;
774 }
775 break;
776 default:
777 return RT_ERR_FAILED;
778 }
779 #endif
780
781 return RT_ERR_OK;
782 }
783
784 /* Function Name:
785 * rtk_switch_initialState_set
786 * Description:
787 * Set initial status
788 * Input:
789 * state - Initial state;
790 * Output:
791 * None
792 * Return:
793 * RT_ERR_OK - Initialized
794 * RT_ERR_FAILED - Uninitialized
795 * Note:
796 *
797 */
798 rtk_api_ret_t rtk_switch_initialState_set(init_state_t state)
799 {
800 if(state >= INIT_STATE_END)
801 return RT_ERR_FAILED;
802
803 init_state = state;
804 return RT_ERR_OK;
805 }
806
807 /* Function Name:
808 * rtk_switch_initialState_get
809 * Description:
810 * Get initial status
811 * Input:
812 * None
813 * Output:
814 * None
815 * Return:
816 * INIT_COMPLETED - Initialized
817 * INIT_NOT_COMPLETED - Uninitialized
818 * Note:
819 *
820 */
821 init_state_t rtk_switch_initialState_get(void)
822 {
823 return init_state;
824 }
825
826 /* Function Name:
827 * rtk_switch_logicalPortCheck
828 * Description:
829 * Check logical port ID.
830 * Input:
831 * logicalPort - logical port ID
832 * Output:
833 * None
834 * Return:
835 * RT_ERR_OK - Port ID is correct
836 * RT_ERR_FAILED - Port ID is not correct
837 * RT_ERR_NOT_INIT - Not Initialize
838 * Note:
839 *
840 */
841 rtk_api_ret_t rtk_switch_logicalPortCheck(rtk_port_t logicalPort)
842 {
843 if(init_state != INIT_COMPLETED)
844 return RT_ERR_NOT_INIT;
845
846 if(logicalPort >= RTK_SWITCH_PORT_NUM)
847 return RT_ERR_FAILED;
848
849 if(halCtrl->l2p_port[logicalPort] == 0xFF)
850 return RT_ERR_FAILED;
851
852 return RT_ERR_OK;
853 }
854
855 /* Function Name:
856 * rtk_switch_isUtpPort
857 * Description:
858 * Check is logical port a UTP port
859 * Input:
860 * logicalPort - logical port ID
861 * Output:
862 * None
863 * Return:
864 * RT_ERR_OK - Port ID is a UTP port
865 * RT_ERR_FAILED - Port ID is not a UTP port
866 * RT_ERR_NOT_INIT - Not Initialize
867 * Note:
868 *
869 */
870 rtk_api_ret_t rtk_switch_isUtpPort(rtk_port_t logicalPort)
871 {
872 if(init_state != INIT_COMPLETED)
873 return RT_ERR_NOT_INIT;
874
875 if(logicalPort >= RTK_SWITCH_PORT_NUM)
876 return RT_ERR_FAILED;
877
878 if(halCtrl->log_port_type[logicalPort] == UTP_PORT)
879 return RT_ERR_OK;
880 else
881 return RT_ERR_FAILED;
882 }
883
884 /* Function Name:
885 * rtk_switch_isExtPort
886 * Description:
887 * Check is logical port a Extension port
888 * Input:
889 * logicalPort - logical port ID
890 * Output:
891 * None
892 * Return:
893 * RT_ERR_OK - Port ID is a EXT port
894 * RT_ERR_FAILED - Port ID is not a EXT port
895 * RT_ERR_NOT_INIT - Not Initialize
896 * Note:
897 *
898 */
899 rtk_api_ret_t rtk_switch_isExtPort(rtk_port_t logicalPort)
900 {
901 if(init_state != INIT_COMPLETED)
902 return RT_ERR_NOT_INIT;
903
904 if(logicalPort >= RTK_SWITCH_PORT_NUM)
905 return RT_ERR_FAILED;
906
907 if(halCtrl->log_port_type[logicalPort] == EXT_PORT)
908 return RT_ERR_OK;
909 else
910 return RT_ERR_FAILED;
911 }
912
913
914 /* Function Name:
915 * rtk_switch_isHsgPort
916 * Description:
917 * Check is logical port a HSG port
918 * Input:
919 * logicalPort - logical port ID
920 * Output:
921 * None
922 * Return:
923 * RT_ERR_OK - Port ID is a HSG port
924 * RT_ERR_FAILED - Port ID is not a HSG port
925 * RT_ERR_NOT_INIT - Not Initialize
926 * Note:
927 *
928 */
929 rtk_api_ret_t rtk_switch_isHsgPort(rtk_port_t logicalPort)
930 {
931 if(init_state != INIT_COMPLETED)
932 return RT_ERR_NOT_INIT;
933
934 if(logicalPort >= RTK_SWITCH_PORT_NUM)
935 return RT_ERR_FAILED;
936
937 if(logicalPort == halCtrl->hsg_logical_port)
938 return RT_ERR_OK;
939 else
940 return RT_ERR_FAILED;
941 }
942
943 /* Function Name:
944 * rtk_switch_isSgmiiPort
945 * Description:
946 * Check is logical port a SGMII port
947 * Input:
948 * logicalPort - logical port ID
949 * Output:
950 * None
951 * Return:
952 * RT_ERR_OK - Port ID is a SGMII port
953 * RT_ERR_FAILED - Port ID is not a SGMII port
954 * RT_ERR_NOT_INIT - Not Initialize
955 * Note:
956 *
957 */
958 rtk_api_ret_t rtk_switch_isSgmiiPort(rtk_port_t logicalPort)
959 {
960 if(init_state != INIT_COMPLETED)
961 return RT_ERR_NOT_INIT;
962
963 if(logicalPort >= RTK_SWITCH_PORT_NUM)
964 return RT_ERR_FAILED;
965
966 if( ((0x01 << logicalPort) & halCtrl->sg_logical_portmask) != 0)
967 return RT_ERR_OK;
968 else
969 return RT_ERR_FAILED;
970 }
971
972 /* Function Name:
973 * rtk_switch_isCPUPort
974 * Description:
975 * Check is logical port a CPU port
976 * Input:
977 * logicalPort - logical port ID
978 * Output:
979 * None
980 * Return:
981 * RT_ERR_OK - Port ID is a CPU port
982 * RT_ERR_FAILED - Port ID is not a CPU port
983 * RT_ERR_NOT_INIT - Not Initialize
984 * Note:
985 *
986 */
987 rtk_api_ret_t rtk_switch_isCPUPort(rtk_port_t logicalPort)
988 {
989 if(init_state != INIT_COMPLETED)
990 return RT_ERR_NOT_INIT;
991
992 if(logicalPort >= RTK_SWITCH_PORT_NUM)
993 return RT_ERR_FAILED;
994
995 if( ((0x01 << logicalPort) & halCtrl->valid_cpu_portmask) != 0)
996 return RT_ERR_OK;
997 else
998 return RT_ERR_FAILED;
999 }
1000
1001 /* Function Name:
1002 * rtk_switch_isComboPort
1003 * Description:
1004 * Check is logical port a Combo port
1005 * Input:
1006 * logicalPort - logical port ID
1007 * Output:
1008 * None
1009 * Return:
1010 * RT_ERR_OK - Port ID is a combo port
1011 * RT_ERR_FAILED - Port ID is not a combo port
1012 * RT_ERR_NOT_INIT - Not Initialize
1013 * Note:
1014 *
1015 */
1016 rtk_api_ret_t rtk_switch_isComboPort(rtk_port_t logicalPort)
1017 {
1018 if(init_state != INIT_COMPLETED)
1019 return RT_ERR_NOT_INIT;
1020
1021 if(logicalPort >= RTK_SWITCH_PORT_NUM)
1022 return RT_ERR_FAILED;
1023
1024 if(halCtrl->combo_logical_port == logicalPort)
1025 return RT_ERR_OK;
1026 else
1027 return RT_ERR_FAILED;
1028 }
1029
1030 /* Function Name:
1031 * rtk_switch_ComboPort_get
1032 * Description:
1033 * Get Combo port ID
1034 * Input:
1035 * None
1036 * Output:
1037 * None
1038 * Return:
1039 * Port ID of combo port
1040 * Note:
1041 *
1042 */
1043 rtk_uint32 rtk_switch_ComboPort_get(void)
1044 {
1045 return halCtrl->combo_logical_port;
1046 }
1047
1048 /* Function Name:
1049 * rtk_switch_isPtpPort
1050 * Description:
1051 * Check is logical port a PTP port
1052 * Input:
1053 * logicalPort - logical port ID
1054 * Output:
1055 * None
1056 * Return:
1057 * RT_ERR_OK - Port ID is a PTP port
1058 * RT_ERR_FAILED - Port ID is not a PTP port
1059 * RT_ERR_NOT_INIT - Not Initialize
1060 * Note:
1061 *
1062 */
1063 rtk_api_ret_t rtk_switch_isPtpPort(rtk_port_t logicalPort)
1064 {
1065 if(init_state != INIT_COMPLETED)
1066 return RT_ERR_NOT_INIT;
1067
1068 if(logicalPort >= RTK_SWITCH_PORT_NUM)
1069 return RT_ERR_FAILED;
1070
1071 if(halCtrl->ptp_port[logicalPort] == 1)
1072 return RT_ERR_OK;
1073 else
1074 return RT_ERR_FAILED;
1075 }
1076
1077 /* Function Name:
1078 * rtk_switch_port_L2P_get
1079 * Description:
1080 * Get physical port ID
1081 * Input:
1082 * logicalPort - logical port ID
1083 * Output:
1084 * None
1085 * Return:
1086 * Physical port ID
1087 * Note:
1088 *
1089 */
1090 rtk_uint32 rtk_switch_port_L2P_get(rtk_port_t logicalPort)
1091 {
1092 if(init_state != INIT_COMPLETED)
1093 return UNDEFINE_PHY_PORT;
1094
1095 if(logicalPort >= RTK_SWITCH_PORT_NUM)
1096 return UNDEFINE_PHY_PORT;
1097
1098 return (halCtrl->l2p_port[logicalPort]);
1099 }
1100
1101 /* Function Name:
1102 * rtk_switch_port_P2L_get
1103 * Description:
1104 * Get logical port ID
1105 * Input:
1106 * physicalPort - physical port ID
1107 * Output:
1108 * None
1109 * Return:
1110 * logical port ID
1111 * Note:
1112 *
1113 */
1114 rtk_port_t rtk_switch_port_P2L_get(rtk_uint32 physicalPort)
1115 {
1116 if(init_state != INIT_COMPLETED)
1117 return UNDEFINE_PORT;
1118
1119 if(physicalPort >= RTK_SWITCH_PORT_NUM)
1120 return UNDEFINE_PORT;
1121
1122 return (halCtrl->p2l_port[physicalPort]);
1123 }
1124
1125 /* Function Name:
1126 * rtk_switch_isPortMaskValid
1127 * Description:
1128 * Check portmask is valid or not
1129 * Input:
1130 * pPmask - logical port mask
1131 * Output:
1132 * None
1133 * Return:
1134 * RT_ERR_OK - port mask is valid
1135 * RT_ERR_FAILED - port mask is not valid
1136 * RT_ERR_NOT_INIT - Not Initialize
1137 * RT_ERR_NULL_POINTER - Null pointer
1138 * Note:
1139 *
1140 */
1141 rtk_api_ret_t rtk_switch_isPortMaskValid(rtk_portmask_t *pPmask)
1142 {
1143 if(init_state != INIT_COMPLETED)
1144 return RT_ERR_NOT_INIT;
1145
1146 if(NULL == pPmask)
1147 return RT_ERR_NULL_POINTER;
1148
1149 if( (pPmask->bits[0] | halCtrl->valid_portmask) != halCtrl->valid_portmask )
1150 return RT_ERR_FAILED;
1151 else
1152 return RT_ERR_OK;
1153 }
1154
1155 /* Function Name:
1156 * rtk_switch_isPortMaskUtp
1157 * Description:
1158 * Check all ports in portmask are only UTP port
1159 * Input:
1160 * pPmask - logical port mask
1161 * Output:
1162 * None
1163 * Return:
1164 * RT_ERR_OK - Only UTP port in port mask
1165 * RT_ERR_FAILED - Not only UTP port in port mask
1166 * RT_ERR_NOT_INIT - Not Initialize
1167 * RT_ERR_NULL_POINTER - Null pointer
1168 * Note:
1169 *
1170 */
1171 rtk_api_ret_t rtk_switch_isPortMaskUtp(rtk_portmask_t *pPmask)
1172 {
1173 if(init_state != INIT_COMPLETED)
1174 return RT_ERR_NOT_INIT;
1175
1176 if(NULL == pPmask)
1177 return RT_ERR_NULL_POINTER;
1178
1179 if( (pPmask->bits[0] | halCtrl->valid_utp_portmask) != halCtrl->valid_utp_portmask )
1180 return RT_ERR_FAILED;
1181 else
1182 return RT_ERR_OK;
1183 }
1184
1185 /* Function Name:
1186 * rtk_switch_isPortMaskExt
1187 * Description:
1188 * Check all ports in portmask are only EXT port
1189 * Input:
1190 * pPmask - logical port mask
1191 * Output:
1192 * None
1193 * Return:
1194 * RT_ERR_OK - Only EXT port in port mask
1195 * RT_ERR_FAILED - Not only EXT port in port mask
1196 * RT_ERR_NOT_INIT - Not Initialize
1197 * RT_ERR_NULL_POINTER - Null pointer
1198 * Note:
1199 *
1200 */
1201 rtk_api_ret_t rtk_switch_isPortMaskExt(rtk_portmask_t *pPmask)
1202 {
1203 if(init_state != INIT_COMPLETED)
1204 return RT_ERR_NOT_INIT;
1205
1206 if(NULL == pPmask)
1207 return RT_ERR_NULL_POINTER;
1208
1209 if( (pPmask->bits[0] | halCtrl->valid_ext_portmask) != halCtrl->valid_ext_portmask )
1210 return RT_ERR_FAILED;
1211 else
1212 return RT_ERR_OK;
1213 }
1214
1215 /* Function Name:
1216 * rtk_switch_portmask_L2P_get
1217 * Description:
1218 * Get physicl portmask from logical portmask
1219 * Input:
1220 * pLogicalPmask - logical port mask
1221 * Output:
1222 * pPhysicalPortmask - physical port mask
1223 * Return:
1224 * RT_ERR_OK - OK
1225 * RT_ERR_NOT_INIT - Not Initialize
1226 * RT_ERR_NULL_POINTER - Null pointer
1227 * RT_ERR_PORT_MASK - Error port mask
1228 * Note:
1229 *
1230 */
1231 rtk_api_ret_t rtk_switch_portmask_L2P_get(rtk_portmask_t *pLogicalPmask, rtk_uint32 *pPhysicalPortmask)
1232 {
1233 rtk_uint32 log_port, phy_port;
1234
1235 if(init_state != INIT_COMPLETED)
1236 return RT_ERR_NOT_INIT;
1237
1238 if(NULL == pLogicalPmask)
1239 return RT_ERR_NULL_POINTER;
1240
1241 if(NULL == pPhysicalPortmask)
1242 return RT_ERR_NULL_POINTER;
1243
1244 if(rtk_switch_isPortMaskValid(pLogicalPmask) != RT_ERR_OK)
1245 return RT_ERR_PORT_MASK;
1246
1247 /* reset physical port mask */
1248 *pPhysicalPortmask = 0;
1249
1250 RTK_PORTMASK_SCAN((*pLogicalPmask), log_port)
1251 {
1252 phy_port = rtk_switch_port_L2P_get((rtk_port_t)log_port);
1253 *pPhysicalPortmask |= (0x0001 << phy_port);
1254 }
1255
1256 return RT_ERR_OK;
1257 }
1258
1259 /* Function Name:
1260 * rtk_switch_portmask_P2L_get
1261 * Description:
1262 * Get logical portmask from physical portmask
1263 * Input:
1264 * physicalPortmask - physical port mask
1265 * Output:
1266 * pLogicalPmask - logical port mask
1267 * Return:
1268 * RT_ERR_OK - OK
1269 * RT_ERR_NOT_INIT - Not Initialize
1270 * RT_ERR_NULL_POINTER - Null pointer
1271 * RT_ERR_PORT_MASK - Error port mask
1272 * Note:
1273 *
1274 */
1275 rtk_api_ret_t rtk_switch_portmask_P2L_get(rtk_uint32 physicalPortmask, rtk_portmask_t *pLogicalPmask)
1276 {
1277 rtk_uint32 log_port, phy_port;
1278
1279 if(init_state != INIT_COMPLETED)
1280 return RT_ERR_NOT_INIT;
1281
1282 if(NULL == pLogicalPmask)
1283 return RT_ERR_NULL_POINTER;
1284
1285 RTK_PORTMASK_CLEAR(*pLogicalPmask);
1286
1287 for(phy_port = halCtrl->min_phy_port; phy_port <= halCtrl->max_phy_port; phy_port++)
1288 {
1289 if(physicalPortmask & (0x0001 << phy_port))
1290 {
1291 log_port = rtk_switch_port_P2L_get(phy_port);
1292 if(log_port != UNDEFINE_PORT)
1293 {
1294 RTK_PORTMASK_PORT_SET(*pLogicalPmask, log_port);
1295 }
1296 }
1297 }
1298
1299 return RT_ERR_OK;
1300 }
1301
1302 /* Function Name:
1303 * rtk_switch_phyPortMask_get
1304 * Description:
1305 * Get physical portmask
1306 * Input:
1307 * None
1308 * Output:
1309 * None
1310 * Return:
1311 * 0x00 - Not Initialize
1312 * Other value - Physical port mask
1313 * Note:
1314 *
1315 */
1316 rtk_uint32 rtk_switch_phyPortMask_get(void)
1317 {
1318 if(init_state != INIT_COMPLETED)
1319 return 0x00; /* No port in portmask */
1320
1321 return (halCtrl->phy_portmask);
1322 }
1323
1324 /* Function Name:
1325 * rtk_switch_logPortMask_get
1326 * Description:
1327 * Get Logical portmask
1328 * Input:
1329 * None
1330 * Output:
1331 * None
1332 * Return:
1333 * RT_ERR_OK - OK
1334 * RT_ERR_NOT_INIT - Not Initialize
1335 * RT_ERR_NULL_POINTER - Null pointer
1336 * Note:
1337 *
1338 */
1339 rtk_api_ret_t rtk_switch_logPortMask_get(rtk_portmask_t *pPortmask)
1340 {
1341 if(init_state != INIT_COMPLETED)
1342 return RT_ERR_FAILED;
1343
1344 if(NULL == pPortmask)
1345 return RT_ERR_NULL_POINTER;
1346
1347 pPortmask->bits[0] = halCtrl->valid_portmask;
1348 return RT_ERR_OK;
1349 }
1350
1351 /* Function Name:
1352 * rtk_switch_init
1353 * Description:
1354 * Set chip to default configuration enviroment
1355 * Input:
1356 * None
1357 * Output:
1358 * None
1359 * Return:
1360 * RT_ERR_OK - OK
1361 * RT_ERR_FAILED - Failed
1362 * RT_ERR_SMI - SMI access error
1363 * Note:
1364 * The API can set chip registers to default configuration for different release chip model.
1365 */
1366 rtk_api_ret_t rtk_switch_init(void)
1367 {
1368 rtk_uint32 retVal;
1369 rtl8367c_rma_t rmaCfg;
1370 switch_chip_t switchChip;
1371
1372 /* probe switch */
1373 if((retVal = rtk_switch_probe(&switchChip)) != RT_ERR_OK)
1374 return retVal;
1375
1376 /* Set initial state */
1377
1378 if((retVal = rtk_switch_initialState_set(INIT_COMPLETED)) != RT_ERR_OK)
1379 return retVal;
1380
1381 /* Initial */
1382 switch(switchChip)
1383 {
1384 case CHIP_RTL8367C:
1385 if((retVal = _rtk_switch_init_8367c()) != RT_ERR_OK)
1386 return retVal;
1387 break;
1388 case CHIP_RTL8370B:
1389 if((retVal = _rtk_switch_init_8370b()) != RT_ERR_OK)
1390 return retVal;
1391 break;
1392 case CHIP_RTL8364B:
1393 if((retVal = _rtk_switch_init_8364b()) != RT_ERR_OK)
1394 return retVal;
1395 break;
1396 case CHIP_RTL8363SC_VB:
1397 if((retVal = _rtk_switch_init_8363sc_vb()) != RT_ERR_OK)
1398 return retVal;
1399 break;
1400 default:
1401 return RT_ERR_CHIP_NOT_FOUND;
1402 }
1403
1404 /* Set Old max packet length to 16K */
1405 if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_MAX_LENGTH_LIMINT_IPG, RTL8367C_MAX_LENTH_CTRL_MASK, 3)) != RT_ERR_OK)
1406 return retVal;
1407
1408 if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_MAX_LEN_RX_TX, RTL8367C_MAX_LEN_RX_TX_MASK, 3)) != RT_ERR_OK)
1409 return retVal;
1410
1411 /* ACL Mode */
1412 if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_ACL_ACCESS_MODE, RTL8367C_ACL_ACCESS_MODE_MASK, 1)) != RT_ERR_OK)
1413 return retVal;
1414
1415 /* Max rate */
1416 if((retVal = rtk_rate_igrBandwidthCtrlRate_set(halCtrl->hsg_logical_port, RTL8367C_QOS_RATE_INPUT_MAX_HSG, DISABLED, ENABLED)) != RT_ERR_OK)
1417 return retVal;
1418
1419 if((retVal = rtk_rate_egrBandwidthCtrlRate_set(halCtrl->hsg_logical_port, RTL8367C_QOS_RATE_INPUT_MAX_HSG, ENABLED)) != RT_ERR_OK)
1420 return retVal;
1421
1422 if((retVal = rtl8367c_setAsicReg(0x03fa, 0x0007)) != RT_ERR_OK)
1423 return retVal;
1424
1425 /* Change unknown DA to per port setting */
1426 if((retVal = rtl8367c_setAsicRegBits(RTL8367C_PORT_SECURIT_CTRL_REG, RTL8367C_UNKNOWN_UNICAST_DA_BEHAVE_MASK, 3)) != RT_ERR_OK)
1427 return retVal;
1428
1429 /* LUT lookup OP = 1 */
1430 if ((retVal = rtl8367c_setAsicLutIpLookupMethod(1))!=RT_ERR_OK)
1431 return retVal;
1432
1433 /* Set RMA */
1434 rmaCfg.portiso_leaky = 0;
1435 rmaCfg.vlan_leaky = 0;
1436 rmaCfg.keep_format = 0;
1437 rmaCfg.trap_priority = 0;
1438 rmaCfg.discard_storm_filter = 0;
1439 rmaCfg.operation = 0;
1440 if ((retVal = rtl8367c_setAsicRma(2, &rmaCfg))!=RT_ERR_OK)
1441 return retVal;
1442
1443 /* Enable TX Mirror isolation leaky */
1444 if ((retVal = rtl8367c_setAsicPortMirrorIsolationTxLeaky(ENABLED)) != RT_ERR_OK)
1445 return retVal;
1446
1447 /* INT EN */
1448 if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_IO_MISC_FUNC, RTL8367C_INT_EN_OFFSET, 1)) != RT_ERR_OK)
1449 return retVal;
1450
1451 return RT_ERR_OK;
1452 }
1453
1454 /* Function Name:
1455 * rtk_switch_portMaxPktLen_set
1456 * Description:
1457 * Set Max packet length
1458 * Input:
1459 * port - Port ID
1460 * speed - Speed
1461 * cfgId - Configuration ID
1462 * Output:
1463 * None.
1464 * Return:
1465 * RT_ERR_OK - OK
1466 * RT_ERR_FAILED - Failed
1467 * RT_ERR_SMI - SMI access error
1468 * RT_ERR_INPUT - Error Input
1469 * Note:
1470 */
1471 rtk_api_ret_t rtk_switch_portMaxPktLen_set(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 cfgId)
1472 {
1473 rtk_api_ret_t retVal;
1474
1475 /* Check initialization state */
1476 RTK_CHK_INIT_STATE();
1477
1478 /* Check Port Valid */
1479 RTK_CHK_PORT_VALID(port);
1480
1481 if(speed >= MAXPKTLEN_LINK_SPEED_END)
1482 return RT_ERR_INPUT;
1483
1484 if(cfgId > MAXPKTLEN_CFG_ID_MAX)
1485 return RT_ERR_INPUT;
1486
1487 if((retVal = rtl8367c_setAsicMaxLength(rtk_switch_port_L2P_get(port), (rtk_uint32)speed, cfgId)) != RT_ERR_OK)
1488 return retVal;
1489
1490 return RT_ERR_OK;
1491 }
1492
1493 /* Function Name:
1494 * rtk_switch_portMaxPktLen_get
1495 * Description:
1496 * Get Max packet length
1497 * Input:
1498 * port - Port ID
1499 * speed - Speed
1500 * Output:
1501 * pCfgId - Configuration ID
1502 * Return:
1503 * RT_ERR_OK - OK
1504 * RT_ERR_FAILED - Failed
1505 * RT_ERR_SMI - SMI access error
1506 * RT_ERR_INPUT - Error Input
1507 * Note:
1508 */
1509 rtk_api_ret_t rtk_switch_portMaxPktLen_get(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 *pCfgId)
1510 {
1511 rtk_api_ret_t retVal;
1512
1513 /* Check initialization state */
1514 RTK_CHK_INIT_STATE();
1515
1516 /* Check Port Valid */
1517 RTK_CHK_PORT_VALID(port);
1518
1519 if(speed >= MAXPKTLEN_LINK_SPEED_END)
1520 return RT_ERR_INPUT;
1521
1522 if(NULL == pCfgId)
1523 return RT_ERR_NULL_POINTER;
1524
1525 if((retVal = rtl8367c_getAsicMaxLength(rtk_switch_port_L2P_get(port), (rtk_uint32)speed, pCfgId)) != RT_ERR_OK)
1526 return retVal;
1527
1528 return RT_ERR_OK;
1529 }
1530
1531 /* Function Name:
1532 * rtk_switch_maxPktLenCfg_set
1533 * Description:
1534 * Set Max packet length configuration
1535 * Input:
1536 * cfgId - Configuration ID
1537 * pktLen - Max packet length
1538 * Output:
1539 * None.
1540 * Return:
1541 * RT_ERR_OK - OK
1542 * RT_ERR_FAILED - Failed
1543 * RT_ERR_SMI - SMI access error
1544 * RT_ERR_INPUT - Error Input
1545 * Note:
1546 */
1547 rtk_api_ret_t rtk_switch_maxPktLenCfg_set(rtk_uint32 cfgId, rtk_uint32 pktLen)
1548 {
1549 rtk_api_ret_t retVal;
1550
1551 /* Check initialization state */
1552 RTK_CHK_INIT_STATE();
1553
1554 if(cfgId > MAXPKTLEN_CFG_ID_MAX)
1555 return RT_ERR_INPUT;
1556
1557 if(pktLen > RTK_SWITCH_MAX_PKTLEN)
1558 return RT_ERR_INPUT;
1559
1560 if((retVal = rtl8367c_setAsicMaxLengthCfg(cfgId, pktLen)) != RT_ERR_OK)
1561 return retVal;
1562
1563 return RT_ERR_OK;
1564 }
1565
1566 /* Function Name:
1567 * rtk_switch_maxPktLenCfg_get
1568 * Description:
1569 * Get Max packet length configuration
1570 * Input:
1571 * cfgId - Configuration ID
1572 * pPktLen - Max packet length
1573 * Output:
1574 * None.
1575 * Return:
1576 * RT_ERR_OK - OK
1577 * RT_ERR_FAILED - Failed
1578 * RT_ERR_SMI - SMI access error
1579 * RT_ERR_INPUT - Error Input
1580 * Note:
1581 */
1582 rtk_api_ret_t rtk_switch_maxPktLenCfg_get(rtk_uint32 cfgId, rtk_uint32 *pPktLen)
1583 {
1584 rtk_api_ret_t retVal;
1585
1586 /* Check initialization state */
1587 RTK_CHK_INIT_STATE();
1588
1589 if(cfgId > MAXPKTLEN_CFG_ID_MAX)
1590 return RT_ERR_INPUT;
1591
1592 if(NULL == pPktLen)
1593 return RT_ERR_NULL_POINTER;
1594
1595 if((retVal = rtl8367c_getAsicMaxLengthCfg(cfgId, pPktLen)) != RT_ERR_OK)
1596 return retVal;
1597
1598 return RT_ERR_OK;
1599 }
1600
1601 /* Function Name:
1602 * rtk_switch_greenEthernet_set
1603 * Description:
1604 * Set all Ports Green Ethernet state.
1605 * Input:
1606 * enable - Green Ethernet state.
1607 * Output:
1608 * None
1609 * Return:
1610 * RT_ERR_OK - OK
1611 * RT_ERR_FAILED - Failed
1612 * RT_ERR_SMI - SMI access error
1613 * RT_ERR_ENABLE - Invalid enable input.
1614 * Note:
1615 * This API can set all Ports Green Ethernet state.
1616 * The configuration is as following:
1617 * - DISABLE
1618 * - ENABLE
1619 */
1620 rtk_api_ret_t rtk_switch_greenEthernet_set(rtk_enable_t enable)
1621 {
1622 rtk_api_ret_t retVal;
1623 rtk_uint32 port;
1624
1625 /* Check initialization state */
1626 RTK_CHK_INIT_STATE();
1627
1628 RTK_SCAN_ALL_LOG_PORT(port)
1629 {
1630 if(rtk_switch_isUtpPort(port) == RT_ERR_OK)
1631 {
1632 if ((retVal = rtl8367c_setAsicPowerSaving(rtk_switch_port_L2P_get(port),enable))!=RT_ERR_OK)
1633 return retVal;
1634
1635 if ((retVal = rtl8367c_setAsicGreenEthernet(rtk_switch_port_L2P_get(port), enable))!=RT_ERR_OK)
1636 return retVal;
1637 }
1638 }
1639
1640 return RT_ERR_OK;
1641 }
1642
1643 /* Function Name:
1644 * rtk_switch_greenEthernet_get
1645 * Description:
1646 * Get all Ports Green Ethernet state.
1647 * Input:
1648 * None
1649 * Output:
1650 * pEnable - Green Ethernet state.
1651 * Return:
1652 * RT_ERR_OK - OK
1653 * RT_ERR_FAILED - Failed
1654 * RT_ERR_SMI - SMI access error
1655 * Note:
1656 * This API can get Green Ethernet state.
1657 */
1658 rtk_api_ret_t rtk_switch_greenEthernet_get(rtk_enable_t *pEnable)
1659 {
1660 rtk_api_ret_t retVal;
1661 rtk_uint32 port;
1662 rtk_uint32 state;
1663
1664 /* Check initialization state */
1665 RTK_CHK_INIT_STATE();
1666
1667 RTK_SCAN_ALL_LOG_PORT(port)
1668 {
1669 if(rtk_switch_isUtpPort(port) == RT_ERR_OK)
1670 {
1671 if ((retVal = rtl8367c_getAsicPowerSaving(rtk_switch_port_L2P_get(port), &state))!=RT_ERR_OK)
1672 return retVal;
1673
1674 if(state == DISABLED)
1675 {
1676 *pEnable = DISABLED;
1677 return RT_ERR_OK;
1678 }
1679
1680 if ((retVal = rtl8367c_getAsicGreenEthernet(rtk_switch_port_L2P_get(port), &state))!=RT_ERR_OK)
1681 return retVal;
1682
1683 if(state == DISABLED)
1684 {
1685 *pEnable = DISABLED;
1686 return RT_ERR_OK;
1687 }
1688 }
1689 }
1690
1691 *pEnable = ENABLED;
1692 return RT_ERR_OK;
1693 }
1694
1695 /* Function Name:
1696 * rtk_switch_maxLogicalPort_get
1697 * Description:
1698 * Get Max logical port ID
1699 * Input:
1700 * None
1701 * Output:
1702 * None
1703 * Return:
1704 * Max logical port
1705 * Note:
1706 * This API can get max logical port
1707 */
1708 rtk_port_t rtk_switch_maxLogicalPort_get(void)
1709 {
1710 rtk_port_t port, maxLogicalPort = 0;
1711
1712 /* Check initialization state */
1713 if(rtk_switch_initialState_get() != INIT_COMPLETED)
1714 {
1715 return UNDEFINE_PORT;
1716 }
1717
1718 for(port = 0; port < RTK_SWITCH_PORT_NUM; port++)
1719 {
1720 if( (halCtrl->log_port_type[port] == UTP_PORT) || (halCtrl->log_port_type[port] == EXT_PORT) )
1721 maxLogicalPort = port;
1722 }
1723
1724 return maxLogicalPort;
1725 }
1726
1727 /* Function Name:
1728 * rtk_switch_maxMeterId_get
1729 * Description:
1730 * Get Max Meter ID
1731 * Input:
1732 * None
1733 * Output:
1734 * None
1735 * Return:
1736 * 0x00 - Not Initialize
1737 * Other value - Max Meter ID
1738 * Note:
1739 *
1740 */
1741 rtk_uint32 rtk_switch_maxMeterId_get(void)
1742 {
1743 if(init_state != INIT_COMPLETED)
1744 return 0x00;
1745
1746 return (halCtrl->max_meter_id);
1747 }
1748
1749 /* Function Name:
1750 * rtk_switch_maxLutAddrNumber_get
1751 * Description:
1752 * Get Max LUT Address number
1753 * Input:
1754 * None
1755 * Output:
1756 * None
1757 * Return:
1758 * 0x00 - Not Initialize
1759 * Other value - Max LUT Address number
1760 * Note:
1761 *
1762 */
1763 rtk_uint32 rtk_switch_maxLutAddrNumber_get(void)
1764 {
1765 if(init_state != INIT_COMPLETED)
1766 return 0x00;
1767
1768 return (halCtrl->max_lut_addr_num);
1769 }
1770
1771 /* Function Name:
1772 * rtk_switch_isValidTrunkGrpId
1773 * Description:
1774 * Check if trunk group is valid or not
1775 * Input:
1776 * grpId - Group ID
1777 * Output:
1778 * None
1779 * Return:
1780 * RT_ERR_OK - Trunk Group ID is valid
1781 * RT_ERR_LA_TRUNK_ID - Trunk Group ID is not valid
1782 * Note:
1783 *
1784 */
1785 rtk_uint32 rtk_switch_isValidTrunkGrpId(rtk_uint32 grpId)
1786 {
1787 if(init_state != INIT_COMPLETED)
1788 return 0x00;
1789
1790 if( (halCtrl->trunk_group_mask & (0x01 << grpId) ) != 0)
1791 return RT_ERR_OK;
1792 else
1793 return RT_ERR_LA_TRUNK_ID;
1794
1795 }
1796
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