target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts

   1 /*
   2  * Copyright (c) 2018 MediaTek Inc.
   3  * Author: Ryder Lee <ryder.lee@mediatek.com>
   4  *
   5  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   6  */
   7
   8 /dts-v1/;
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11
  12 #include "mt7622.dtsi"
  13 #include "mt6380.dtsi"
  14
  15 / {
  16         model = "Bananapi BPI-R64";
  17         compatible = "bananapi,bpi-r64-rootdisk", "mediatek,mt7622";
  18
  19         aliases {
  20                 serial0 = &uart0;
  21         };
  22
  23         chosen {
  24                 stdout-path = "serial0:115200n8";
  25                 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512 root=/dev/mmcblk0p7 rootfstype=squashfs,f2fs";
  26         };
  27
  28         cpus {
  29                 cpu@0 {
  30                         proc-supply = <&mt6380_vcpu_reg>;
  31                         sram-supply = <&mt6380_vm_reg>;
  32                 };
  33
  34                 cpu@1 {
  35                         proc-supply = <&mt6380_vcpu_reg>;
  36                         sram-supply = <&mt6380_vm_reg>;
  37                 };
  38         };
  39
  40         gpio-keys {
  41                 compatible = "gpio-keys";
  42
  43                 factory {
  44                         label = "factory";
  45                         linux,code = <BTN_0>;
  46                         gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
  47                 };
  48
  49                 wps {
  50                         label = "wps";
  51                         linux,code = <KEY_WPS_BUTTON>;
  52                         gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
  53                 };
  54         };
  55
  56         gsw: gsw@0 {
  57                 compatible = "mediatek,mt753x";
  58                 mediatek,ethsys = <&ethsys>;
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61         };
  62
  63         leds {
  64                 compatible = "gpio-leds";
  65
  66                 green {
  67                         label = "bpi-r64:pio:green";
  68                         gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
  69                         default-state = "off";
  70                 };
  71
  72                 red {
  73                         label = "bpi-r64:pio:red";
  74                         gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
  75                         default-state = "off";
  76                 };
  77         };
  78
  79         memory {
  80                 reg = <0 0x40000000 0 0x40000000>;
  81         };
  82
  83         reg_1p8v: regulator-1p8v {
  84                 compatible = "regulator-fixed";
  85                 regulator-name = "fixed-1.8V";
  86                 regulator-min-microvolt = <1800000>;
  87                 regulator-max-microvolt = <1800000>;
  88                 regulator-always-on;
  89         };
  90
  91         reg_3p3v: regulator-3p3v {
  92                 compatible = "regulator-fixed";
  93                 regulator-name = "fixed-3.3V";
  94                 regulator-min-microvolt = <3300000>;
  95                 regulator-max-microvolt = <3300000>;
  96                 regulator-boot-on;
  97                 regulator-always-on;
  98         };
  99
 100         reg_5v: regulator-5v {
 101                 compatible = "regulator-fixed";
 102                 regulator-name = "fixed-5V";
 103                 regulator-min-microvolt = <5000000>;
 104                 regulator-max-microvolt = <5000000>;
 105                 regulator-boot-on;
 106                 regulator-always-on;
 107         };
 108 };
 109
 110 &bch {
 111         status = "disabled";
 112 };
 113
 114 &btif {
 115         status = "okay";
 116 };
 117
 118 &cir {
 119         pinctrl-names = "default";
 120         pinctrl-0 = <&irrx_pins>;
 121         status = "okay";
 122 };
 123
 124 &eth {
 125         status = "okay";
 126         gmac0: mac@0 {
 127                 compatible = "mediatek,eth-mac";
 128                 reg = <0>;
 129                 phy-mode = "2500base-x";
 130
 131                 fixed-link {
 132                         speed = <2500>;
 133                         full-duplex;
 134                         pause;
 135                 };
 136         };
 137
 138         gmac1: mac@1 {
 139                 compatible = "mediatek,eth-mac";
 140                 reg = <1>;
 141                 phy-mode = "rgmii";
 142
 143                 fixed-link {
 144                         speed = <1000>;
 145                         full-duplex;
 146                         pause;
 147                 };
 148         };
 149
 150         mdio: mdio-bus {
 151                 #address-cells = <1>;
 152                 #size-cells = <0>;
 153         };
 154 };
 155
 156 &gsw {
 157         mediatek,mdio = <&mdio>;
 158         mediatek,portmap = "wllll";
 159         mediatek,mdio_master_pinmux = <0>;
 160         reset-gpios = <&pio 54 0>;
 161         interrupt-parent = <&pio>;
 162         interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
 163         status = "okay";
 164
 165         port5: port@5 {
 166                 compatible = "mediatek,mt753x-port";
 167                 reg = <5>;
 168                 phy-mode = "rgmii";
 169                 fixed-link {
 170                         speed = <1000>;
 171                         full-duplex;
 172                 };
 173         };
 174
 175         port6: port@6 {
 176                 compatible = "mediatek,mt753x-port";
 177                 reg = <6>;
 178                 phy-mode = "sgmii";
 179                 fixed-link {
 180                         speed = <2500>;
 181                         full-duplex;
 182                 };
 183         };
 184 };
 185
 186 &i2c1 {
 187         pinctrl-names = "default";
 188         pinctrl-0 = <&i2c1_pins>;
 189         status = "okay";
 190 };
 191
 192 &i2c2 {
 193         pinctrl-names = "default";
 194         pinctrl-0 = <&i2c2_pins>;
 195         status = "okay";
 196 };
 197
 198 &mmc0 {
 199         pinctrl-names = "default", "state_uhs";
 200         pinctrl-0 = <&emmc_pins_default>;
 201         pinctrl-1 = <&emmc_pins_uhs>;
 202         status = "okay";
 203         bus-width = <8>;
 204         max-frequency = <50000000>;
 205         cap-mmc-highspeed;
 206         mmc-hs200-1_8v;
 207         vmmc-supply = <&reg_3p3v>;
 208         vqmmc-supply = <&reg_1p8v>;
 209         assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
 210         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 211         non-removable;
 212 };
 213
 214 &mmc1 {
 215         pinctrl-names = "default", "state_uhs";
 216         pinctrl-0 = <&sd0_pins_default>;
 217         pinctrl-1 = <&sd0_pins_uhs>;
 218         status = "okay";
 219         bus-width = <4>;
 220         max-frequency = <50000000>;
 221         cap-sd-highspeed;
 222         r_smpl = <1>;
 223         cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 224         vmmc-supply = <&reg_3p3v>;
 225         vqmmc-supply = <&reg_3p3v>;
 226         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
 227         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 228 };
 229
 230 &nandc {
 231         pinctrl-names = "default";
 232         pinctrl-0 = <&parallel_nand_pins>;
 233         status = "disabled";
 234 };
 235
 236 &nor_flash {
 237         pinctrl-names = "default";
 238         pinctrl-0 = <&spi_nor_pins>;
 239         status = "disabled";
 240
 241         flash@0 {
 242                 compatible = "jedec,spi-nor";
 243                 reg = <0>;
 244         };
 245 };
 246
 247 &pcie {
 248         pinctrl-names = "default";
 249         pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
 250         status = "okay";
 251
 252         pcie@0,0 {
 253                 status = "okay";
 254         };
 255
 256         pcie@1,0 {
 257                 status = "okay";
 258         };
 259 };
 260
 261 &pio {
 262         /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
 263          * SATA functions. i.e. output-high: PCIe, output-low: SATA
 264          */
 265         asm_sel {
 266                 gpio-hog;
 267                 gpios = <90 GPIO_ACTIVE_HIGH>;
 268                 output-high;
 269         };
 270
 271         /* eMMC is shared pin with parallel NAND */
 272         emmc_pins_default: emmc-pins-default {
 273                 mux {
 274                         function = "emmc", "emmc_rst";
 275                         groups = "emmc";
 276                 };
 277
 278                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
 279                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
 280                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
 281                  */
 282                 conf-cmd-dat {
 283                         pins = "NDL0", "NDL1", "NDL2",
 284                                "NDL3", "NDL4", "NDL5",
 285                                "NDL6", "NDL7", "NRB";
 286                         input-enable;
 287                         bias-pull-up;
 288                 };
 289
 290                 conf-clk {
 291                         pins = "NCLE";
 292                         bias-pull-down;
 293                 };
 294         };
 295
 296         emmc_pins_uhs: emmc-pins-uhs {
 297                 mux {
 298                         function = "emmc";
 299                         groups = "emmc";
 300                 };
 301
 302                 conf-cmd-dat {
 303                         pins = "NDL0", "NDL1", "NDL2",
 304                                "NDL3", "NDL4", "NDL5",
 305                                "NDL6", "NDL7", "NRB";
 306                         input-enable;
 307                         drive-strength = <4>;
 308                         bias-pull-up;
 309                 };
 310
 311                 conf-clk {
 312                         pins = "NCLE";
 313                         drive-strength = <4>;
 314                         bias-pull-down;
 315                 };
 316         };
 317
 318         eth_pins: eth-pins {
 319                 mux {
 320                         function = "eth";
 321                         groups = "mdc_mdio", "rgmii_via_gmac2";
 322                 };
 323         };
 324
 325         i2c1_pins: i2c1-pins {
 326                 mux {
 327                         function = "i2c";
 328                         groups =  "i2c1_0";
 329                 };
 330         };
 331
 332         i2c2_pins: i2c2-pins {
 333                 mux {
 334                         function = "i2c";
 335                         groups =  "i2c2_0";
 336                 };
 337         };
 338
 339         i2s1_pins: i2s1-pins {
 340                 mux {
 341                         function = "i2s";
 342                         groups =  "i2s_out_mclk_bclk_ws",
 343                                   "i2s1_in_data",
 344                                   "i2s1_out_data";
 345                 };
 346
 347                 conf {
 348                         pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
 349                                "I2S_WS", "I2S_MCLK";
 350                         drive-strength = <12>;
 351                         bias-pull-down;
 352                 };
 353         };
 354
 355         irrx_pins: irrx-pins {
 356                 mux {
 357                         function = "ir";
 358                         groups =  "ir_1_rx";
 359                 };
 360         };
 361
 362         irtx_pins: irtx-pins {
 363                 mux {
 364                         function = "ir";
 365                         groups =  "ir_1_tx";
 366                 };
 367         };
 368
 369         /* Parallel nand is shared pin with eMMC */
 370         parallel_nand_pins: parallel-nand-pins {
 371                 mux {
 372                         function = "flash";
 373                         groups = "par_nand";
 374                 };
 375         };
 376
 377         pcie0_pins: pcie0-pins {
 378                 mux {
 379                         function = "pcie";
 380                         groups = "pcie0_pad_perst",
 381                                  "pcie0_1_waken",
 382                                  "pcie0_1_clkreq";
 383                 };
 384         };
 385
 386         pcie1_pins: pcie1-pins {
 387                 mux {
 388                         function = "pcie";
 389                         groups = "pcie1_pad_perst",
 390                                  "pcie1_0_waken",
 391                                  "pcie1_0_clkreq";
 392                 };
 393         };
 394
 395         pmic_bus_pins: pmic-bus-pins {
 396                 mux {
 397                         function = "pmic";
 398                         groups = "pmic_bus";
 399                 };
 400         };
 401
 402         pwm7_pins: pwm1-2-pins {
 403                 mux {
 404                         function = "pwm";
 405                         groups = "pwm_ch7_2";
 406                 };
 407         };
 408
 409         wled_pins: wled-pins {
 410                 mux {
 411                         function = "led";
 412                         groups = "wled";
 413                 };
 414         };
 415
 416         sd0_pins_default: sd0-pins-default {
 417                 mux {
 418                         function = "sd";
 419                         groups = "sd_0";
 420                 };
 421
 422                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 423                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 424                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 425                  */
 426                 conf-cmd-data {
 427                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 428                                "I2S2_IN","I2S4_OUT";
 429                         input-enable;
 430                         drive-strength = <8>;
 431                         bias-pull-up;
 432                 };
 433                 conf-clk {
 434                         pins = "I2S3_OUT";
 435                         drive-strength = <12>;
 436                         bias-pull-down;
 437                 };
 438                 conf-cd {
 439                         pins = "TXD3";
 440                         bias-pull-up;
 441                 };
 442         };
 443
 444         sd0_pins_uhs: sd0-pins-uhs {
 445                 mux {
 446                         function = "sd";
 447                         groups = "sd_0";
 448                 };
 449
 450                 conf-cmd-data {
 451                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 452                                "I2S2_IN","I2S4_OUT";
 453                         input-enable;
 454                         bias-pull-up;
 455                 };
 456
 457                 conf-clk {
 458                         pins = "I2S3_OUT";
 459                         bias-pull-down;
 460                 };
 461         };
 462
 463         /* Serial NAND is shared pin with SPI-NOR */
 464         serial_nand_pins: serial-nand-pins {
 465                 mux {
 466                         function = "flash";
 467                         groups = "snfi";
 468                 };
 469         };
 470
 471         spic0_pins: spic0-pins {
 472                 mux {
 473                         function = "spi";
 474                         groups = "spic0_0";
 475                 };
 476         };
 477
 478         spic1_pins: spic1-pins {
 479                 mux {
 480                         function = "spi";
 481                         groups = "spic1_0";
 482                 };
 483         };
 484
 485         /* SPI-NOR is shared pin with serial NAND */
 486         spi_nor_pins: spi-nor-pins {
 487                 mux {
 488                         function = "flash";
 489                         groups = "spi_nor";
 490                 };
 491         };
 492
 493         /* serial NAND is shared pin with SPI-NOR */
 494         serial_nand_pins: serial-nand-pins {
 495                 mux {
 496                         function = "flash";
 497                         groups = "snfi";
 498                 };
 499         };
 500
 501         uart0_pins: uart0-pins {
 502                 mux {
 503                         function = "uart";
 504                         groups = "uart0_0_tx_rx" ;
 505                 };
 506         };
 507
 508         uart2_pins: uart2-pins {
 509                 mux {
 510                         function = "uart";
 511                         groups = "uart2_1_tx_rx" ;
 512                 };
 513         };
 514
 515         watchdog_pins: watchdog-pins {
 516                 mux {
 517                         function = "watchdog";
 518                         groups = "watchdog";
 519                 };
 520         };
 521 };
 522
 523 &pwm {
 524         pinctrl-names = "default";
 525         pinctrl-0 = <&pwm7_pins>;
 526         status = "okay";
 527 };
 528
 529 &pwrap {
 530         pinctrl-names = "default";
 531         pinctrl-0 = <&pmic_bus_pins>;
 532
 533         status = "okay";
 534 };
 535
 536 &sata {
 537         status = "disable";
 538 };
 539
 540 &sata_phy {
 541         status = "disable";
 542 };
 543
 544 &spi0 {
 545         pinctrl-names = "default";
 546         pinctrl-0 = <&spic0_pins>;
 547         status = "okay";
 548 };
 549
 550 &spi1 {
 551         pinctrl-names = "default";
 552         pinctrl-0 = <&spic1_pins>;
 553         status = "okay";
 554 };
 555
 556 &ssusb {
 557         vusb33-supply = <&reg_3p3v>;
 558         vbus-supply = <&reg_5v>;
 559         status = "okay";
 560 };
 561
 562 &u3phy {
 563         status = "okay";
 564 };
 565
 566 &uart0 {
 567         pinctrl-names = "default";
 568         pinctrl-0 = <&uart0_pins>;
 569         status = "okay";
 570 };
 571
 572 &uart2 {
 573         pinctrl-names = "default";
 574         pinctrl-0 = <&uart2_pins>;
 575         status = "okay";
 576 };
 577
 578 &watchdog {
 579         pinctrl-names = "default";
 580         pinctrl-0 = <&watchdog_pins>;
 581         status = "okay";
 582 };