target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-topckgen.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2023 MediaTek Inc.
   4  * Author: Sam Shih <sam.shih@mediatek.com>
   5  * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
   6  */
   7
   8 #include <linux/clk-provider.h>
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include "clk-mtk.h"
  14 #include "clk-gate.h"
  15 #include "clk-mux.h"
  16 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
  17
  18 static DEFINE_SPINLOCK(mt7988_clk_lock);
  19
  20 static const struct mtk_fixed_clk top_fixed_clks[] = {
  21         FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
  22 };
  23
  24 static const struct mtk_fixed_factor top_divs[] = {
  25         FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
  26         FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
  27         FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
  28         FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),
  29         FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2),
  30         FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),
  31         FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8),
  32         FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16),
  33         FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
  34         FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15),
  35         FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
  36         FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),
  37         FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8),
  38         FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
  39         FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4),
  40         FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5),
  41         FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10),
  42         FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20),
  43         FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8),
  44         FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16),
  45         FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32),
  46         FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64),
  47         FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128),
  48         FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2),
  49         FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4),
  50         FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16),
  51         FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32),
  52         FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6),
  53         FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8),
  54 };
  55
  56 static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2",
  57                                               "mmpll_d2" };
  58
  59 static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5",
  60                                                    "net1pll_d5_d2" };
  61
  62 static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll",
  63                                                  "mmpll" };
  64
  65 static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4",
  66                                                   "net1pll_d5" };
  67
  68 static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" };
  69
  70 static const char *const netsys_mcu_parents[] = { "top_xtal",   "net2pll",
  71                                                   "mmpll",      "net1pll_d4",
  72                                                   "net1pll_d5", "mpll" };
  73
  74 static const char *const eip197_parents[] = { "top_xtal",   "netsyspll",
  75                                               "net2pll",    "mmpll",
  76                                               "net1pll_d4", "net1pll_d5" };
  77
  78 static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" };
  79
  80 static const char *const uart_parents[] = { "top_xtal", "mpll_d8",
  81                                             "mpll_d8_d2" };
  82
  83 static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2",
  84                                                  "mmpll_d4" };
  85
  86 static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll",
  87                                                  "mmpll_d2", "mpll_d2",
  88                                                  "mmpll_d4", "net1pll_d8_d2" };
  89
  90 static const char *const spi_parents[] = { "top_xtal",   "mpll_d2",
  91                                            "mmpll_d4",   "net1pll_d8_d2",
  92                                            "net2pll_d6", "net1pll_d5_d4",
  93                                            "mpll_d4",    "net1pll_d8_d4" };
  94
  95 static const char *const nfi1x_parents[] = { "top_xtal",      "mmpll_d4",
  96                                              "net1pll_d8_d2", "net2pll_d6",
  97                                              "mpll_d4",       "mmpll_d8",
  98                                              "net1pll_d8_d4", "mpll_d8" };
  99
 100 static const char *const spinfi_parents[] = { "top_xtal_d2",   "top_xtal",
 101                                               "net1pll_d5_d4", "mpll_d4",
 102                                               "mmpll_d8",      "net1pll_d8_d4",
 103                                               "mmpll_d6_d2",   "mpll_d8" };
 104
 105 static const char *const pwm_parents[] = { "top_xtal",      "net1pll_d8_d2",
 106                                            "net1pll_d5_d4", "mpll_d4",
 107                                            "mpll_d8_d2",    "top_rtc_32k" };
 108
 109 static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4",
 110                                            "mpll_d4", "net1pll_d8_d4" };
 111
 112 static const char *const pcie_mbist_250m_parents[] = { "top_xtal",
 113                                                        "net1pll_d5_d2" };
 114
 115 static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6",
 116                                                    "mmpll_d8", "mpll_d8_d2",
 117                                                    "top_rtc_32k" };
 118
 119 static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" };
 120
 121 static const char *const aud_parents[] = { "top_xtal", "apll2" };
 122
 123 static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" };
 124
 125 static const char *const aud_l_parents[] = { "top_xtal", "apll2",
 126                                              "mpll_d8_d2" };
 127
 128 static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" };
 129
 130 static const char *const usxgmii_sbus_0_parents[] = { "top_xtal",
 131                                                       "net1pll_d8_d4" };
 132
 133 static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" };
 134
 135 static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" };
 136
 137 static const char *const eth_refck_50m_parents[] = { "top_xtal",
 138                                                      "net2pll_d4_d4" };
 139
 140 static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" };
 141
 142 static const char *const eth_xgmii_parents[] = { "top_xtal_d2",
 143                                                  "net1pll_d8_d8",
 144                                                  "net1pll_d8_d16" };
 145
 146 static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5",
 147                                                 "net2pll_d2" };
 148
 149 static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" };
 150
 151 static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2",
 152                                                   "wedmcupll" };
 153
 154 static const char *const da_xtp_glb_p0_parents[] = { "top_xtal",
 155                                                      "net2pll_d8" };
 156
 157 static const char *const mcusys_backup_625m_parents[] = { "top_xtal",
 158                                                           "net1pll_d4" };
 159
 160 static const char *const macsec_parents[] = { "top_xtal", "sgmpll",
 161                                               "net1pll_d8" };
 162
 163 static const char *const netsys_tops_400m_parents[] = { "top_xtal",
 164                                                         "net2pll_d2" };
 165
 166 static const char *const eth_mii_parents[] = { "top_xtal_d2",
 167                                                "net2pll_d4_d8" };
 168
 169 static const struct mtk_mux top_muxes[] = {
 170         /* CLK_CFG_0 */
 171         MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
 172                              0x000, 0x004, 0x008, 0, 2, 7, 0x1c0, 0),
 173         MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
 174                              netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2,
 175                              15, 0x1C0, 1),
 176         MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
 177                              netsys_2x_parents, 0x000, 0x004, 0x008, 16, 2, 23,
 178                              0x1C0, 2),
 179         MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel",
 180                              netsys_gsw_parents, 0x000, 0x004, 0x008, 24, 2,
 181                              31, 0x1C0, 3),
 182         /* CLK_CFG_1 */
 183         MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel",
 184                              eth_gmii_parents, 0x010, 0x014, 0x018, 0, 1, 7,
 185                              0x1C0, 4),
 186         MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
 187                              netsys_mcu_parents, 0x010, 0x014, 0x018, 8, 3, 15,
 188                              0x1C0, 5),
 189         MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
 190                              netsys_mcu_parents, 0x010, 0x014, 0x018, 16, 3,
 191                              23, 0x1C0, 6),
 192         MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents,
 193                              0x010, 0x014, 0x018, 24, 3, 31, 0x1c0, 7),
 194         /* CLK_CFG_2 */
 195         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel",
 196                                    axi_infra_parents, 0x020, 0x024, 0x028, 0,
 197                                    1, 7, 0x1C0, 8, CLK_IS_CRITICAL),
 198         MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020,
 199                              0x024, 0x028, 8, 2, 15, 0x1c0, 9),
 200         MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
 201                              emmc_250m_parents, 0x020, 0x024, 0x028, 16, 2, 23,
 202                              0x1C0, 10),
 203         MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
 204                              emmc_400m_parents, 0x020, 0x024, 0x028, 24, 3, 31,
 205                              0x1C0, 11),
 206         /* CLK_CFG_3 */
 207         MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030,
 208                              0x034, 0x038, 0, 3, 7, 0x1c0, 12),
 209         MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
 210                              0x030, 0x034, 0x038, 8, 3, 15, 0x1c0, 13),
 211         MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
 212                              0x030, 0x034, 0x038, 16, 3, 23, 0x1c0, 14),
 213         MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
 214                              0x030, 0x034, 0x038, 24, 3, 31, 0x1c0, 15),
 215         /* CLK_CFG_4 */
 216         MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040,
 217                              0x044, 0x048, 0, 3, 7, 0x1c0, 16),
 218         MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040,
 219                              0x044, 0x048, 8, 2, 15, 0x1c0, 17),
 220         MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL,
 221                              "pcie_mbist_250m_sel", pcie_mbist_250m_parents,
 222                              0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
 223         MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel",
 224                              pextp_tl_ck_parents, 0x040, 0x044, 0x048, 24, 3,
 225                              31, 0x1C0, 19),
 226         /* CLK_CFG_5 */
 227         MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel",
 228                              pextp_tl_ck_parents, 0x050, 0x054, 0x058, 0, 3, 7,
 229                              0x1C0, 20),
 230         MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel",
 231                              pextp_tl_ck_parents, 0x050, 0x054, 0x058, 8, 3,
 232                              15, 0x1C0, 21),
 233         MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel",
 234                              pextp_tl_ck_parents, 0x050, 0x054, 0x058, 16, 3,
 235                              23, 0x1C0, 22),
 236         MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel",
 237                              eth_gmii_parents, 0x050, 0x054, 0x058, 24, 1, 31,
 238                              0x1C0, 23),
 239         /* CLK_CFG_6 */
 240         MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel",
 241                              eth_gmii_parents, 0x060, 0x064, 0x068, 0, 1, 7,
 242                              0x1C0, 24),
 243         MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel",
 244                              eth_gmii_parents, 0x060, 0x064, 0x068, 8, 1, 15,
 245                              0x1C0, 25),
 246         MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel",
 247                              eth_gmii_parents, 0x060, 0x064, 0x068, 16, 1, 23,
 248                              0x1C0, 26),
 249         MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
 250                              usb_frmcnt_parents, 0x060, 0x064, 0x068, 24, 1,
 251                              31, 0x1C0, 27),
 252         /* CLK_CFG_7 */
 253         MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
 254                              usb_frmcnt_parents, 0x070, 0x074, 0x078, 0, 1, 7,
 255                              0x1C0, 28),
 256         MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070,
 257                              0x074, 0x078, 8, 1, 15, 0x1c0, 29),
 258         MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
 259                              0x070, 0x074, 0x078, 16, 1, 23, 0x1c0, 30),
 260         MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
 261                              0x070, 0x074, 0x078, 24, 2, 31, 0x1c4, 0),
 262         /* CLK_CFG_8 */
 263         MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents,
 264                              0x080, 0x084, 0x088, 0, 1, 7, 0x1c4, 1),
 265         MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents,
 266                              0x080, 0x084, 0x088, 8, 1, 15, 0x1c4, 2),
 267         MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel",
 268                              sspxtp_parents, 0x080, 0x084, 0x088, 16, 1, 23,
 269                              0x1c4, 3),
 270         MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
 271                              usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24,
 272                              1, 31, 0x1C4, 4),
 273         /* CLK_CFG_9 */
 274         MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
 275                              usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1,
 276                              7, 0x1C4, 5),
 277         MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents,
 278                              0x090, 0x094, 0x098, 8, 1, 15, 0x1c4, 6),
 279         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel",
 280                                    usxgmii_sbus_0_parents, 0x090, 0x094, 0x098,
 281                                    16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL),
 282         MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents,
 283                              0x090, 0x094, 0x098, 24, 1, 31, 0x1c4, 8),
 284         /* CLK_CFG_10 */
 285         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel",
 286                                    usxgmii_sbus_0_parents, 0x0a0, 0x0a4, 0x0a8,
 287                                    0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL),
 288         MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel",
 289                              sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15,
 290                              0x1C4, 10),
 291         MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel",
 292                              sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 16, 1, 23,
 293                              0x1C4, 11),
 294         /* CLK_CFG_11 */
 295         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
 296                                    axi_infra_parents, 0x0a0, 0x0a4, 0x0a8, 24,
 297                                    1, 31, 0x1C4, 12, CLK_IS_CRITICAL),
 298         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
 299                                    sysapb_parents, 0x0b0, 0x0b4, 0x0b8, 0, 1,
 300                                    7, 0x1c4, 13, CLK_IS_CRITICAL),
 301         MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
 302                              eth_refck_50m_parents, 0x0b0, 0x0b4, 0x0b8, 8, 1,
 303                              15, 0x1C4, 14),
 304         MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
 305                              eth_sys_200m_parents, 0x0b0, 0x0b4, 0x0b8, 16, 1,
 306                              23, 0x1C4, 15),
 307         MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel",
 308                              pcie_mbist_250m_parents, 0x0b0, 0x0b4, 0x0b8, 24,
 309                              1, 31, 0x1C4, 16),
 310         /* CLK_CFG_12 */
 311         MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel",
 312                              eth_xgmii_parents, 0x0c0, 0x0c4, 0x0c8, 0, 2, 7,
 313                              0x1C4, 17),
 314         MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel",
 315                              bus_tops_parents, 0x0c0, 0x0c4, 0x0c8, 8, 2, 15,
 316                              0x1C4, 18),
 317         MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel",
 318                              npu_tops_parents, 0x0c0, 0x0c4, 0x0c8, 16, 1, 23,
 319                              0x1C4, 19),
 320         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
 321                                    sspxtp_parents, 0x0c0, 0x0c4, 0x0c8, 24, 1,
 322                                    31, 0x1C4, 20, CLK_IS_CRITICAL),
 323         /* CLK_CFG_13 */
 324         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
 325                                    dramc_md32_parents, 0x0d0, 0x0d4, 0x0d8, 0,
 326                                    2, 7, 0x1C4, 21, CLK_IS_CRITICAL),
 327         MUX_GATE_CLR_SET_UPD_FLAGS(
 328                 CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
 329                 0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL),
 330         MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel",
 331                              sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 16, 1, 23,
 332                              0x1C4, 23),
 333         MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel",
 334                              sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 24, 1, 31,
 335                              0x1C4, 24),
 336         /* CLK_CFG_14 */
 337         MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel",
 338                              sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7,
 339                              0x1C4, 25),
 340         MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel",
 341                              sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15,
 342                              0x1C4, 26),
 343         MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
 344                              da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 16, 1,
 345                              23, 0x1C4, 27),
 346         MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
 347                              da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 24, 1,
 348                              31, 0x1C4, 28),
 349         /* CLK_CFG_15 */
 350         MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
 351                              da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 0, 1,
 352                              7, 0x1C4, 29),
 353         MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
 354                              da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 8, 1,
 355                              15, 0x1C4, 30),
 356         MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0,
 357                              0x0f4, 0x0f8, 16, 1, 23, 0x1c8, 0),
 358         MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0,
 359                              0x0f4, 0x0f8, 24, 1, 31, 0x1C8, 1),
 360         /* CLK_CFG_16 */
 361         MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents,
 362                              0x0100, 0x104, 0x108, 0, 1, 7, 0x1c8, 2),
 363         MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel",
 364                              sspxtp_parents, 0x0100, 0x104, 0x108, 8, 1, 15,
 365                              0x1C8, 3),
 366         MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL,
 367                              "mcusys_backup_625m_sel",
 368                              mcusys_backup_625m_parents, 0x0100, 0x104, 0x108,
 369                              16, 1, 23, 0x1C8, 4),
 370         MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL,
 371                              "netsys_sync_250m_sel", pcie_mbist_250m_parents,
 372                              0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5),
 373         /* CLK_CFG_17 */
 374         MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents,
 375                              0x0110, 0x114, 0x118, 0, 2, 7, 0x1c8, 6),
 376         MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL,
 377                              "netsys_tops_400m_sel", netsys_tops_400m_parents,
 378                              0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7),
 379         MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL,
 380                              "netsys_ppefb_250m_sel", pcie_mbist_250m_parents,
 381                              0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8),
 382         MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel",
 383                              netsys_parents, 0x0110, 0x114, 0x118, 24, 2, 31,
 384                              0x1C8, 9),
 385         /* CLK_CFG_18 */
 386         MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel",
 387                              eth_mii_parents, 0x0120, 0x124, 0x128, 0, 1, 7,
 388                              0x1c8, 10),
 389         MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents,
 390                              0x0120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
 391 };
 392
 393 static const struct mtk_composite top_aud_divs[] = {
 394         DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420,
 395                  8, 8),
 396 };
 397
 398 static int clk_mt7988_topckgen_probe(struct platform_device *pdev)
 399 {
 400         struct clk_onecell_data *clk_data;
 401         struct device_node *node = pdev->dev.of_node;
 402         int r;
 403         void __iomem *base;
 404         int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
 405                  ARRAY_SIZE(top_muxes) + ARRAY_SIZE(top_aud_divs);
 406
 407         base = of_iomap(node, 0);
 408         if (!base) {
 409                 pr_err("%s(): ioremap failed\n", __func__);
 410                 return -ENOMEM;
 411         }
 412
 413         clk_data = mtk_alloc_clk_data(nr);
 414         if (!clk_data)
 415                 return -ENOMEM;
 416
 417         mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
 418                                     clk_data);
 419
 420         mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
 421
 422         mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
 423                                &mt7988_clk_lock, clk_data);
 424
 425         mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
 426                                     base, &mt7988_clk_lock, clk_data);
 427
 428         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 429
 430         if (r) {
 431                 pr_err("%s(): could not register clock provider: %d\n",
 432                        __func__, r);
 433                 goto free_topckgen_data;
 434         }
 435         return r;
 436
 437 free_topckgen_data:
 438         mtk_free_clk_data(clk_data);
 439         return r;
 440 }
 441
 442 static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b",
 443                                                    "net1pll_d4" };
 444
 445 static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b",
 446                                                    "net1pll_d4" };
 447
 448 static struct mtk_composite mcu_muxes[] = {
 449         /* bus_pll_divider_cfg */
 450         MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel",
 451                        mcu_bus_div_parents, 0x7C0, 9, 2, -1, CLK_IS_CRITICAL),
 452         /* mp2_pll_divider_cfg */
 453         MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel",
 454                        mcu_arm_div_parents, 0x7A8, 9, 2, -1, CLK_IS_CRITICAL),
 455 };
 456
 457 static int clk_mt7988_mcusys_probe(struct platform_device *pdev)
 458 {
 459         struct clk_onecell_data *clk_data;
 460         struct device_node *node = pdev->dev.of_node;
 461         int r;
 462         void __iomem *base;
 463         int nr = ARRAY_SIZE(mcu_muxes);
 464
 465         base = of_iomap(node, 0);
 466         if (!base) {
 467                 pr_err("%s(): ioremap failed\n", __func__);
 468                 return -ENOMEM;
 469         }
 470
 471         clk_data = mtk_alloc_clk_data(nr);
 472         if (!clk_data)
 473                 return -ENOMEM;
 474
 475         mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
 476                                     &mt7988_clk_lock, clk_data);
 477
 478         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 479
 480         if (r) {
 481                 pr_err("%s(): could not register clock provider: %d\n",
 482                        __func__, r);
 483                 goto free_mcusys_data;
 484         }
 485         return r;
 486
 487 free_mcusys_data:
 488         mtk_free_clk_data(clk_data);
 489         return r;
 490 }
 491
 492 static const struct of_device_id of_match_clk_mt7988_topckgen[] = {
 493         {
 494                 .compatible = "mediatek,mt7988-topckgen",
 495         },
 496         {}
 497 };
 498
 499 static struct platform_driver clk_mt7988_topckgen_drv = {
 500         .probe = clk_mt7988_topckgen_probe,
 501         .driver = {
 502                 .name = "clk-mt7988-topckgen",
 503                 .of_match_table = of_match_clk_mt7988_topckgen,
 504         },
 505 };
 506 builtin_platform_driver(clk_mt7988_topckgen_drv);
 507
 508 static const struct of_device_id of_match_clk_mt7988_mcusys[] = {
 509         {
 510                 .compatible = "mediatek,mt7988-mcusys",
 511         },
 512         {}
 513 };
 514
 515 static struct platform_driver clk_mt7988_mcusys_drv = {
 516         .probe = clk_mt7988_mcusys_probe,
 517         .driver = {
 518                 .name = "clk-mt7988-mcusys",
 519                 .of_match_table = of_match_clk_mt7988_mcusys,
 520         },
 521 };
 522 builtin_platform_driver(clk_mt7988_mcusys_drv);