target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2020 MediaTek Inc.
   4  * Author: Sam.Shih <sam.shih@mediatek.com>
   5  * Author: Jianhui Zhao <zhaojh329@gmail.com>
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/phy/phy.h>
  11 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
  12 #include <dt-bindings/reset/mt7986-resets.h>
  13 #include <dt-bindings/pinctrl/mt65xx.h>
  14 #include <dt-bindings/leds/common.h>
  15 #include <dt-bindings/input/linux-event-codes.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/mux/mux.h>
  18
  19 / {
  20         compatible = "mediatek,mt7981";
  21         interrupt-parent = <&gic>;
  22         #address-cells = <2>;
  23         #size-cells = <2>;
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu@0 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a53";
  32                         enable-method = "psci";
  33                         reg = <0x0>;
  34                 };
  35
  36                 cpu@1 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a53";
  39                         enable-method = "psci";
  40                         reg = <0x1>;
  41                 };
  42         };
  43
  44         pwm: pwm@10048000 {
  45                 compatible = "mediatek,mt7981-pwm";
  46                 reg = <0 0x10048000 0 0x1000>;
  47                 #pwm-cells = <2>;
  48                 clocks = <&infracfg CLK_INFRA_PWM_STA>,
  49                          <&infracfg CLK_INFRA_PWM_HCK>,
  50                          <&infracfg CLK_INFRA_PWM1_CK>,
  51                          <&infracfg CLK_INFRA_PWM2_CK>,
  52                          <&infracfg CLK_INFRA_PWM3_CK>;
  53                 clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
  54         };
  55
  56         fan: pwm-fan {
  57                 compatible = "pwm-fan";
  58                 /* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */
  59                 cooling-levels = <0 63 95 127 159 191 223 255>;
  60                 #cooling-cells = <2>;
  61                 status = "disabled";
  62         };
  63
  64         thermal-zones {
  65                 cpu_thermal: cpu-thermal {
  66                         polling-delay-passive = <1000>;
  67                         polling-delay = <1000>;
  68                         thermal-sensors = <&thermal 0>;
  69                         trips {
  70                                 cpu_trip_active_highest: active-highest {
  71                                         temperature = <70000>;
  72                                         hysteresis = <2000>;
  73                                         type = "active";
  74                                 };
  75
  76                                 cpu_trip_active_high: active-high {
  77                                         temperature = <60000>;
  78                                         hysteresis = <2000>;
  79                                         type = "active";
  80                                 };
  81
  82                                 cpu_trip_active_med: active-med {
  83                                         temperature = <50000>;
  84                                         hysteresis = <2000>;
  85                                         type = "active";
  86                                 };
  87
  88                                 cpu_trip_active_low: active-low {
  89                                         temperature = <45000>;
  90                                         hysteresis = <2000>;
  91                                         type = "active";
  92                                 };
  93
  94                                 cpu_trip_active_lowest: active-lowest {
  95                                         temperature = <40000>;
  96                                         hysteresis = <2000>;
  97                                         type = "active";
  98                                 };
  99                         };
 100
 101                         cooling-maps {
 102                                 cpu-active-highest {
 103                                         /* active: set fan to cooling level 7 */
 104                                         cooling-device = <&fan 7 7>;
 105                                         trip = <&cpu_trip_active_highest>;
 106                                 };
 107
 108                                 cpu-active-high {
 109                                         /* active: set fan to cooling level 5 */
 110                                         cooling-device = <&fan 5 5>;
 111                                         trip = <&cpu_trip_active_high>;
 112                                 };
 113
 114                                 cpu-active-med {
 115                                         /* active: set fan to cooling level 3 */
 116                                         cooling-device = <&fan 3 3>;
 117                                         trip = <&cpu_trip_active_med>;
 118                                 };
 119
 120                                 cpu-active-low {
 121                                         /* active: set fan to cooling level 2 */
 122                                         cooling-device = <&fan 2 2>;
 123                                         trip = <&cpu_trip_active_low>;
 124                                 };
 125
 126                                 cpu-active-lowest {
 127                                         /* active: set fan to cooling level 1 */
 128                                         cooling-device = <&fan 1 1>;
 129                                         trip = <&cpu_trip_active_lowest>;
 130                                 };
 131                         };
 132                 };
 133         };
 134
 135         thermal: thermal@1100c800 {
 136                 #thermal-sensor-cells = <1>;
 137                 compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
 138                 reg = <0 0x1100c800 0 0x800>;
 139                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 140                 clocks = <&infracfg CLK_INFRA_THERM_CK>,
 141                          <&infracfg CLK_INFRA_ADC_26M_CK>;
 142                 clock-names = "therm", "auxadc";
 143                 mediatek,auxadc = <&auxadc>;
 144                 mediatek,apmixedsys = <&apmixedsys>;
 145                 nvmem-cells = <&thermal_calibration>;
 146                 nvmem-cell-names = "calibration-data";
 147         };
 148
 149         auxadc: adc@1100d000 {
 150                 compatible = "mediatek,mt7981-auxadc",
 151                              "mediatek,mt7986-auxadc",
 152                              "mediatek,mt7622-auxadc";
 153                 reg = <0 0x1100d000 0 0x1000>;
 154                 clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
 155                          <&infracfg CLK_INFRA_ADC_FRC_CK>;
 156                 clock-names = "main", "32k";
 157                 #io-channel-cells = <1>;
 158         };
 159
 160         wdma: wdma@15104800 {
 161                 compatible = "mediatek,wed-wdma";
 162                 reg = <0 0x15104800 0 0x400>,
 163                       <0 0x15104c00 0 0x400>;
 164         };
 165
 166         ap2woccif: ap2woccif@151a5000 {
 167                 compatible = "mediatek,ap2woccif";
 168                 reg = <0 0x151a5000 0 0x1000>,
 169                       <0 0x151ad000 0 0x1000>;
 170                 interrupt-parent = <&gic>;
 171                 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
 173         };
 174
 175         reserved-memory {
 176                 #address-cells = <2>;
 177                 #size-cells = <2>;
 178                 ranges;
 179
 180                 /* 64 KiB reserved for ramoops/pstore */
 181                 ramoops@42ff0000 {
 182                         compatible = "ramoops";
 183                         reg = <0 0x42ff0000 0 0x10000>;
 184                         record-size = <0x1000>;
 185                 };
 186
 187                 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
 188                 secmon_reserved: secmon@43000000 {
 189                         reg = <0 0x43000000 0 0x30000>;
 190                         no-map;
 191                 };
 192
 193                 wmcpu_emi: wmcpu-reserved@47c80000 {
 194                         reg = <0 0x47c80000 0 0x100000>;
 195                         no-map;
 196                 };
 197
 198                 wo_emi0: wo-emi@47d80000 {
 199                         reg = <0 0x47d80000 0 0x40000>;
 200                         no-map;
 201                 };
 202
 203                 wo_data: wo-data@47dc0000 {
 204                         reg = <0 0x47dc0000 0 0x240000>;
 205                         no-map;
 206                 };
 207         };
 208
 209         psci {
 210                 compatible  = "arm,psci-0.2";
 211                 method      = "smc";
 212         };
 213
 214         trng {
 215                 compatible = "mediatek,mt7981-rng";
 216         };
 217
 218         clk40m: oscillator@0 {
 219                 compatible = "fixed-clock";
 220                 #clock-cells = <0>;
 221                 clock-frequency = <40000000>;
 222                 clock-output-names = "clkxtal";
 223         };
 224
 225         infracfg: infracfg@10001000 {
 226                 compatible = "mediatek,mt7981-infracfg", "syscon";
 227                 reg = <0 0x10001000 0 0x1000>;
 228                 #clock-cells = <1>;
 229         };
 230
 231         topckgen: topckgen@1001B000 {
 232                 compatible = "mediatek,mt7981-topckgen", "syscon";
 233                 reg = <0 0x1001B000 0 0x1000>;
 234                 #clock-cells = <1>;
 235         };
 236
 237         apmixedsys: apmixedsys@1001E000 {
 238                 compatible = "mediatek,mt7981-apmixedsys", "mediatek,mt7986-apmixedsys", "syscon";
 239                 reg = <0 0x1001E000 0 0x1000>;
 240                 #clock-cells = <1>;
 241         };
 242
 243         timer {
 244                 compatible = "arm,armv8-timer";
 245                 interrupt-parent = <&gic>;
 246                 clock-frequency = <13000000>;
 247                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 248                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 249                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 250                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 251
 252         };
 253
 254         watchdog: watchdog@1001c000 {
 255                 compatible = "mediatek,mt7986-wdt",
 256                              "mediatek,mt6589-wdt";
 257                 reg = <0 0x1001c000 0 0x1000>;
 258                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 259                 #reset-cells = <1>;
 260                 status = "disabled";
 261         };
 262
 263         gic: interrupt-controller@c000000 {
 264                 compatible = "arm,gic-v3";
 265                 #interrupt-cells = <3>;
 266                 interrupt-parent = <&gic>;
 267                 interrupt-controller;
 268                 reg = <0 0x0c000000 0 0x40000>,  /* GICD */
 269                       <0 0x0c080000 0 0x200000>; /* GICR */
 270
 271                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 272         };
 273
 274         uart0: serial@11002000 {
 275                 compatible = "mediatek,mt6577-uart";
 276                 reg = <0 0x11002000 0 0x400>;
 277                 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 278                 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
 279                         <&infracfg CLK_INFRA_UART0_CK>;
 280                 clock-names = "baud", "bus";
 281                 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 282                                   <&infracfg CLK_INFRA_UART0_SEL>;
 283                 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
 284                                          <&topckgen CLK_TOP_UART_SEL>;
 285                 pinctrl-0 = <&uart0_pins>;
 286                 pinctrl-names = "default";
 287                 status = "disabled";
 288         };
 289
 290         uart1: serial@11003000 {
 291                 compatible = "mediatek,mt6577-uart";
 292                 reg = <0 0x11003000 0 0x400>;
 293                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 294                 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
 295                         <&infracfg CLK_INFRA_UART1_CK>;
 296                 clock-names = "baud", "bus";
 297                 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 298                                   <&infracfg CLK_INFRA_UART1_SEL>;
 299                 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
 300                                          <&topckgen CLK_TOP_UART_SEL>;
 301                 status = "disabled";
 302         };
 303
 304         uart2: serial@11004000 {
 305                 compatible = "mediatek,mt6577-uart";
 306                 reg = <0 0x11004000 0 0x400>;
 307                 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 308                 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
 309                         <&infracfg CLK_INFRA_UART2_CK>;
 310                 clock-names = "baud", "bus";
 311                 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 312                                   <&infracfg CLK_INFRA_UART2_SEL>;
 313                 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
 314                                          <&topckgen CLK_TOP_UART_SEL>;
 315                 status = "disabled";
 316         };
 317
 318         i2c0: i2c@11007000 {
 319                 compatible = "mediatek,mt7981-i2c";
 320                 reg = <0 0x11007000 0 0x1000>,
 321                       <0 0x10217080 0 0x80>;
 322                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 323                 clock-div = <1>;
 324                 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
 325                          <&infracfg CLK_INFRA_AP_DMA_CK>,
 326                          <&infracfg CLK_INFRA_I2C_MCK_CK>,
 327                          <&infracfg CLK_INFRA_I2C_PCK_CK>;
 328                 clock-names = "main", "dma", "arb", "pmic";
 329                 #address-cells = <1>;
 330                 #size-cells = <0>;
 331                 status = "disabled";
 332         };
 333
 334         pcie: pcie@11280000 {
 335                 compatible = "mediatek,mt7981-pcie",
 336                              "mediatek,mt7986-pcie";
 337                 device_type = "pci";
 338                 reg = <0 0x11280000 0 0x4000>;
 339                 reg-names = "pcie-mac";
 340                 #address-cells = <3>;
 341                 #size-cells = <2>;
 342                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 343                 bus-range = <0x00 0xff>;
 344                 ranges = <0x82000000 0 0x20000000
 345                           0x0 0x20000000 0 0x10000000>;
 346                 status = "disabled";
 347
 348                 clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
 349                          <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
 350                          <&infracfg CLK_INFRA_IPCIER_CK>,
 351                          <&infracfg CLK_INFRA_IPCIEB_CK>;
 352
 353                 phys = <&u3port0 PHY_TYPE_PCIE>;
 354                 phy-names = "pcie-phy";
 355
 356                 #interrupt-cells = <1>;
 357                 interrupt-map-mask = <0 0 0 7>;
 358                 interrupt-map = <0 0 0 1 &pcie_intc 0>,
 359                                 <0 0 0 2 &pcie_intc 1>,
 360                                 <0 0 0 3 &pcie_intc 2>,
 361                                 <0 0 0 4 &pcie_intc 3>;
 362                 pcie_intc: interrupt-controller {
 363                         interrupt-controller;
 364                         #address-cells = <0>;
 365                         #interrupt-cells = <1>;
 366                 };
 367         };
 368
 369         crypto: crypto@10320000 {
 370                 compatible = "inside-secure,safexcel-eip97";
 371                 reg = <0 0x10320000 0 0x40000>;
 372                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 373                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 374                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 375                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 376                 interrupt-names = "ring0", "ring1", "ring2", "ring3";
 377                 clocks = <&topckgen CLK_TOP_EIP97B>;
 378                 clock-names = "top_eip97_ck";
 379                 assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
 380                 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
 381         };
 382
 383         pio: pinctrl@11d00000 {
 384                 compatible = "mediatek,mt7981-pinctrl";
 385                 reg = <0 0x11d00000 0 0x1000>,
 386                       <0 0x11c00000 0 0x1000>,
 387                       <0 0x11c10000 0 0x1000>,
 388                       <0 0x11d20000 0 0x1000>,
 389                       <0 0x11e00000 0 0x1000>,
 390                       <0 0x11e20000 0 0x1000>,
 391                       <0 0x11f00000 0 0x1000>,
 392                       <0 0x11f10000 0 0x1000>,
 393                       <0 0x1000b000 0 0x1000>;
 394                 reg-names = "gpio", "iocfg_rt", "iocfg_rm",
 395                             "iocfg_rb", "iocfg_lb", "iocfg_bl",
 396                             "iocfg_tm", "iocfg_tl", "eint";
 397                 gpio-controller;
 398                 #gpio-cells = <2>;
 399                 gpio-ranges = <&pio 0 0 56>;
 400                 interrupt-controller;
 401                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 402                 interrupt-parent = <&gic>;
 403                 #interrupt-cells = <2>;
 404
 405                 mdio_pins: mdc-mdio-pins {
 406                         mux {
 407                                 function = "eth";
 408                                 groups = "smi_mdc_mdio";
 409                         };
 410                 };
 411
 412                 uart0_pins: uart0-pins {
 413                         mux {
 414                                 function = "uart";
 415                                 groups = "uart0";
 416                         };
 417                 };
 418
 419                 wifi_dbdc_pins: wifi-dbdc-pins {
 420                         mux {
 421                                 function = "eth";
 422                                 groups = "wf0_mode1";
 423                         };
 424                         conf {
 425                                 pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
 426                                        "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
 427                                        "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
 428                                        "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
 429                                        "WF_CBA_RESETB", "WF_DIG_RESETB";
 430                                 drive-strength = <4>;
 431                         };
 432                 };
 433
 434                 gbe_led0_pins: gbe-led0-pins {
 435                         mux {
 436                                 function = "led";
 437                                 groups = "gbe_led0";
 438                         };
 439                 };
 440
 441                 gbe_led1_pins: gbe-led1-pins {
 442                         mux {
 443                                 function = "led";
 444                                 groups = "gbe_led1";
 445                         };
 446                 };
 447         };
 448
 449         ethsys: syscon@15000000 {
 450                 #address-cells = <1>;
 451                 #size-cells = <1>;
 452                 compatible = "mediatek,mt7981-ethsys",
 453                              "mediatek,mt7986-ethsys",
 454                              "syscon";
 455                 reg = <0 0x15000000 0 0x1000>;
 456                 #clock-cells = <1>;
 457                 #reset-cells = <1>;
 458         };
 459
 460         wed: wed@15010000 {
 461                 compatible = "mediatek,mt7981-wed",
 462                              "mediatek,mt7986-wed",
 463                              "syscon";
 464                 reg = <0 0x15010000 0 0x1000>;
 465                 interrupt-parent = <&gic>;
 466                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 467                 memory-region = <&wo_emi0>, <&wo_data>;
 468                 memory-region-names = "wo-emi", "wo-data";
 469                 mediatek,wo-ccif = <&wo_ccif0>;
 470                 mediatek,wo-ilm = <&wo_ilm0>;
 471                 mediatek,wo-dlm = <&wo_dlm0>;
 472                 mediatek,wo-cpuboot = <&wo_cpuboot>;
 473         };
 474
 475         eth: ethernet@15100000 {
 476                 compatible = "mediatek,mt7981-eth";
 477                 reg = <0 0x15100000 0 0x80000>;
 478                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 479                                 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
 480                                 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 481                                 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 482                 clocks = <&ethsys CLK_ETH_FE_EN>,
 483                         <&ethsys CLK_ETH_GP2_EN>,
 484                         <&ethsys CLK_ETH_GP1_EN>,
 485                         <&ethsys CLK_ETH_WOCPU0_EN>,
 486                         <&sgmiisys0 CLK_SGM0_TX_EN>,
 487                         <&sgmiisys0 CLK_SGM0_RX_EN>,
 488                         <&sgmiisys0 CLK_SGM0_CK0_EN>,
 489                         <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
 490                         <&sgmiisys1 CLK_SGM1_TX_EN>,
 491                         <&sgmiisys1 CLK_SGM1_RX_EN>,
 492                         <&sgmiisys1 CLK_SGM1_CK1_EN>,
 493                         <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
 494                         <&topckgen CLK_TOP_SGM_REG>,
 495                         <&topckgen CLK_TOP_NETSYS_SEL>,
 496                         <&topckgen CLK_TOP_NETSYS_500M_SEL>;
 497                 clock-names = "fe", "gp2", "gp1", "wocpu0",
 498                                         "sgmii_tx250m", "sgmii_rx250m",
 499                                         "sgmii_cdr_ref", "sgmii_cdr_fb",
 500                                         "sgmii2_tx250m", "sgmii2_rx250m",
 501                                         "sgmii2_cdr_ref", "sgmii2_cdr_fb",
 502                                         "sgmii_ck", "netsys0", "netsys1";
 503                 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
 504                                   <&topckgen CLK_TOP_SGM_325M_SEL>;
 505                 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
 506                                          <&topckgen CLK_TOP_CB_SGM_325M>;
 507                 mediatek,ethsys = <&ethsys>;
 508                 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
 509                 mediatek,infracfg = <&topmisc>;
 510                 mediatek,wed = <&wed>;
 511                 #reset-cells = <1>;
 512                 #address-cells = <1>;
 513                 #size-cells = <0>;
 514                 status = "disabled";
 515
 516                 mdio_bus: mdio-bus {
 517                         #address-cells = <1>;
 518                         #size-cells = <0>;
 519
 520                         int_gbe_phy: ethernet-phy@0 {
 521                                 reg = <0>;
 522                                 compatible = "ethernet-phy-ieee802.3-c22";
 523                                 phy-mode = "gmii";
 524                                 phy-is-integrated;
 525                                 nvmem-cells = <&phy_calibration>;
 526                                 nvmem-cell-names = "phy-cal-data";
 527
 528                                 leds {
 529                                         #address-cells = <1>;
 530                                         #size-cells = <0>;
 531
 532                                         int_gbe_phy_led0: int-gbe-phy-led0@0 {
 533                                                 reg = <0>;
 534                                                 function = LED_FUNCTION_LAN;
 535                                                 status = "disabled";
 536                                         };
 537
 538                                         int_gbe_phy_led1: int-gbe-phy-led1@1 {
 539                                                 reg = <1>;
 540                                                 function = LED_FUNCTION_LAN;
 541                                                 status = "disabled";
 542                                         };
 543                                 };
 544                         };
 545                 };
 546         };
 547
 548         wo_dlm0: syscon@151e8000 {
 549                 compatible = "mediatek,mt7986-wo-dlm", "syscon";
 550                 reg = <0 0x151e8000 0 0x2000>;
 551         };
 552
 553         wo_ilm0: syscon@151e0000 {
 554                 compatible = "mediatek,mt7986-wo-ilm", "syscon";
 555                 reg = <0 0x151e0000 0 0x8000>;
 556         };
 557
 558         wo_cpuboot: syscon@15194000 {
 559                 compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
 560                 reg = <0 0x15194000 0 0x1000>;
 561         };
 562
 563         wo_ccif0: syscon@151a5000 {
 564                 compatible = "mediatek,mt7986-wo-ccif", "syscon";
 565                 reg = <0 0x151a5000 0 0x1000>;
 566                 interrupt-parent = <&gic>;
 567                 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
 568         };
 569
 570         sgmiisys0: syscon@10060000 {
 571                 compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon";
 572                 reg = <0 0x10060000 0 0x1000>;
 573                 mediatek,pnswap;
 574                 #clock-cells = <1>;
 575         };
 576
 577         sgmiisys1: syscon@10070000 {
 578                 compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon";
 579                 reg = <0 0x10070000 0 0x1000>;
 580                 #clock-cells = <1>;
 581         };
 582
 583         topmisc: topmisc@11d10000 {
 584                 compatible = "mediatek,mt7981-topmisc", "syscon";
 585                 reg = <0 0x11d10000 0 0x10000>;
 586                 #clock-cells = <1>;
 587         };
 588
 589         snand: snfi@11005000 {
 590                 compatible = "mediatek,mt7986-snand";
 591                 reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
 592                 reg-names = "nfi", "ecc";
 593                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 594                 clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
 595                          <&infracfg CLK_INFRA_NFI1_CK>,
 596                          <&infracfg CLK_INFRA_NFI_HCK_CK>;
 597                 clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
 598                 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
 599                                   <&topckgen CLK_TOP_NFI1X_SEL>;
 600                 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
 601                                          <&topckgen CLK_TOP_CB_M_D8>;
 602                 #address-cells = <1>;
 603                 #size-cells = <0>;
 604                 status = "disabled";
 605         };
 606
 607         mmc0: mmc@11230000 {
 608                 compatible = "mediatek,mt7986-mmc",
 609                                         "mediatek,mt7981-mmc";
 610                 reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
 611                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 612                 clocks = <&infracfg CLK_INFRA_MSDC_CK>,
 613                          <&infracfg CLK_INFRA_MSDC_HCK_CK>,
 614                          <&infracfg CLK_INFRA_MSDC_66M_CK>,
 615                          <&infracfg CLK_INFRA_MSDC_133M_CK>;
 616                 assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
 617                                   <&topckgen CLK_TOP_EMMC_400M_SEL>;
 618                 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
 619                                          <&topckgen CLK_TOP_CB_NET2_D2>;
 620                 clock-names = "source", "hclk", "axi_cg", "ahb_cg";
 621                 status = "disabled";
 622         };
 623
 624         wed_pcie: wed_pcie@10003000 {
 625                 compatible = "mediatek,wed_pcie";
 626                 reg = <0 0x10003000 0 0x10>;
 627         };
 628
 629         spi0: spi@1100a000 {
 630                 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
 631                 #address-cells = <1>;
 632                 #size-cells = <0>;
 633                 reg = <0 0x1100a000 0 0x100>;
 634                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 635                 clocks = <&topckgen CLK_TOP_CB_M_D2>,
 636                          <&topckgen CLK_TOP_SPI_SEL>,
 637                          <&infracfg CLK_INFRA_SPI0_CK>,
 638                          <&infracfg CLK_INFRA_SPI0_HCK_CK>;
 639
 640                 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 641                 status = "disabled";
 642         };
 643
 644         spi1: spi@1100b000 {
 645                 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
 646                 #address-cells = <1>;
 647                 #size-cells = <0>;
 648                 reg = <0 0x1100b000 0 0x100>;
 649                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 650                 clocks = <&topckgen CLK_TOP_CB_M_D2>,
 651                          <&topckgen CLK_TOP_SPIM_MST_SEL>,
 652                          <&infracfg CLK_INFRA_SPI1_CK>,
 653                          <&infracfg CLK_INFRA_SPI1_HCK_CK>;
 654                 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 655                 status = "disabled";
 656         };
 657
 658         spi2: spi@11009000 {
 659                 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
 660                 #address-cells = <1>;
 661                 #size-cells = <0>;
 662                 reg = <0 0x11009000 0 0x100>;
 663                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 664                 clocks = <&topckgen CLK_TOP_CB_M_D2>,
 665                          <&topckgen CLK_TOP_SPI_SEL>,
 666                          <&infracfg CLK_INFRA_SPI2_CK>,
 667                          <&infracfg CLK_INFRA_SPI2_HCK_CK>;
 668                 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 669                 status = "disabled";
 670         };
 671
 672         consys: consys@10000000 {
 673                 compatible = "mediatek,mt7981-consys";
 674                 reg = <0 0x10000000 0 0x8600000>;
 675                 memory-region = <&wmcpu_emi>;
 676         };
 677
 678         xhci: usb@11200000 {
 679                 compatible = "mediatek,mt7986-xhci",
 680                              "mediatek,mtk-xhci";
 681                 reg = <0 0x11200000 0 0x2e00>,
 682                       <0 0x11203e00 0 0x0100>;
 683                 reg-names = "mac", "ippc";
 684                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 685                 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
 686                          <&infracfg CLK_INFRA_IUSB_CK>,
 687                          <&infracfg CLK_INFRA_IUSB_133_CK>,
 688                          <&infracfg CLK_INFRA_IUSB_66M_CK>,
 689                          <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
 690                 clock-names = "sys_ck",
 691                               "ref_ck",
 692                               "mcu_ck",
 693                               "dma_ck",
 694                               "xhci_ck";
 695                 phys = <&u2port0 PHY_TYPE_USB2>,
 696                        <&u3port0 PHY_TYPE_USB3>;
 697                 vusb33-supply = <&reg_3p3v>;
 698                 status = "disabled";
 699         };
 700
 701         usb_phy: usb-phy@11e10000 {
 702                 compatible = "mediatek,mt7981",
 703                              "mediatek,generic-tphy-v2";
 704                 #address-cells = <1>;
 705                 #size-cells = <1>;
 706                 ranges = <0 0 0x11e10000 0x1700>;
 707                 status = "disabled";
 708
 709                 u2port0: usb-phy@0 {
 710                         reg = <0x0 0x700>;
 711                         clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
 712                         clock-names = "ref";
 713                         #phy-cells = <1>;
 714                 };
 715
 716                 u3port0: usb-phy@700 {
 717                         reg = <0x700 0x900>;
 718                         clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
 719                         clock-names = "ref";
 720                         #phy-cells = <1>;
 721                         mediatek,syscon-type = <&topmisc 0x218 0>;
 722                         status = "okay";
 723                 };
 724         };
 725
 726         reg_3p3v: regulator-3p3v {
 727                 compatible = "regulator-fixed";
 728                 regulator-name = "fixed-3.3V";
 729                 regulator-min-microvolt = <3300000>;
 730                 regulator-max-microvolt = <3300000>;
 731                 regulator-boot-on;
 732                 regulator-always-on;
 733         };
 734
 735         efuse: efuse@11f20000 {
 736                 compatible = "mediatek,mt7981-efuse",
 737                              "mediatek,efuse";
 738                 reg = <0 0x11f20000 0 0x1000>;
 739                 #address-cells = <1>;
 740                 #size-cells = <1>;
 741                 status = "okay";
 742
 743                 thermal_calibration: thermal-calib@274 {
 744                         reg = <0x274 0xc>;
 745                 };
 746
 747                 phy_calibration: phy-calib@8dc {
 748                         reg = <0x8dc 0x10>;
 749                 };
 750
 751                 comb_rx_imp_p0: usb3-rx-imp@8c8 {
 752                         reg = <0x8c8 1>;
 753                         bits = <0 5>;
 754                 };
 755
 756                 comb_tx_imp_p0: usb3-tx-imp@8c8 {
 757                         reg = <0x8c8 2>;
 758                         bits = <5 5>;
 759                 };
 760
 761                 comb_intr_p0: usb3-intr@8c9 {
 762                         reg = <0x8c9 1>;
 763                         bits = <2 6>;
 764                 };
 765         };
 766
 767         afe: audio-controller@11210000 {
 768                 compatible = "mediatek,mt79xx-audio";
 769                 reg = <0 0x11210000 0 0x9000>;
 770                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 771                 clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
 772                          <&infracfg CLK_INFRA_AUD_26M_CK>,
 773                          <&infracfg CLK_INFRA_AUD_L_CK>,
 774                          <&infracfg CLK_INFRA_AUD_AUD_CK>,
 775                          <&infracfg CLK_INFRA_AUD_EG2_CK>,
 776                          <&topckgen CLK_TOP_AUD_SEL>;
 777                 clock-names = "aud_bus_ck",
 778                               "aud_26m_ck",
 779                               "aud_l_ck",
 780                               "aud_aud_ck",
 781                               "aud_eg2_ck",
 782                               "aud_sel";
 783                 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
 784                                   <&topckgen CLK_TOP_A1SYS_SEL>,
 785                                   <&topckgen CLK_TOP_AUD_L_SEL>,
 786                                   <&topckgen CLK_TOP_A_TUNER_SEL>;
 787                 assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
 788                                          <&topckgen CLK_TOP_APLL2_D4>,
 789                                          <&topckgen CLK_TOP_CB_APLL2_196M>,
 790                                          <&topckgen CLK_TOP_APLL2_D4>;
 791                 status = "disabled";
 792         };
 793
 794         ice: ice_debug {
 795                 compatible = "mediatek,mt7981-ice_debug",
 796                            "mediatek,mt2701-ice_debug";
 797                 clocks = <&infracfg CLK_INFRA_DBG_CK>;
 798                 clock-names = "ice_dbg";
 799         };
 800
 801         wifi: wifi@18000000 {
 802                 compatible = "mediatek,mt7981-wmac";
 803                 resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
 804                 reset-names = "consys";
 805                 pinctrl-0 = <&wifi_dbdc_pins>;
 806                 pinctrl-names = "dbdc";
 807                 clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
 808                          <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
 809                 clock-names = "mcu", "ap2conn";
 810                 reg = <0 0x18000000 0 0x1000000>,
 811                       <0 0x10003000 0 0x1000>,
 812                       <0 0x11d10000 0 0x1000>;
 813                 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 814                              <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 815                              <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 816                              <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 817                 memory-region = <&wmcpu_emi>;
 818                 status = "disabled";
 819         };
 820 };