target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts

   1 /*
   2  * Copyright (c) 2018 MediaTek Inc.
   3  * Author: Ryder Lee <ryder.lee@mediatek.com>
   4  *
   5  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   6  */
   7
   8 /dts-v1/;
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11
  12 #include "mt7622.dtsi"
  13 #include "mt6380.dtsi"
  14
  15 / {
  16         model = "Bananapi BPI-R64";
  17         compatible = "bananapi,bpi-r64", "mediatek,mt7622";
  18
  19         aliases {
  20                 serial0 = &uart0;
  21         };
  22
  23         chosen {
  24                 stdout-path = "serial0:115200n8";
  25                 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
  26         };
  27
  28         cpus {
  29                 cpu@0 {
  30                         proc-supply = <&mt6380_vcpu_reg>;
  31                         sram-supply = <&mt6380_vm_reg>;
  32                 };
  33
  34                 cpu@1 {
  35                         proc-supply = <&mt6380_vcpu_reg>;
  36                         sram-supply = <&mt6380_vm_reg>;
  37                 };
  38         };
  39
  40         gpio-keys {
  41                 compatible = "gpio-keys";
  42
  43                 factory {
  44                         label = "factory";
  45                         linux,code = <BTN_0>;
  46                         gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
  47                 };
  48
  49                 wps {
  50                         label = "wps";
  51                         linux,code = <KEY_WPS_BUTTON>;
  52                         gpios = <&pio 102 GPIO_ACTIVE_LOW>;
  53                 };
  54         };
  55
  56         leds {
  57                 compatible = "gpio-leds";
  58
  59                 green {
  60                         label = "bpi-r64:pio:green";
  61                         gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
  62                         default-state = "off";
  63                 };
  64
  65                 red {
  66                         label = "bpi-r64:pio:red";
  67                         gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
  68                         default-state = "off";
  69                 };
  70         };
  71
  72         gsw: gsw@0 {
  73                 compatible = "mediatek,mt753x";
  74                 mediatek,ethsys = <&ethsys>;
  75                 #address-cells = <1>;
  76                 #size-cells = <0>;
  77         };
  78
  79         memory {
  80                 reg = <0 0x40000000 0 0x40000000>;
  81         };
  82
  83         reg_1p8v: regulator-1p8v {
  84                 compatible = "regulator-fixed";
  85                 regulator-name = "fixed-1.8V";
  86                 regulator-min-microvolt = <1800000>;
  87                 regulator-max-microvolt = <1800000>;
  88                 regulator-always-on;
  89         };
  90
  91         reg_3p3v: regulator-3p3v {
  92                 compatible = "regulator-fixed";
  93                 regulator-name = "fixed-3.3V";
  94                 regulator-min-microvolt = <3300000>;
  95                 regulator-max-microvolt = <3300000>;
  96                 regulator-boot-on;
  97                 regulator-always-on;
  98         };
  99
 100         reg_5v: regulator-5v {
 101                 compatible = "regulator-fixed";
 102                 regulator-name = "fixed-5V";
 103                 regulator-min-microvolt = <5000000>;
 104                 regulator-max-microvolt = <5000000>;
 105                 regulator-boot-on;
 106                 regulator-always-on;
 107         };
 108 };
 109
 110 &bch {
 111         status = "disabled";
 112 };
 113
 114 &btif {
 115         status = "okay";
 116 };
 117
 118 &cir {
 119         pinctrl-names = "default";
 120         pinctrl-0 = <&irrx_pins>;
 121         status = "okay";
 122 };
 123
 124 &eth {
 125         pinctrl-names = "default";
 126         pinctrl-0 = <&eth_pins>;
 127         status = "okay";
 128
 129         gmac1: mac@1 {
 130                 compatible = "mediatek,eth-mac";
 131                 reg = <1>;
 132                 phy-handle = <&phy5>;
 133         };
 134
 135         mdio: mdio-bus {
 136                 #address-cells = <1>;
 137                 #size-cells = <0>;
 138
 139                 phy5: ethernet-phy@5 {
 140                         reg = <5>;
 141                         phy-mode = "sgmii";
 142                 };
 143         };
 144 };
 145
 146 &i2c1 {
 147         pinctrl-names = "default";
 148         pinctrl-0 = <&i2c1_pins>;
 149         status = "okay";
 150 };
 151
 152 &i2c2 {
 153         pinctrl-names = "default";
 154         pinctrl-0 = <&i2c2_pins>;
 155         status = "okay";
 156 };
 157
 158 &mmc0 {
 159         pinctrl-names = "default", "state_uhs";
 160         pinctrl-0 = <&emmc_pins_default>;
 161         pinctrl-1 = <&emmc_pins_uhs>;
 162         status = "okay";
 163         bus-width = <8>;
 164         max-frequency = <50000000>;
 165         cap-mmc-highspeed;
 166         mmc-hs200-1_8v;
 167         vmmc-supply = <&reg_3p3v>;
 168         vqmmc-supply = <&reg_1p8v>;
 169         assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
 170         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 171         non-removable;
 172 };
 173
 174 &mmc1 {
 175         pinctrl-names = "default", "state_uhs";
 176         pinctrl-0 = <&sd0_pins_default>;
 177         pinctrl-1 = <&sd0_pins_uhs>;
 178         status = "okay";
 179         bus-width = <4>;
 180         max-frequency = <50000000>;
 181         cap-sd-highspeed;
 182         r_smpl = <1>;
 183         cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 184         vmmc-supply = <&reg_3p3v>;
 185         vqmmc-supply = <&reg_3p3v>;
 186         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
 187         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 188 };
 189
 190 &nandc {
 191         pinctrl-names = "default";
 192         pinctrl-0 = <&parallel_nand_pins>;
 193         status = "disabled";
 194 };
 195
 196 &nor_flash {
 197         pinctrl-names = "default";
 198         pinctrl-0 = <&spi_nor_pins>;
 199         status = "disabled";
 200
 201         flash@0 {
 202                 compatible = "jedec,spi-nor";
 203                 reg = <0>;
 204         };
 205 };
 206
 207 &pcie {
 208         pinctrl-names = "default";
 209         pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
 210         status = "okay";
 211
 212         pcie@0,0 {
 213                 status = "okay";
 214         };
 215
 216         pcie@1,0 {
 217                 status = "okay";
 218         };
 219 };
 220
 221 &pio {
 222         /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
 223          * SATA functions. i.e. output-high: PCIe, output-low: SATA
 224          */
 225         asm_sel {
 226                 gpio-hog;
 227                 gpios = <90 GPIO_ACTIVE_HIGH>;
 228                 output-high;
 229         };
 230
 231         /* eMMC is shared pin with parallel NAND */
 232         emmc_pins_default: emmc-pins-default {
 233                 mux {
 234                         function = "emmc", "emmc_rst";
 235                         groups = "emmc";
 236                 };
 237
 238                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
 239                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
 240                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
 241                  */
 242                 conf-cmd-dat {
 243                         pins = "NDL0", "NDL1", "NDL2",
 244                                "NDL3", "NDL4", "NDL5",
 245                                "NDL6", "NDL7", "NRB";
 246                         input-enable;
 247                         bias-pull-up;
 248                 };
 249
 250                 conf-clk {
 251                         pins = "NCLE";
 252                         bias-pull-down;
 253                 };
 254         };
 255
 256         emmc_pins_uhs: emmc-pins-uhs {
 257                 mux {
 258                         function = "emmc";
 259                         groups = "emmc";
 260                 };
 261
 262                 conf-cmd-dat {
 263                         pins = "NDL0", "NDL1", "NDL2",
 264                                "NDL3", "NDL4", "NDL5",
 265                                "NDL6", "NDL7", "NRB";
 266                         input-enable;
 267                         drive-strength = <4>;
 268                         bias-pull-up;
 269                 };
 270
 271                 conf-clk {
 272                         pins = "NCLE";
 273                         drive-strength = <4>;
 274                         bias-pull-down;
 275                 };
 276         };
 277
 278         eth_pins: eth-pins {
 279                 mux {
 280                         function = "eth";
 281                         groups = "mdc_mdio", "rgmii_via_gmac2";
 282                 };
 283         };
 284
 285         i2c1_pins: i2c1-pins {
 286                 mux {
 287                         function = "i2c";
 288                         groups =  "i2c1_0";
 289                 };
 290         };
 291
 292         i2c2_pins: i2c2-pins {
 293                 mux {
 294                         function = "i2c";
 295                         groups =  "i2c2_0";
 296                 };
 297         };
 298
 299         i2s1_pins: i2s1-pins {
 300                 mux {
 301                         function = "i2s";
 302                         groups =  "i2s_out_mclk_bclk_ws",
 303                                   "i2s1_in_data",
 304                                   "i2s1_out_data";
 305                 };
 306
 307                 conf {
 308                         pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
 309                                "I2S_WS", "I2S_MCLK";
 310                         drive-strength = <12>;
 311                         bias-pull-down;
 312                 };
 313         };
 314
 315         irrx_pins: irrx-pins {
 316                 mux {
 317                         function = "ir";
 318                         groups =  "ir_1_rx";
 319                 };
 320         };
 321
 322         irtx_pins: irtx-pins {
 323                 mux {
 324                         function = "ir";
 325                         groups =  "ir_1_tx";
 326                 };
 327         };
 328
 329         /* Parallel nand is shared pin with eMMC */
 330         parallel_nand_pins: parallel-nand-pins {
 331                 mux {
 332                         function = "flash";
 333                         groups = "par_nand";
 334                 };
 335         };
 336
 337         pcie0_pins: pcie0-pins {
 338                 mux {
 339                         function = "pcie";
 340                         groups = "pcie0_pad_perst",
 341                                  "pcie0_1_waken",
 342                                  "pcie0_1_clkreq";
 343                 };
 344         };
 345
 346         pcie1_pins: pcie1-pins {
 347                 mux {
 348                         function = "pcie";
 349                         groups = "pcie1_pad_perst",
 350                                  "pcie1_0_waken",
 351                                  "pcie1_0_clkreq";
 352                 };
 353         };
 354
 355         pmic_bus_pins: pmic-bus-pins {
 356                 mux {
 357                         function = "pmic";
 358                         groups = "pmic_bus";
 359                 };
 360         };
 361
 362         pwm7_pins: pwm1-2-pins {
 363                 mux {
 364                         function = "pwm";
 365                         groups = "pwm_ch7_2";
 366                 };
 367         };
 368
 369         wled_pins: wled-pins {
 370                 mux {
 371                         function = "led";
 372                         groups = "wled";
 373                 };
 374         };
 375
 376         sd0_pins_default: sd0-pins-default {
 377                 mux {
 378                         function = "sd";
 379                         groups = "sd_0";
 380                 };
 381
 382                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 383                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 384                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 385                  */
 386                 conf-cmd-data {
 387                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 388                                "I2S2_IN","I2S4_OUT";
 389                         input-enable;
 390                         drive-strength = <8>;
 391                         bias-pull-up;
 392                 };
 393                 conf-clk {
 394                         pins = "I2S3_OUT";
 395                         drive-strength = <12>;
 396                         bias-pull-down;
 397                 };
 398                 conf-cd {
 399                         pins = "TXD3";
 400                         bias-pull-up;
 401                 };
 402         };
 403
 404         sd0_pins_uhs: sd0-pins-uhs {
 405                 mux {
 406                         function = "sd";
 407                         groups = "sd_0";
 408                 };
 409
 410                 conf-cmd-data {
 411                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 412                                "I2S2_IN","I2S4_OUT";
 413                         input-enable;
 414                         bias-pull-up;
 415                 };
 416
 417                 conf-clk {
 418                         pins = "I2S3_OUT";
 419                         bias-pull-down;
 420                 };
 421         };
 422
 423         /* Serial NAND is shared pin with SPI-NOR */
 424         serial_nand_pins: serial-nand-pins {
 425                 mux {
 426                         function = "flash";
 427                         groups = "snfi";
 428                 };
 429         };
 430
 431         spic0_pins: spic0-pins {
 432                 mux {
 433                         function = "spi";
 434                         groups = "spic0_0";
 435                 };
 436         };
 437
 438         spic1_pins: spic1-pins {
 439                 mux {
 440                         function = "spi";
 441                         groups = "spic1_0";
 442                 };
 443         };
 444
 445         /* SPI-NOR is shared pin with serial NAND */
 446         spi_nor_pins: spi-nor-pins {
 447                 mux {
 448                         function = "flash";
 449                         groups = "spi_nor";
 450                 };
 451         };
 452
 453         /* serial NAND is shared pin with SPI-NOR */
 454         serial_nand_pins: serial-nand-pins {
 455                 mux {
 456                         function = "flash";
 457                         groups = "snfi";
 458                 };
 459         };
 460
 461         uart0_pins: uart0-pins {
 462                 mux {
 463                         function = "uart";
 464                         groups = "uart0_0_tx_rx" ;
 465                 };
 466         };
 467
 468         uart2_pins: uart2-pins {
 469                 mux {
 470                         function = "uart";
 471                         groups = "uart2_1_tx_rx" ;
 472                 };
 473         };
 474
 475         watchdog_pins: watchdog-pins {
 476                 mux {
 477                         function = "watchdog";
 478                         groups = "watchdog";
 479                 };
 480         };
 481 };
 482
 483 &pwm {
 484         pinctrl-names = "default";
 485         pinctrl-0 = <&pwm7_pins>;
 486         status = "okay";
 487 };
 488
 489 &pwrap {
 490         pinctrl-names = "default";
 491         pinctrl-0 = <&pmic_bus_pins>;
 492
 493         status = "okay";
 494 };
 495
 496 &sata {
 497         status = "disable";
 498 };
 499
 500 &sata_phy {
 501         status = "disable";
 502 };
 503
 504 &spi0 {
 505         pinctrl-names = "default";
 506         pinctrl-0 = <&spic0_pins>;
 507         status = "okay";
 508 };
 509
 510 &spi1 {
 511         pinctrl-names = "default";
 512         pinctrl-0 = <&spic1_pins>;
 513         status = "okay";
 514 };
 515
 516 &ssusb {
 517         vusb33-supply = <&reg_3p3v>;
 518         vbus-supply = <&reg_5v>;
 519         status = "okay";
 520 };
 521
 522 &u3phy {
 523         status = "okay";
 524 };
 525
 526 &uart0 {
 527         pinctrl-names = "default";
 528         pinctrl-0 = <&uart0_pins>;
 529         status = "okay";
 530 };
 531
 532 &uart2 {
 533         pinctrl-names = "default";
 534         pinctrl-0 = <&uart2_pins>;
 535         status = "okay";
 536 };
 537
 538 &watchdog {
 539         pinctrl-names = "default";
 540         pinctrl-0 = <&watchdog_pins>;
 541         status = "okay";
 542 };
 543
 544 &gsw {
 545         mediatek,mdio = <&mdio>;
 546         mediatek,portmap = "llllw";
 547         mediatek,mdio_master_pinmux = <0>;
 548         reset-gpios = <&pio 54 0>;
 549         interrupt-parent = <&pio>;
 550         interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
 551         status = "okay";
 552
 553         port5: port@5 {
 554                 compatible = "mediatek,mt753x-port";
 555                 reg = <5>;
 556                 phy-mode = "rgmii";
 557                 fixed-link {
 558                         speed = <1000>;
 559                         full-duplex;
 560                 };
 561         };
 562
 563         port6: port@6 {
 564                 compatible = "mediatek,mt753x-port";
 565                 reg = <6>;
 566                 phy-mode = "sgmii";
 567                 fixed-link {
 568                         speed = <2500>;
 569                         full-duplex;
 570                 };
 571         };
 572 };
 573
 574