target/linux/ipq807x/patches-6.1/0130-arm64-dts-qcom-ipq8074-add-CPU-OPP-table.patch

   1 From a20c4e8738a00087aa5d53fe5148ed484e23d229 Mon Sep 17 00:00:00 2001
   2 From: Robert Marko <robimarko@gmail.com>
   3 Date: Sat, 31 Dec 2022 13:56:26 +0100
   4 Subject: [PATCH] arm64: dts: qcom: ipq8074: add CPU OPP table
   5
   6 Now that there is NVMEM CPUFreq support for IPQ8074, we can add the OPP
   7 table for SoC.
   8
   9 Signed-off-by: Robert Marko <robimarko@gmail.com>
  10 ---
  11  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 52 +++++++++++++++++++++++++++
  12  1 file changed, 52 insertions(+)
  13
  14 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  15 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  16 @@ -42,6 +42,7 @@
  17                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  18                         clock-names = "cpu";
  19                         #cooling-cells = <2>;
  20 +                       operating-points-v2 = <&cpu_opp_table>;
  21                 };
  22
  23                 CPU1: cpu@1 {
  24 @@ -53,6 +54,7 @@
  25                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  26                         clock-names = "cpu";
  27                         #cooling-cells = <2>;
  28 +                       operating-points-v2 = <&cpu_opp_table>;
  29                 };
  30
  31                 CPU2: cpu@2 {
  32 @@ -64,6 +66,7 @@
  33                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  34                         clock-names = "cpu";
  35                         #cooling-cells = <2>;
  36 +                       operating-points-v2 = <&cpu_opp_table>;
  37                 };
  38
  39                 CPU3: cpu@3 {
  40 @@ -75,6 +78,7 @@
  41                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  42                         clock-names = "cpu";
  43                         #cooling-cells = <2>;
  44 +                       operating-points-v2 = <&cpu_opp_table>;
  45                 };
  46
  47                 L2_0: l2-cache {
  48 @@ -83,6 +87,54 @@
  49                 };
  50         };
  51
  52 +       cpu_opp_table: opp-table {
  53 +               compatible = "operating-points-v2-kryo-cpu";
  54 +               nvmem-cells = <&cpr_efuse_speedbin>;
  55 +               opp-shared;
  56 +
  57 +               opp-1017600000 {
  58 +                       opp-hz = /bits/ 64 <1017600000>;
  59 +                       opp-microvolt = <1>;
  60 +                       opp-supported-hw = <0xf>;
  61 +                       clock-latency-ns = <200000>;
  62 +               };
  63 +
  64 +               opp-1382400000 {
  65 +                       opp-hz = /bits/ 64 <1382400000>;
  66 +                       opp-microvolt = <2>;
  67 +                       opp-supported-hw = <0xf>;
  68 +                       clock-latency-ns = <200000>;
  69 +               };
  70 +
  71 +               opp-1651200000 {
  72 +                       opp-hz = /bits/ 64 <1651200000>;
  73 +                       opp-microvolt = <3>;
  74 +                       opp-supported-hw = <0x1>;
  75 +                       clock-latency-ns = <200000>;
  76 +               };
  77 +
  78 +               opp-1843200000 {
  79 +                       opp-hz = /bits/ 64 <1843200000>;
  80 +                       opp-microvolt = <4>;
  81 +                       opp-supported-hw = <0x1>;
  82 +                       clock-latency-ns = <200000>;
  83 +               };
  84 +
  85 +               opp-1920000000 {
  86 +                       opp-hz = /bits/ 64 <1920000000>;
  87 +                       opp-microvolt = <5>;
  88 +                       opp-supported-hw = <0x1>;
  89 +                       clock-latency-ns = <200000>;
  90 +               };
  91 +
  92 +               opp-2208000000 {
  93 +                       opp-hz = /bits/ 64 <2208000000>;
  94 +                       opp-microvolt = <6>;
  95 +                       opp-supported-hw = <0x1>;
  96 +                       clock-latency-ns = <200000>;
  97 +               };
  98 +       };
  99 +
 100         pmu {
 101                 compatible = "arm,cortex-a53-pmu";
 102                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;