09abbfa2e59d69e135537779e818b71c05645ed0
[openwrt/staging/jow.git] / target / linux / ipq807x / patches-6.1 / 0128-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch
1 From 11592aa862e67f4477dee7e94d5c8244d893de1b Mon Sep 17 00:00:00 2001
2 From: Robert Marko <robimarko@gmail.com>
3 Date: Sat, 31 Dec 2022 13:03:41 +0100
4 Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ8074
5
6 IPQ8074 comes in 2 families:
7 * IPQ8070A/IPQ8071A (Acorn) up to 1.4GHz
8 * IPQ8072A/IPQ8074A/IPQ8076A/IPQ8078A (Hawkeye) up to 2.2GHz
9
10 So, in order to be able to share one OPP table lets add support for IPQ8074
11 family based of SMEM SoC ID-s as speedbin fuse is always 0 on IPQ8074.
12
13 IPQ8074 compatible is blacklisted from DT platdev as the cpufreq device
14 will get created by NVMEM CPUFreq driver.
15
16 Signed-off-by: Robert Marko <robimarko@gmail.com>
17 ---
18 Changes in v2:
19 * Print an error if SMEM ID is not part of the IPQ8074 family
20 and restrict the speed to Acorn variant (1.4GHz)
21 ---
22 drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
23 drivers/cpufreq/qcom-cpufreq-nvmem.c | 43 ++++++++++++++++++++++++++++
24 2 files changed, 44 insertions(+)
25
26 --- a/drivers/cpufreq/cpufreq-dt-platdev.c
27 +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
28 @@ -164,6 +164,7 @@ static const struct of_device_id blockli
29 { .compatible = "ti,omap3", },
30
31 { .compatible = "qcom,ipq8064", },
32 + { .compatible = "qcom,ipq8074", },
33 { .compatible = "qcom,apq8064", },
34 { .compatible = "qcom,msm8974", },
35 { .compatible = "qcom,msm8960", },
36 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
37 +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
38 @@ -31,6 +31,9 @@
39
40 #include <dt-bindings/arm/qcom,ids.h>
41
42 +#define IPQ8074_HAWKEYE_VERSION BIT(0)
43 +#define IPQ8074_ACORN_VERSION BIT(1)
44 +
45 struct qcom_cpufreq_drv;
46
47 struct qcom_cpufreq_match_data {
48 @@ -204,6 +207,41 @@ len_error:
49 return ret;
50 }
51
52 +static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
53 + struct nvmem_cell *speedbin_nvmem,
54 + char **pvs_name,
55 + struct qcom_cpufreq_drv *drv)
56 +{
57 + u32 msm_id;
58 + int ret;
59 + *pvs_name = NULL;
60 +
61 + ret = qcom_smem_get_soc_id(&msm_id);
62 + if (ret)
63 + return ret;
64 +
65 + switch (msm_id) {
66 + case QCOM_ID_IPQ8070A:
67 + case QCOM_ID_IPQ8071A:
68 + drv->versions = IPQ8074_ACORN_VERSION;
69 + break;
70 + case QCOM_ID_IPQ8072A:
71 + case QCOM_ID_IPQ8074A:
72 + case QCOM_ID_IPQ8076A:
73 + case QCOM_ID_IPQ8078A:
74 + drv->versions = IPQ8074_HAWKEYE_VERSION;
75 + break;
76 + default:
77 + dev_err(cpu_dev,
78 + "SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n",
79 + msm_id);
80 + drv->versions = IPQ8074_ACORN_VERSION;
81 + break;
82 + }
83 +
84 + return 0;
85 +}
86 +
87 static const struct qcom_cpufreq_match_data match_data_kryo = {
88 .get_version = qcom_cpufreq_kryo_name_version,
89 };
90 @@ -218,6 +256,10 @@ static const struct qcom_cpufreq_match_d
91 .genpd_names = qcs404_genpd_names,
92 };
93
94 +static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
95 + .get_version = qcom_cpufreq_ipq8074_name_version,
96 +};
97 +
98 static int qcom_cpufreq_probe(struct platform_device *pdev)
99 {
100 struct qcom_cpufreq_drv *drv;
101 @@ -363,6 +405,7 @@ static const struct of_device_id qcom_cp
102 { .compatible = "qcom,msm8996", .data = &match_data_kryo },
103 { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
104 { .compatible = "qcom,ipq8064", .data = &match_data_krait },
105 + { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
106 { .compatible = "qcom,apq8064", .data = &match_data_krait },
107 { .compatible = "qcom,msm8974", .data = &match_data_krait },
108 { .compatible = "qcom,msm8960", .data = &match_data_krait },