target/linux/ipq807x/patches-6.1/0121-arm64-dts-ipq8074-Add-WLAN-node.patch

   1 From a67d1901741c162645eda0dbdc3a2c0c2aff5cf4 Mon Sep 17 00:00:00 2001
   2 From: Robert Marko <robimarko@gmail.com>
   3 Date: Tue, 21 Dec 2021 14:49:36 +0100
   4 Subject: [PATCH] arm64: dts: ipq8074: Add WLAN node
   5
   6 IPQ8074 has a AHB based Q6v5 802.11ax radios that are supported
   7 by the ath11k.
   8
   9 Add the required DT node to enable the built-in radios.
  10
  11 Signed-off-by: Robert Marko <robimarko@gmail.com>
  12 ---
  13  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 111 ++++++++++++++++++++++++++
  14  1 file changed, 111 insertions(+)
  15
  16 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  17 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  18 @@ -994,6 +994,117 @@
  19                                 };
  20                         };
  21                 };
  22 +
  23 +               wifi: wifi@c0000000 {
  24 +                       compatible = "qcom,ipq8074-wifi";
  25 +                       reg = <0xc000000 0x2000000>;
  26 +
  27 +                       interrupts = <GIC_SPI 320 IRQ_TYPE_EDGE_RISING>,
  28 +                                    <GIC_SPI 319 IRQ_TYPE_EDGE_RISING>,
  29 +                                    <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>,
  30 +                                    <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
  31 +                                    <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
  32 +                                    <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
  33 +                                    <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
  34 +                                    <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
  35 +                                    <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
  36 +                                    <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
  37 +                                    <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
  38 +                                    <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
  39 +                                    <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
  40 +                                    <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
  41 +                                    <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
  42 +                                    <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
  43 +                                    <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
  44 +                                    <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
  45 +                                    <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
  46 +                                    <GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
  47 +                                    <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>,
  48 +                                    <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
  49 +                                    <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
  50 +                                    <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
  51 +                                    <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
  52 +                                    <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
  53 +                                    <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
  54 +                                    <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
  55 +                                    <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
  56 +                                    <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
  57 +                                    <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
  58 +                                    <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
  59 +                                    <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
  60 +                                    <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
  61 +                                    <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
  62 +                                    <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
  63 +                                    <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
  64 +                                    <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
  65 +                                    <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
  66 +                                    <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
  67 +                                    <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
  68 +                                    <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
  69 +                                    <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
  70 +                                    <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
  71 +                                    <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
  72 +                                    <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
  73 +                                    <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
  74 +                                    <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
  75 +                                    <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
  76 +                                    <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
  77 +                                    <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
  78 +
  79 +                       interrupt-names = "misc-pulse1",
  80 +                                         "misc-latch",
  81 +                                         "sw-exception",
  82 +                                         "ce0",
  83 +                                         "ce1",
  84 +                                         "ce2",
  85 +                                         "ce3",
  86 +                                         "ce4",
  87 +                                         "ce5",
  88 +                                         "ce6",
  89 +                                         "ce7",
  90 +                                         "ce8",
  91 +                                         "ce9",
  92 +                                         "ce10",
  93 +                                         "ce11",
  94 +                                         "host2wbm-desc-feed",
  95 +                                         "host2reo-re-injection",
  96 +                                         "host2reo-command",
  97 +                                         "host2rxdma-monitor-ring3",
  98 +                                         "host2rxdma-monitor-ring2",
  99 +                                         "host2rxdma-monitor-ring1",
 100 +                                         "reo2ost-exception",
 101 +                                         "wbm2host-rx-release",
 102 +                                         "reo2host-status",
 103 +                                         "reo2host-destination-ring4",
 104 +                                         "reo2host-destination-ring3",
 105 +                                         "reo2host-destination-ring2",
 106 +                                         "reo2host-destination-ring1",
 107 +                                         "rxdma2host-monitor-destination-mac3",
 108 +                                         "rxdma2host-monitor-destination-mac2",
 109 +                                         "rxdma2host-monitor-destination-mac1",
 110 +                                         "ppdu-end-interrupts-mac3",
 111 +                                         "ppdu-end-interrupts-mac2",
 112 +                                         "ppdu-end-interrupts-mac1",
 113 +                                         "rxdma2host-monitor-status-ring-mac3",
 114 +                                         "rxdma2host-monitor-status-ring-mac2",
 115 +                                         "rxdma2host-monitor-status-ring-mac1",
 116 +                                         "host2rxdma-host-buf-ring-mac3",
 117 +                                         "host2rxdma-host-buf-ring-mac2",
 118 +                                         "host2rxdma-host-buf-ring-mac1",
 119 +                                         "rxdma2host-destination-ring-mac3",
 120 +                                         "rxdma2host-destination-ring-mac2",
 121 +                                         "rxdma2host-destination-ring-mac1",
 122 +                                         "host2tcl-input-ring4",
 123 +                                         "host2tcl-input-ring3",
 124 +                                         "host2tcl-input-ring2",
 125 +                                         "host2tcl-input-ring1",
 126 +                                         "wbm2host-tx-completions-ring3",
 127 +                                         "wbm2host-tx-completions-ring2",
 128 +                                         "wbm2host-tx-completions-ring1",
 129 +                                         "tcl2host-status-ring";
 130 +                       qcom,rproc = <&q6v5_wcss>;
 131 +                       status = "disabled";
 132 +               };
 133         };
 134
 135         timer {