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[openwrt/staging/jow.git] / target / linux / ipq40xx / files / drivers / net / dsa / qca / qca8k-ipq4019.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2011-2012, 2020-2021 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2016 John Crispin <john@phrozen.org>
7 * Copyright (c) 2021 Robert Marko <robert.marko@sartura.hr>
8 */
9
10 #include <linux/version.h>
11 #include <linux/etherdevice.h>
12 #include <linux/if_bridge.h>
13 #include <linux/mdio.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/netdevice.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_net.h>
19 #include <linux/of_platform.h>
20 #include <linux/phy.h>
21 #include <linux/phylink.h>
22 #include <linux/reset.h>
23 #include <net/dsa.h>
24
25 #include "qca8k-ipq4019.h"
26
27 #define MIB_DESC(_s, _o, _n) \
28 { \
29 .size = (_s), \
30 .offset = (_o), \
31 .name = (_n), \
32 }
33
34 static const struct qca8k_mib_desc ar8327_mib[] = {
35 MIB_DESC(1, 0x00, "RxBroad"),
36 MIB_DESC(1, 0x04, "RxPause"),
37 MIB_DESC(1, 0x08, "RxMulti"),
38 MIB_DESC(1, 0x0c, "RxFcsErr"),
39 MIB_DESC(1, 0x10, "RxAlignErr"),
40 MIB_DESC(1, 0x14, "RxRunt"),
41 MIB_DESC(1, 0x18, "RxFragment"),
42 MIB_DESC(1, 0x1c, "Rx64Byte"),
43 MIB_DESC(1, 0x20, "Rx128Byte"),
44 MIB_DESC(1, 0x24, "Rx256Byte"),
45 MIB_DESC(1, 0x28, "Rx512Byte"),
46 MIB_DESC(1, 0x2c, "Rx1024Byte"),
47 MIB_DESC(1, 0x30, "Rx1518Byte"),
48 MIB_DESC(1, 0x34, "RxMaxByte"),
49 MIB_DESC(1, 0x38, "RxTooLong"),
50 MIB_DESC(2, 0x3c, "RxGoodByte"),
51 MIB_DESC(2, 0x44, "RxBadByte"),
52 MIB_DESC(1, 0x4c, "RxOverFlow"),
53 MIB_DESC(1, 0x50, "Filtered"),
54 MIB_DESC(1, 0x54, "TxBroad"),
55 MIB_DESC(1, 0x58, "TxPause"),
56 MIB_DESC(1, 0x5c, "TxMulti"),
57 MIB_DESC(1, 0x60, "TxUnderRun"),
58 MIB_DESC(1, 0x64, "Tx64Byte"),
59 MIB_DESC(1, 0x68, "Tx128Byte"),
60 MIB_DESC(1, 0x6c, "Tx256Byte"),
61 MIB_DESC(1, 0x70, "Tx512Byte"),
62 MIB_DESC(1, 0x74, "Tx1024Byte"),
63 MIB_DESC(1, 0x78, "Tx1518Byte"),
64 MIB_DESC(1, 0x7c, "TxMaxByte"),
65 MIB_DESC(1, 0x80, "TxOverSize"),
66 MIB_DESC(2, 0x84, "TxByte"),
67 MIB_DESC(1, 0x8c, "TxCollision"),
68 MIB_DESC(1, 0x90, "TxAbortCol"),
69 MIB_DESC(1, 0x94, "TxMultiCol"),
70 MIB_DESC(1, 0x98, "TxSingleCol"),
71 MIB_DESC(1, 0x9c, "TxExcDefer"),
72 MIB_DESC(1, 0xa0, "TxDefer"),
73 MIB_DESC(1, 0xa4, "TxLateCol"),
74 MIB_DESC(1, 0xa8, "RXUnicast"),
75 MIB_DESC(1, 0xac, "TXunicast"),
76 };
77
78 static int
79 qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
80 {
81 return regmap_read(priv->regmap, reg, val);
82 }
83
84 static int
85 qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
86 {
87 return regmap_write(priv->regmap, reg, val);
88 }
89
90 static int
91 qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
92 {
93 return regmap_update_bits(priv->regmap, reg, mask, write_val);
94 }
95
96 static int
97 qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)
98 {
99 return regmap_set_bits(priv->regmap, reg, val);
100 }
101
102 static int
103 qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)
104 {
105 return regmap_clear_bits(priv->regmap, reg, val);
106 }
107
108 static const struct regmap_range qca8k_readable_ranges[] = {
109 regmap_reg_range(0x0000, 0x00e4), /* Global control */
110 regmap_reg_range(0x0100, 0x0168), /* EEE control */
111 regmap_reg_range(0x0200, 0x0270), /* Parser control */
112 regmap_reg_range(0x0400, 0x0454), /* ACL */
113 regmap_reg_range(0x0600, 0x0718), /* Lookup */
114 regmap_reg_range(0x0800, 0x0b70), /* QM */
115 regmap_reg_range(0x0c00, 0x0c80), /* PKT */
116 regmap_reg_range(0x0e00, 0x0e98), /* L3 */
117 regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
118 regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
119 regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
120 regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
121 regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
122 regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
123 regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
124
125 };
126
127 static const struct regmap_access_table qca8k_readable_table = {
128 .yes_ranges = qca8k_readable_ranges,
129 .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
130 };
131
132 static struct regmap_config qca8k_ipq4019_regmap_config = {
133 .reg_bits = 32,
134 .val_bits = 32,
135 .reg_stride = 4,
136 .max_register = 0x16ac, /* end MIB - Port6 range */
137 .rd_table = &qca8k_readable_table,
138 };
139
140 static struct regmap_config qca8k_ipq4019_psgmii_phy_regmap_config = {
141 .name = "psgmii-phy",
142 .reg_bits = 32,
143 .val_bits = 32,
144 .reg_stride = 4,
145 .max_register = 0x7fc,
146 };
147
148 static int
149 qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
150 {
151 u32 val;
152
153 return regmap_read_poll_timeout(priv->regmap, reg, val,
154 !(val & mask),
155 0,
156 QCA8K_BUSY_WAIT_TIMEOUT);
157 }
158
159 static int
160 qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
161 {
162 u32 reg[4], val;
163 int i, ret;
164
165 /* load the ARL table into an array */
166 for (i = 0; i < 4; i++) {
167 ret = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4), &val);
168 if (ret < 0)
169 return ret;
170
171 reg[i] = val;
172 }
173
174 /* vid - 83:72 */
175 fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
176 /* aging - 67:64 */
177 fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
178 /* portmask - 54:48 */
179 fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
180 /* mac - 47:0 */
181 fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
182 fdb->mac[1] = reg[1] & 0xff;
183 fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
184 fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
185 fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
186 fdb->mac[5] = reg[0] & 0xff;
187
188 return 0;
189 }
190
191 static void
192 qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
193 u8 aging)
194 {
195 u32 reg[3] = { 0 };
196 int i;
197
198 /* vid - 83:72 */
199 reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
200 /* aging - 67:64 */
201 reg[2] |= aging & QCA8K_ATU_STATUS_M;
202 /* portmask - 54:48 */
203 reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
204 /* mac - 47:0 */
205 reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
206 reg[1] |= mac[1];
207 reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
208 reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
209 reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
210 reg[0] |= mac[5];
211
212 /* load the array into the ARL table */
213 for (i = 0; i < 3; i++)
214 qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]);
215 }
216
217 static int
218 qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
219 {
220 u32 reg;
221 int ret;
222
223 /* Set the command and FDB index */
224 reg = QCA8K_ATU_FUNC_BUSY;
225 reg |= cmd;
226 if (port >= 0) {
227 reg |= QCA8K_ATU_FUNC_PORT_EN;
228 reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
229 }
230
231 /* Write the function register triggering the table access */
232 ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
233 if (ret)
234 return ret;
235
236 /* wait for completion */
237 ret = qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY);
238 if (ret)
239 return ret;
240
241 /* Check for table full violation when adding an entry */
242 if (cmd == QCA8K_FDB_LOAD) {
243 ret = qca8k_read(priv, QCA8K_REG_ATU_FUNC, &reg);
244 if (ret < 0)
245 return ret;
246 if (reg & QCA8K_ATU_FUNC_FULL)
247 return -1;
248 }
249
250 return 0;
251 }
252
253 static int
254 qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port)
255 {
256 int ret;
257
258 qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
259 ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
260 if (ret < 0)
261 return ret;
262
263 return qca8k_fdb_read(priv, fdb);
264 }
265
266 static int
267 qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask,
268 u16 vid, u8 aging)
269 {
270 int ret;
271
272 mutex_lock(&priv->reg_mutex);
273 qca8k_fdb_write(priv, vid, port_mask, mac, aging);
274 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
275 mutex_unlock(&priv->reg_mutex);
276
277 return ret;
278 }
279
280 static int
281 qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid)
282 {
283 int ret;
284
285 mutex_lock(&priv->reg_mutex);
286 qca8k_fdb_write(priv, vid, port_mask, mac, 0);
287 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
288 mutex_unlock(&priv->reg_mutex);
289
290 return ret;
291 }
292
293 static void
294 qca8k_fdb_flush(struct qca8k_priv *priv)
295 {
296 mutex_lock(&priv->reg_mutex);
297 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
298 mutex_unlock(&priv->reg_mutex);
299 }
300
301 static int
302 qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid)
303 {
304 u32 reg;
305 int ret;
306
307 /* Set the command and VLAN index */
308 reg = QCA8K_VTU_FUNC1_BUSY;
309 reg |= cmd;
310 reg |= vid << QCA8K_VTU_FUNC1_VID_S;
311
312 /* Write the function register triggering the table access */
313 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
314 if (ret)
315 return ret;
316
317 /* wait for completion */
318 ret = qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY);
319 if (ret)
320 return ret;
321
322 /* Check for table full violation when adding an entry */
323 if (cmd == QCA8K_VLAN_LOAD) {
324 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC1, &reg);
325 if (ret < 0)
326 return ret;
327 if (reg & QCA8K_VTU_FUNC1_FULL)
328 return -ENOMEM;
329 }
330
331 return 0;
332 }
333
334 static int
335 qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged)
336 {
337 u32 reg;
338 int ret;
339
340 /*
341 We do the right thing with VLAN 0 and treat it as untagged while
342 preserving the tag on egress.
343 */
344 if (vid == 0)
345 return 0;
346
347 mutex_lock(&priv->reg_mutex);
348 ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
349 if (ret < 0)
350 goto out;
351
352 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
353 if (ret < 0)
354 goto out;
355 reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;
356 reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port));
357 if (untagged)
358 reg |= QCA8K_VTU_FUNC0_EG_MODE_UNTAG <<
359 QCA8K_VTU_FUNC0_EG_MODE_S(port);
360 else
361 reg |= QCA8K_VTU_FUNC0_EG_MODE_TAG <<
362 QCA8K_VTU_FUNC0_EG_MODE_S(port);
363
364 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
365 if (ret)
366 goto out;
367 ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
368
369 out:
370 mutex_unlock(&priv->reg_mutex);
371
372 return ret;
373 }
374
375 static int
376 qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid)
377 {
378 u32 reg, mask;
379 int ret, i;
380 bool del;
381
382 mutex_lock(&priv->reg_mutex);
383 ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
384 if (ret < 0)
385 goto out;
386
387 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
388 if (ret < 0)
389 goto out;
390 reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port));
391 reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT <<
392 QCA8K_VTU_FUNC0_EG_MODE_S(port);
393
394 /* Check if we're the last member to be removed */
395 del = true;
396 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
397 mask = QCA8K_VTU_FUNC0_EG_MODE_NOT;
398 mask <<= QCA8K_VTU_FUNC0_EG_MODE_S(i);
399
400 if ((reg & mask) != mask) {
401 del = false;
402 break;
403 }
404 }
405
406 if (del) {
407 ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid);
408 } else {
409 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
410 if (ret)
411 goto out;
412 ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
413 }
414
415 out:
416 mutex_unlock(&priv->reg_mutex);
417
418 return ret;
419 }
420
421 static int
422 qca8k_mib_init(struct qca8k_priv *priv)
423 {
424 int ret;
425
426 mutex_lock(&priv->reg_mutex);
427 ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
428 if (ret)
429 goto exit;
430
431 ret = qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
432 if (ret)
433 goto exit;
434
435 ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
436 if (ret)
437 goto exit;
438
439 ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
440
441 exit:
442 mutex_unlock(&priv->reg_mutex);
443 return ret;
444 }
445
446 static void
447 qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
448 {
449 u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
450
451 /* Port 0 is internally connected to the CPU
452 * TODO: Probably check for RGMII as well if it doesnt work
453 * in RGMII mode.
454 */
455 if (port > QCA8K_CPU_PORT)
456 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
457
458 if (enable)
459 qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask);
460 else
461 qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);
462 }
463
464 static int
465 qca8k_setup_port(struct dsa_switch *ds, int port)
466 {
467 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
468 int ret;
469
470 /* CPU port gets connected to all user ports of the switch */
471 if (dsa_is_cpu_port(ds, port)) {
472 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
473 QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
474 if (ret)
475 return ret;
476
477 /* Disable CPU ARP Auto-learning by default */
478 ret = qca8k_reg_clear(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
479 QCA8K_PORT_LOOKUP_LEARN);
480 if (ret)
481 return ret;
482 }
483
484 /* Individual user ports get connected to CPU port only */
485 if (dsa_is_user_port(ds, port)) {
486 int shift = 16 * (port % 2);
487
488 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
489 QCA8K_PORT_LOOKUP_MEMBER,
490 BIT(QCA8K_CPU_PORT));
491 if (ret)
492 return ret;
493
494 /* Enable ARP Auto-learning by default */
495 ret = qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(port),
496 QCA8K_PORT_LOOKUP_LEARN);
497 if (ret)
498 return ret;
499
500 /* For port based vlans to work we need to set the
501 * default egress vid
502 */
503 ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
504 0xfff << shift,
505 QCA8K_PORT_VID_DEF << shift);
506 if (ret)
507 return ret;
508
509 ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
510 QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
511 QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
512 if (ret)
513 return ret;
514 }
515
516 return 0;
517 }
518
519 static int
520 qca8k_setup(struct dsa_switch *ds)
521 {
522 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
523 int ret, i;
524
525 /* Make sure that port 0 is the cpu port */
526 if (!dsa_is_cpu_port(ds, 0)) {
527 dev_err(priv->dev, "port 0 is not the CPU port");
528 return -EINVAL;
529 }
530
531 /* Enable CPU Port */
532 ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
533 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
534 if (ret) {
535 dev_err(priv->dev, "failed enabling CPU port");
536 return ret;
537 }
538
539 /* Enable MIB counters */
540 ret = qca8k_mib_init(priv);
541 if (ret)
542 dev_warn(priv->dev, "MIB init failed");
543
544 /* Enable QCA header mode on the cpu port */
545 ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
546 QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
547 QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
548 if (ret) {
549 dev_err(priv->dev, "failed enabling QCA header mode");
550 return ret;
551 }
552
553 /* Disable forwarding by default on all ports */
554 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
555 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
556 QCA8K_PORT_LOOKUP_MEMBER, 0);
557 if (ret)
558 return ret;
559 }
560
561 /* Disable MAC by default on all ports */
562 for (i = 1; i < QCA8K_NUM_PORTS; i++)
563 qca8k_port_set_status(priv, i, 0);
564
565 /* Forward all unknown frames to CPU port for Linux processing */
566 ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
567 BIT(QCA8K_CPU_PORT) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
568 BIT(QCA8K_CPU_PORT) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
569 BIT(QCA8K_CPU_PORT) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
570 BIT(QCA8K_CPU_PORT) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
571 if (ret)
572 return ret;
573
574 /* Setup connection between CPU port & user ports */
575 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
576 ret = qca8k_setup_port(ds, i);
577 if (ret)
578 return ret;
579 }
580
581 /* Setup our port MTUs to match power on defaults */
582 for (i = 0; i < QCA8K_NUM_PORTS; i++)
583 /* Set per port MTU to 1500 as the MTU change function
584 * will add the overhead and if its set to 1518 then it
585 * will apply the overhead again and we will end up with
586 * MTU of 1536 instead of 1518
587 */
588 priv->port_mtu[i] = ETH_DATA_LEN;
589 ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
590 if (ret)
591 dev_warn(priv->dev, "failed setting MTU settings");
592
593 /* Flush the FDB table */
594 qca8k_fdb_flush(priv);
595
596 /* We don't have interrupts for link changes, so we need to poll */
597 ds->pcs_poll = true;
598
599 /* CPU port HW learning doesnt work correctly, so let DSA handle it */
600 ds->assisted_learning_on_cpu_port = true;
601
602 return 0;
603 }
604
605 static int psgmii_vco_calibrate(struct qca8k_priv *priv)
606 {
607 int val, ret;
608
609 if (!priv->psgmii_ethphy) {
610 dev_err(priv->dev, "PSGMII eth PHY missing, calibration failed!\n");
611 return -ENODEV;
612 }
613
614 /* Fix PSGMII RX 20bit */
615 ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5b);
616 /* Reset PHY PSGMII */
617 ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x1b);
618 /* Release PHY PSGMII reset */
619 ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5b);
620
621 /* Poll for VCO PLL calibration finish - Malibu(QCA8075) */
622 ret = phy_read_mmd_poll_timeout(priv->psgmii_ethphy,
623 MDIO_MMD_PMAPMD,
624 0x28, val,
625 (val & BIT(0)),
626 10000, 1000000,
627 false);
628 if (ret) {
629 dev_err(priv->dev, "QCA807x PSGMII VCO calibration PLL not ready\n");
630 return ret;
631 }
632 mdelay(50);
633
634 /* Freeze PSGMII RX CDR */
635 ret = phy_write(priv->psgmii_ethphy, MII_RESV2, 0x2230);
636
637 /* Start PSGMIIPHY VCO PLL calibration */
638 ret = regmap_set_bits(priv->psgmii,
639 PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_1,
640 PSGMIIPHY_REG_PLL_VCO_CALIB_RESTART);
641
642 /* Poll for PSGMIIPHY PLL calibration finish - Dakota(IPQ40xx) */
643 ret = regmap_read_poll_timeout(priv->psgmii,
644 PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_2,
645 val, val & PSGMIIPHY_REG_PLL_VCO_CALIB_READY,
646 10000, 1000000);
647 if (ret) {
648 dev_err(priv->dev, "IPQ PSGMIIPHY VCO calibration PLL not ready\n");
649 return ret;
650 }
651 mdelay(50);
652
653 /* Release PSGMII RX CDR */
654 ret = phy_write(priv->psgmii_ethphy, MII_RESV2, 0x3230);
655 /* Release PSGMII RX 20bit */
656 ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5f);
657 mdelay(200);
658
659 return ret;
660 }
661
662 static void
663 qca8k_switch_port_loopback_on_off(struct qca8k_priv *priv, int port, int on)
664 {
665 u32 val = QCA8K_PORT_LOOKUP_LOOPBACK;
666
667 if (on == 0)
668 val = 0;
669
670 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
671 QCA8K_PORT_LOOKUP_LOOPBACK, val);
672 }
673
674 static int
675 qca8k_wait_for_phy_link_state(struct phy_device *phy, int need_status)
676 {
677 int a;
678 u16 status;
679
680 for (a = 0; a < 100; a++) {
681 status = phy_read(phy, MII_QCA8075_SSTATUS);
682 status &= QCA8075_PHY_SPEC_STATUS_LINK;
683 status = !!status;
684 if (status == need_status)
685 return 0;
686 mdelay(8);
687 }
688
689 return -1;
690 }
691
692 static void
693 qca8k_phy_loopback_on_off(struct qca8k_priv *priv, struct phy_device *phy,
694 int sw_port, int on)
695 {
696 if (on) {
697 phy_write(phy, MII_BMCR, BMCR_ANENABLE | BMCR_RESET);
698 phy_modify(phy, MII_BMCR, BMCR_PDOWN, BMCR_PDOWN);
699 qca8k_wait_for_phy_link_state(phy, 0);
700 qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port), 0);
701 phy_write(phy, MII_BMCR,
702 BMCR_SPEED1000 |
703 BMCR_FULLDPLX |
704 BMCR_LOOPBACK);
705 qca8k_wait_for_phy_link_state(phy, 1);
706 qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port),
707 QCA8K_PORT_STATUS_SPEED_1000 |
708 QCA8K_PORT_STATUS_TXMAC |
709 QCA8K_PORT_STATUS_RXMAC |
710 QCA8K_PORT_STATUS_DUPLEX);
711 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(sw_port),
712 QCA8K_PORT_LOOKUP_STATE_FORWARD,
713 QCA8K_PORT_LOOKUP_STATE_FORWARD);
714 } else { /* off */
715 qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port), 0);
716 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(sw_port),
717 QCA8K_PORT_LOOKUP_STATE_DISABLED,
718 QCA8K_PORT_LOOKUP_STATE_DISABLED);
719 phy_write(phy, MII_BMCR, BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_RESET);
720 /* turn off the power of the phys - so that unused
721 ports do not raise links */
722 phy_modify(phy, MII_BMCR, BMCR_PDOWN, BMCR_PDOWN);
723 }
724 }
725
726 static void
727 qca8k_phy_pkt_gen_prep(struct qca8k_priv *priv, struct phy_device *phy,
728 int pkts_num, int on)
729 {
730 if (on) {
731 /* enable CRC checker and packets counters */
732 phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT, 0);
733 phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT,
734 QCA8075_MMD7_CNT_FRAME_CHK_EN | QCA8075_MMD7_CNT_SELFCLR);
735 qca8k_wait_for_phy_link_state(phy, 1);
736 /* packet number */
737 phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_NUMB, pkts_num);
738 /* pkt size - 1504 bytes + 20 bytes */
739 phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_SIZE, 1504);
740 } else { /* off */
741 /* packet number */
742 phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_NUMB, 0);
743 /* disable CRC checker and packet counter */
744 phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT, 0);
745 /* disable traffic gen */
746 phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL, 0);
747 }
748 }
749
750 static void
751 qca8k_wait_for_phy_pkt_gen_fin(struct qca8k_priv *priv, struct phy_device *phy)
752 {
753 int val;
754 /* wait for all traffic end: 4096(pkt num)*1524(size)*8ns(125MHz)=49938us */
755 phy_read_mmd_poll_timeout(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL,
756 val, !(val & QCA8075_MMD7_PKT_GEN_INPROGR),
757 50000, 1000000, true);
758 }
759
760 static void
761 qca8k_start_phy_pkt_gen(struct phy_device *phy)
762 {
763 /* start traffic gen */
764 phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL,
765 QCA8075_MMD7_PKT_GEN_START | QCA8075_MMD7_PKT_GEN_INPROGR);
766 }
767
768 static int
769 qca8k_start_all_phys_pkt_gens(struct qca8k_priv *priv)
770 {
771 struct phy_device *phy;
772 phy = phy_device_create(priv->bus, QCA8075_MDIO_BRDCST_PHY_ADDR,
773 0, 0, NULL);
774 if (!phy) {
775 dev_err(priv->dev, "unable to create mdio broadcast PHY(0x%x)\n",
776 QCA8075_MDIO_BRDCST_PHY_ADDR);
777 return -ENODEV;
778 }
779
780 qca8k_start_phy_pkt_gen(phy);
781
782 phy_device_free(phy);
783 return 0;
784 }
785
786 static int
787 qca8k_get_phy_pkt_gen_test_result(struct phy_device *phy, int pkts_num)
788 {
789 u32 tx_ok, tx_error;
790 u32 rx_ok, rx_error;
791 u32 tx_ok_high16;
792 u32 rx_ok_high16;
793 u32 tx_all_ok, rx_all_ok;
794
795 /* check counters */
796 tx_ok = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_RECV_CNT_LO);
797 tx_ok_high16 = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_RECV_CNT_HI);
798 tx_error = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_ERR_CNT);
799 rx_ok = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_RECV_CNT_LO);
800 rx_ok_high16 = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_RECV_CNT_HI);
801 rx_error = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_ERR_CNT);
802 tx_all_ok = tx_ok + (tx_ok_high16 << 16);
803 rx_all_ok = rx_ok + (rx_ok_high16 << 16);
804
805 if (tx_all_ok < pkts_num)
806 return -1;
807 if(rx_all_ok < pkts_num)
808 return -2;
809 if(tx_error)
810 return -3;
811 if(rx_error)
812 return -4;
813 return 0; /* test is ok */
814 }
815
816 static
817 void qca8k_phy_broadcast_write_on_off(struct qca8k_priv *priv,
818 struct phy_device *phy, int on)
819 {
820 u32 val;
821
822 val = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_MDIO_BRDCST_WRITE);
823
824 if (on == 0)
825 val &= ~QCA8075_MMD7_MDIO_BRDCST_WRITE_EN;
826 else
827 val |= QCA8075_MMD7_MDIO_BRDCST_WRITE_EN;
828
829 phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_MDIO_BRDCST_WRITE, val);
830 }
831
832 static int
833 qca8k_test_dsa_port_for_errors(struct qca8k_priv *priv, struct phy_device *phy,
834 int port, int test_phase)
835 {
836 int res = 0;
837 const int test_pkts_num = QCA8075_PKT_GEN_PKTS_COUNT;
838
839 if (test_phase == 1) { /* start test preps */
840 qca8k_phy_loopback_on_off(priv, phy, port, 1);
841 qca8k_switch_port_loopback_on_off(priv, port, 1);
842 qca8k_phy_broadcast_write_on_off(priv, phy, 1);
843 qca8k_phy_pkt_gen_prep(priv, phy, test_pkts_num, 1);
844 } else if (test_phase == 2) {
845 /* wait for test results, collect it and cleanup */
846 qca8k_wait_for_phy_pkt_gen_fin(priv, phy);
847 res = qca8k_get_phy_pkt_gen_test_result(phy, test_pkts_num);
848 qca8k_phy_pkt_gen_prep(priv, phy, test_pkts_num, 0);
849 qca8k_phy_broadcast_write_on_off(priv, phy, 0);
850 qca8k_switch_port_loopback_on_off(priv, port, 0);
851 qca8k_phy_loopback_on_off(priv, phy, port, 0);
852 }
853
854 return res;
855 }
856
857 static int
858 qca8k_do_dsa_sw_ports_self_test(struct qca8k_priv *priv, int parallel_test)
859 {
860 struct device_node *dn = priv->dev->of_node;
861 struct device_node *ports, *port;
862 struct device_node *phy_dn;
863 struct phy_device *phy;
864 int reg, err = 0, test_phase;
865 u32 tests_result = 0;
866
867 ports = of_get_child_by_name(dn, "ports");
868 if (!ports) {
869 dev_err(priv->dev, "no ports child node found\n");
870 return -EINVAL;
871 }
872
873 for (test_phase = 1; test_phase <= 2; test_phase++) {
874 if (parallel_test && test_phase == 2) {
875 err = qca8k_start_all_phys_pkt_gens(priv);
876 if (err)
877 goto error;
878 }
879 for_each_available_child_of_node(ports, port) {
880 err = of_property_read_u32(port, "reg", &reg);
881 if (err)
882 goto error;
883 if (reg >= QCA8K_NUM_PORTS) {
884 err = -EINVAL;
885 goto error;
886 }
887 phy_dn = of_parse_phandle(port, "phy-handle", 0);
888 if (phy_dn) {
889 phy = of_phy_find_device(phy_dn);
890 of_node_put(phy_dn);
891 if (phy) {
892 int result;
893 result = qca8k_test_dsa_port_for_errors(priv,
894 phy, reg, test_phase);
895 if (!parallel_test && test_phase == 1)
896 qca8k_start_phy_pkt_gen(phy);
897 put_device(&phy->mdio.dev);
898 if (test_phase == 2) {
899 tests_result <<= 1;
900 if (result)
901 tests_result |= 1;
902 }
903 }
904 }
905 }
906 }
907
908 end:
909 of_node_put(ports);
910 qca8k_fdb_flush(priv);
911 return tests_result;
912 error:
913 tests_result |= 0xf000;
914 goto end;
915 }
916
917 static int
918 psgmii_vco_calibrate_and_test(struct dsa_switch *ds)
919 {
920 int ret, a, test_result;
921 struct qca8k_priv *priv = ds->priv;
922
923 for (a = 0; a <= QCA8K_PSGMII_CALB_NUM; a++) {
924 ret = psgmii_vco_calibrate(priv);
925 if (ret)
926 return ret;
927 /* first we run serial test */
928 test_result = qca8k_do_dsa_sw_ports_self_test(priv, 0);
929 /* and if it is ok then we run the test in parallel */
930 if (!test_result)
931 test_result = qca8k_do_dsa_sw_ports_self_test(priv, 1);
932 if (!test_result) {
933 if (a > 0) {
934 dev_warn(priv->dev, "PSGMII work was stabilized after %d "
935 "calibration retries !\n", a);
936 }
937 return 0;
938 } else {
939 schedule();
940 if (a > 0 && a % 10 == 0) {
941 dev_err(priv->dev, "PSGMII work is unstable !!! "
942 "Let's try to wait a bit ... %d\n", a);
943 set_current_state(TASK_INTERRUPTIBLE);
944 schedule_timeout(msecs_to_jiffies(a * 100));
945 }
946 }
947 }
948
949 panic("PSGMII work is unstable !!! "
950 "Repeated recalibration attempts did not help(0x%x) !\n",
951 test_result);
952
953 return -EFAULT;
954 }
955
956 static int
957 ipq4019_psgmii_configure(struct dsa_switch *ds)
958 {
959 struct qca8k_priv *priv = ds->priv;
960 int ret;
961
962 if (!priv->psgmii_calibrated) {
963 ret = psgmii_vco_calibrate_and_test(ds);
964
965 ret = regmap_clear_bits(priv->psgmii, PSGMIIPHY_MODE_CONTROL,
966 PSGMIIPHY_MODE_ATHR_CSCO_MODE_25M);
967 ret = regmap_write(priv->psgmii, PSGMIIPHY_TX_CONTROL,
968 PSGMIIPHY_TX_CONTROL_MAGIC_VALUE);
969
970 priv->psgmii_calibrated = true;
971
972 return ret;
973 }
974
975 return 0;
976 }
977
978 static void
979 qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
980 const struct phylink_link_state *state)
981 {
982 struct qca8k_priv *priv = ds->priv;
983
984 switch (port) {
985 case 0:
986 /* CPU port, no configuration needed */
987 return;
988 case 1:
989 case 2:
990 case 3:
991 if (state->interface == PHY_INTERFACE_MODE_PSGMII)
992 if (ipq4019_psgmii_configure(ds))
993 dev_err(ds->dev, "PSGMII configuration failed!\n");
994 return;
995 case 4:
996 case 5:
997 if (state->interface == PHY_INTERFACE_MODE_RGMII ||
998 state->interface == PHY_INTERFACE_MODE_RGMII_ID ||
999 state->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1000 state->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
1001 qca8k_reg_set(priv, QCA8K_REG_RGMII_CTRL, QCA8K_RGMII_CTRL_CLK);
1002 }
1003
1004 if (state->interface == PHY_INTERFACE_MODE_PSGMII)
1005 if (ipq4019_psgmii_configure(ds))
1006 dev_err(ds->dev, "PSGMII configuration failed!\n");
1007 return;
1008 default:
1009 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1010 return;
1011 }
1012 }
1013
1014 static void
1015 qca8k_phylink_validate(struct dsa_switch *ds, int port,
1016 unsigned long *supported,
1017 struct phylink_link_state *state)
1018 {
1019 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1020
1021 switch (port) {
1022 case 0: /* CPU port */
1023 if (state->interface != PHY_INTERFACE_MODE_INTERNAL)
1024 goto unsupported;
1025 break;
1026 case 1:
1027 case 2:
1028 case 3:
1029 /* Only PSGMII mode is supported */
1030 if (state->interface != PHY_INTERFACE_MODE_PSGMII)
1031 goto unsupported;
1032 break;
1033 case 4:
1034 case 5:
1035 /* PSGMII and RGMII modes are supported */
1036 if (state->interface != PHY_INTERFACE_MODE_PSGMII &&
1037 state->interface != PHY_INTERFACE_MODE_RGMII &&
1038 state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1039 state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1040 state->interface != PHY_INTERFACE_MODE_RGMII_TXID)
1041 goto unsupported;
1042 break;
1043 default:
1044 unsupported:
1045 dev_warn(ds->dev, "interface '%s' (%d) on port %d is not supported\n",
1046 phy_modes(state->interface), state->interface, port);
1047 linkmode_zero(supported);
1048 return;
1049 }
1050
1051 if (port == 0) {
1052 phylink_set_port_modes(mask);
1053
1054 phylink_set(mask, 1000baseT_Full);
1055
1056 phylink_set(mask, Pause);
1057 phylink_set(mask, Asym_Pause);
1058
1059 linkmode_and(supported, supported, mask);
1060 linkmode_and(state->advertising, state->advertising, mask);
1061 } else {
1062 /* Simply copy what PHYs tell us */
1063 linkmode_copy(state->advertising, supported);
1064 }
1065 }
1066
1067 static int
1068 qca8k_phylink_mac_link_state(struct dsa_switch *ds, int port,
1069 struct phylink_link_state *state)
1070 {
1071 struct qca8k_priv *priv = ds->priv;
1072 u32 reg;
1073 int ret;
1074
1075 ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), &reg);
1076 if (ret < 0)
1077 return ret;
1078
1079 state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
1080 state->an_complete = state->link;
1081 state->an_enabled = !!(reg & QCA8K_PORT_STATUS_LINK_AUTO);
1082 state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL :
1083 DUPLEX_HALF;
1084
1085 switch (reg & QCA8K_PORT_STATUS_SPEED) {
1086 case QCA8K_PORT_STATUS_SPEED_10:
1087 state->speed = SPEED_10;
1088 break;
1089 case QCA8K_PORT_STATUS_SPEED_100:
1090 state->speed = SPEED_100;
1091 break;
1092 case QCA8K_PORT_STATUS_SPEED_1000:
1093 state->speed = SPEED_1000;
1094 break;
1095 default:
1096 state->speed = SPEED_UNKNOWN;
1097 break;
1098 }
1099
1100 state->pause = MLO_PAUSE_NONE;
1101 if (reg & QCA8K_PORT_STATUS_RXFLOW)
1102 state->pause |= MLO_PAUSE_RX;
1103 if (reg & QCA8K_PORT_STATUS_TXFLOW)
1104 state->pause |= MLO_PAUSE_TX;
1105
1106 return 1;
1107 }
1108
1109 static void
1110 qca8k_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
1111 phy_interface_t interface)
1112 {
1113 struct qca8k_priv *priv = ds->priv;
1114
1115 qca8k_port_set_status(priv, port, 0);
1116 }
1117
1118 static void
1119 qca8k_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
1120 phy_interface_t interface, struct phy_device *phydev,
1121 int speed, int duplex, bool tx_pause, bool rx_pause)
1122 {
1123 struct qca8k_priv *priv = ds->priv;
1124 u32 reg;
1125
1126 if (phylink_autoneg_inband(mode)) {
1127 reg = QCA8K_PORT_STATUS_LINK_AUTO;
1128 } else {
1129 switch (speed) {
1130 case SPEED_10:
1131 reg = QCA8K_PORT_STATUS_SPEED_10;
1132 break;
1133 case SPEED_100:
1134 reg = QCA8K_PORT_STATUS_SPEED_100;
1135 break;
1136 case SPEED_1000:
1137 reg = QCA8K_PORT_STATUS_SPEED_1000;
1138 break;
1139 default:
1140 reg = QCA8K_PORT_STATUS_LINK_AUTO;
1141 break;
1142 }
1143
1144 if (duplex == DUPLEX_FULL)
1145 reg |= QCA8K_PORT_STATUS_DUPLEX;
1146
1147 if (rx_pause || dsa_is_cpu_port(ds, port))
1148 reg |= QCA8K_PORT_STATUS_RXFLOW;
1149
1150 if (tx_pause || dsa_is_cpu_port(ds, port))
1151 reg |= QCA8K_PORT_STATUS_TXFLOW;
1152 }
1153
1154 reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
1155
1156 qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
1157 }
1158
1159 static void
1160 qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)
1161 {
1162 int i;
1163
1164 if (stringset != ETH_SS_STATS)
1165 return;
1166
1167 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)
1168 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
1169 ETH_GSTRING_LEN);
1170 }
1171
1172 static void
1173 qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
1174 uint64_t *data)
1175 {
1176 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1177 const struct qca8k_mib_desc *mib;
1178 u32 reg, i, val;
1179 u32 hi = 0;
1180 int ret;
1181
1182 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
1183 mib = &ar8327_mib[i];
1184 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
1185
1186 ret = qca8k_read(priv, reg, &val);
1187 if (ret < 0)
1188 continue;
1189
1190 if (mib->size == 2) {
1191 ret = qca8k_read(priv, reg + 4, &hi);
1192 if (ret < 0)
1193 continue;
1194 }
1195
1196 data[i] = val;
1197 if (mib->size == 2)
1198 data[i] |= (u64)hi << 32;
1199 }
1200 }
1201
1202 static int
1203 qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
1204 {
1205 if (sset != ETH_SS_STATS)
1206 return 0;
1207
1208 return ARRAY_SIZE(ar8327_mib);
1209 }
1210
1211 static int
1212 qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
1213 {
1214 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1215 u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
1216 u32 reg;
1217 int ret;
1218
1219 mutex_lock(&priv->reg_mutex);
1220 ret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, &reg);
1221 if (ret < 0)
1222 goto exit;
1223
1224 if (eee->eee_enabled)
1225 reg |= lpi_en;
1226 else
1227 reg &= ~lpi_en;
1228 ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
1229
1230 exit:
1231 mutex_unlock(&priv->reg_mutex);
1232 return ret;
1233 }
1234
1235 static int
1236 qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1237 {
1238 /* Nothing to do on the port's MAC */
1239 return 0;
1240 }
1241
1242 static void
1243 qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1244 {
1245 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1246 u32 stp_state;
1247
1248 switch (state) {
1249 case BR_STATE_DISABLED:
1250 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
1251 break;
1252 case BR_STATE_BLOCKING:
1253 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
1254 break;
1255 case BR_STATE_LISTENING:
1256 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
1257 break;
1258 case BR_STATE_LEARNING:
1259 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
1260 break;
1261 case BR_STATE_FORWARDING:
1262 default:
1263 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
1264 break;
1265 }
1266
1267 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1268 QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
1269 }
1270
1271 static int
1272 qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
1273 {
1274 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1275 int port_mask, cpu_port;
1276 int i, ret;
1277
1278 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1279 port_mask = BIT(cpu_port);
1280
1281 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1282 if (dsa_is_cpu_port(ds, i))
1283 continue;
1284 if (dsa_to_port(ds, i)->bridge_dev != br)
1285 continue;
1286 /* Add this port to the portvlan mask of the other ports
1287 * in the bridge
1288 */
1289 ret = qca8k_reg_set(priv,
1290 QCA8K_PORT_LOOKUP_CTRL(i),
1291 BIT(port));
1292 if (ret)
1293 return ret;
1294 if (i != port)
1295 port_mask |= BIT(i);
1296 }
1297
1298 /* Add all other ports to this ports portvlan mask */
1299 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1300 QCA8K_PORT_LOOKUP_MEMBER, port_mask);
1301
1302 return ret;
1303 }
1304
1305 static void
1306 qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)
1307 {
1308 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1309 int cpu_port, i;
1310
1311 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1312
1313 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1314 if (dsa_is_cpu_port(ds, i))
1315 continue;
1316 if (dsa_to_port(ds, i)->bridge_dev != br)
1317 continue;
1318 /* Remove this port to the portvlan mask of the other ports
1319 * in the bridge
1320 */
1321 qca8k_reg_clear(priv,
1322 QCA8K_PORT_LOOKUP_CTRL(i),
1323 BIT(port));
1324 }
1325
1326 /* Set the cpu port to be the only one in the portvlan mask of
1327 * this port
1328 */
1329 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1330 QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port));
1331 }
1332
1333 static int
1334 qca8k_port_enable(struct dsa_switch *ds, int port,
1335 struct phy_device *phy)
1336 {
1337 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1338
1339 qca8k_port_set_status(priv, port, 1);
1340 priv->port_sts[port].enabled = 1;
1341
1342 if (dsa_is_user_port(ds, port))
1343 phy_support_asym_pause(phy);
1344
1345 return 0;
1346 }
1347
1348 static void
1349 qca8k_port_disable(struct dsa_switch *ds, int port)
1350 {
1351 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1352
1353 qca8k_port_set_status(priv, port, 0);
1354 priv->port_sts[port].enabled = 0;
1355 }
1356
1357 static int
1358 qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1359 {
1360 struct qca8k_priv *priv = ds->priv;
1361 int i, mtu = 0;
1362
1363 priv->port_mtu[port] = new_mtu;
1364
1365 for (i = 0; i < QCA8K_NUM_PORTS; i++)
1366 if (priv->port_mtu[i] > mtu)
1367 mtu = priv->port_mtu[i];
1368
1369 /* Include L2 header / FCS length */
1370 return qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN);
1371 }
1372
1373 static int
1374 qca8k_port_max_mtu(struct dsa_switch *ds, int port)
1375 {
1376 return QCA8K_MAX_MTU;
1377 }
1378
1379 static int
1380 qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
1381 u16 port_mask, u16 vid)
1382 {
1383 /* Set the vid to the port vlan id if no vid is set */
1384 if (!vid)
1385 vid = QCA8K_PORT_VID_DEF;
1386
1387 return qca8k_fdb_add(priv, addr, port_mask, vid,
1388 QCA8K_ATU_STATUS_STATIC);
1389 }
1390
1391 static int
1392 qca8k_port_fdb_add(struct dsa_switch *ds, int port,
1393 const unsigned char *addr, u16 vid)
1394 {
1395 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1396 u16 port_mask = BIT(port);
1397
1398 return qca8k_port_fdb_insert(priv, addr, port_mask, vid);
1399 }
1400
1401 static int
1402 qca8k_port_fdb_del(struct dsa_switch *ds, int port,
1403 const unsigned char *addr, u16 vid)
1404 {
1405 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1406 u16 port_mask = BIT(port);
1407
1408 if (!vid)
1409 vid = QCA8K_PORT_VID_DEF;
1410
1411 return qca8k_fdb_del(priv, addr, port_mask, vid);
1412 }
1413
1414 static int
1415 qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
1416 dsa_fdb_dump_cb_t *cb, void *data)
1417 {
1418 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1419 struct qca8k_fdb _fdb = { 0 };
1420 int cnt = QCA8K_NUM_FDB_RECORDS;
1421 bool is_static;
1422 int ret = 0;
1423
1424 mutex_lock(&priv->reg_mutex);
1425 while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
1426 if (!_fdb.aging)
1427 break;
1428 is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC);
1429 ret = cb(_fdb.mac, _fdb.vid, is_static, data);
1430 if (ret)
1431 break;
1432 }
1433 mutex_unlock(&priv->reg_mutex);
1434
1435 return 0;
1436 }
1437
1438 static int
1439 qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1440 struct netlink_ext_ack *extack)
1441 {
1442 struct qca8k_priv *priv = ds->priv;
1443
1444 if (vlan_filtering) {
1445 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1446 QCA8K_PORT_LOOKUP_VLAN_MODE,
1447 QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE);
1448 } else {
1449 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1450 QCA8K_PORT_LOOKUP_VLAN_MODE,
1451 QCA8K_PORT_LOOKUP_VLAN_MODE_NONE);
1452 }
1453
1454 return 0;
1455 }
1456
1457 static int
1458 qca8k_port_vlan_add(struct dsa_switch *ds, int port,
1459 const struct switchdev_obj_port_vlan *vlan,
1460 struct netlink_ext_ack *extack)
1461 {
1462 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1463 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1464 struct qca8k_priv *priv = ds->priv;
1465 int ret = 0;
1466
1467 ret = qca8k_vlan_add(priv, port, vlan->vid, untagged);
1468 if (ret) {
1469 dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret);
1470 return ret;
1471 }
1472
1473 if (pvid) {
1474 int shift = 16 * (port % 2);
1475
1476 qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
1477 0xfff << shift, vlan->vid << shift);
1478 qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
1479 QCA8K_PORT_VLAN_CVID(vlan->vid) |
1480 QCA8K_PORT_VLAN_SVID(vlan->vid));
1481 }
1482 return 0;
1483 }
1484
1485 static int
1486 qca8k_port_vlan_del(struct dsa_switch *ds, int port,
1487 const struct switchdev_obj_port_vlan *vlan)
1488 {
1489 struct qca8k_priv *priv = ds->priv;
1490 int ret = 0;
1491
1492 ret = qca8k_vlan_del(priv, port, vlan->vid);
1493 if (ret)
1494 dev_err(priv->dev, "Failed to delete VLAN from port %d (%d)", port, ret);
1495
1496 return ret;
1497 }
1498
1499 static enum dsa_tag_protocol
1500 qca8k_get_tag_protocol(struct dsa_switch *ds, int port,
1501 enum dsa_tag_protocol mp)
1502 {
1503 return DSA_TAG_PROTO_IPQ4019;
1504 }
1505
1506 static const struct dsa_switch_ops qca8k_switch_ops = {
1507 .get_tag_protocol = qca8k_get_tag_protocol,
1508 .setup = qca8k_setup,
1509 .get_strings = qca8k_get_strings,
1510 .get_ethtool_stats = qca8k_get_ethtool_stats,
1511 .get_sset_count = qca8k_get_sset_count,
1512 .get_mac_eee = qca8k_get_mac_eee,
1513 .set_mac_eee = qca8k_set_mac_eee,
1514 .port_enable = qca8k_port_enable,
1515 .port_disable = qca8k_port_disable,
1516 .port_change_mtu = qca8k_port_change_mtu,
1517 .port_max_mtu = qca8k_port_max_mtu,
1518 .port_stp_state_set = qca8k_port_stp_state_set,
1519 .port_bridge_join = qca8k_port_bridge_join,
1520 .port_bridge_leave = qca8k_port_bridge_leave,
1521 .port_fdb_add = qca8k_port_fdb_add,
1522 .port_fdb_del = qca8k_port_fdb_del,
1523 .port_fdb_dump = qca8k_port_fdb_dump,
1524 .port_vlan_filtering = qca8k_port_vlan_filtering,
1525 .port_vlan_add = qca8k_port_vlan_add,
1526 .port_vlan_del = qca8k_port_vlan_del,
1527 .phylink_validate = qca8k_phylink_validate,
1528 .phylink_mac_link_state = qca8k_phylink_mac_link_state,
1529 .phylink_mac_config = qca8k_phylink_mac_config,
1530 .phylink_mac_link_down = qca8k_phylink_mac_link_down,
1531 .phylink_mac_link_up = qca8k_phylink_mac_link_up,
1532 };
1533
1534 static int
1535 qca8k_ipq4019_probe(struct platform_device *pdev)
1536 {
1537 struct qca8k_priv *priv;
1538 void __iomem *base, *psgmii;
1539 struct device_node *np = pdev->dev.of_node, *mdio_np, *psgmii_ethphy_np;
1540 int ret;
1541
1542 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1543 if (!priv)
1544 return -ENOMEM;
1545
1546 priv->dev = &pdev->dev;
1547
1548 base = devm_platform_ioremap_resource_byname(pdev, "base");
1549 if (IS_ERR(base))
1550 return PTR_ERR(base);
1551
1552 priv->regmap = devm_regmap_init_mmio(priv->dev, base,
1553 &qca8k_ipq4019_regmap_config);
1554 if (IS_ERR(priv->regmap)) {
1555 ret = PTR_ERR(priv->regmap);
1556 dev_err(priv->dev, "base regmap initialization failed, %d\n", ret);
1557 return ret;
1558 }
1559
1560 psgmii = devm_platform_ioremap_resource_byname(pdev, "psgmii_phy");
1561 if (IS_ERR(psgmii))
1562 return PTR_ERR(psgmii);
1563
1564 priv->psgmii = devm_regmap_init_mmio(priv->dev, psgmii,
1565 &qca8k_ipq4019_psgmii_phy_regmap_config);
1566 if (IS_ERR(priv->psgmii)) {
1567 ret = PTR_ERR(priv->psgmii);
1568 dev_err(priv->dev, "PSGMII regmap initialization failed, %d\n", ret);
1569 return ret;
1570 }
1571
1572 mdio_np = of_parse_phandle(np, "mdio", 0);
1573 if (!mdio_np) {
1574 dev_err(&pdev->dev, "unable to get MDIO bus phandle\n");
1575 of_node_put(mdio_np);
1576 return -EINVAL;
1577 }
1578
1579 priv->bus = of_mdio_find_bus(mdio_np);
1580 of_node_put(mdio_np);
1581 if (!priv->bus) {
1582 dev_err(&pdev->dev, "unable to find MDIO bus\n");
1583 return -EPROBE_DEFER;
1584 }
1585
1586 psgmii_ethphy_np = of_parse_phandle(np, "psgmii-ethphy", 0);
1587 if (!psgmii_ethphy_np) {
1588 dev_dbg(&pdev->dev, "unable to get PSGMII eth PHY phandle\n");
1589 of_node_put(psgmii_ethphy_np);
1590 }
1591
1592 if (psgmii_ethphy_np) {
1593 priv->psgmii_ethphy = of_phy_find_device(psgmii_ethphy_np);
1594 of_node_put(psgmii_ethphy_np);
1595 if (!priv->psgmii_ethphy) {
1596 dev_err(&pdev->dev, "unable to get PSGMII eth PHY\n");
1597 return -ENODEV;
1598 }
1599 }
1600
1601 priv->ds = devm_kzalloc(priv->dev, sizeof(*priv->ds), GFP_KERNEL);
1602 if (!priv->ds)
1603 return -ENOMEM;
1604
1605 priv->ds->dev = priv->dev;
1606 priv->ds->num_ports = QCA8K_NUM_PORTS;
1607 priv->ds->priv = priv;
1608 priv->ops = qca8k_switch_ops;
1609 priv->ds->ops = &priv->ops;
1610
1611 mutex_init(&priv->reg_mutex);
1612 platform_set_drvdata(pdev, priv);
1613
1614 return dsa_register_switch(priv->ds);
1615 }
1616
1617 static int
1618 qca8k_ipq4019_remove(struct platform_device *pdev)
1619 {
1620 struct qca8k_priv *priv = dev_get_drvdata(&pdev->dev);
1621 int i;
1622
1623 if (!priv)
1624 return 0;
1625
1626 for (i = 0; i < QCA8K_NUM_PORTS; i++)
1627 qca8k_port_set_status(priv, i, 0);
1628
1629 dsa_unregister_switch(priv->ds);
1630
1631 dev_set_drvdata(&pdev->dev, NULL);
1632
1633 return 0;
1634 }
1635
1636 static const struct of_device_id qca8k_ipq4019_of_match[] = {
1637 { .compatible = "qca,ipq4019-qca8337n" },
1638 { /* sentinel */ },
1639 };
1640
1641 static struct platform_driver qca8k_ipq4019_driver = {
1642 .probe = qca8k_ipq4019_probe,
1643 .remove = qca8k_ipq4019_remove,
1644 .driver = {
1645 .name = "qca8k-ipq4019",
1646 .of_match_table = qca8k_ipq4019_of_match,
1647 },
1648 };
1649
1650 module_platform_driver(qca8k_ipq4019_driver);
1651
1652 MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
1653 MODULE_AUTHOR("Gabor Juhos <j4g8y7@gmail.com>, Robert Marko <robert.marko@sartura.hr>");
1654 MODULE_DESCRIPTION("Qualcomm IPQ4019 built-in switch driver");
1655 MODULE_LICENSE("GPL v2");
Staging tree of Jo-Philipp Wich