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[openwrt/staging/jow.git] / target / linux / ipq40xx / files / drivers / net / dsa / qca / qca8k-ipq4019.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2011-2012, 2020-2021 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2016 John Crispin <john@phrozen.org>
7 * Copyright (c) 2021 Robert Marko <robert.marko@sartura.hr>
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/version.h>
12 #include <linux/etherdevice.h>
13 #include <linux/if_bridge.h>
14 #include <linux/mdio.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/of_mdio.h>
19 #include <linux/of_net.h>
20 #include <linux/of_platform.h>
21 #include <linux/phy.h>
22 #include <linux/phylink.h>
23 #include <linux/reset.h>
24 #include <net/dsa.h>
25
26 #include "qca8k-ipq4019.h"
27
28 #define MIB_DESC(_s, _o, _n) \
29 { \
30 .size = (_s), \
31 .offset = (_o), \
32 .name = (_n), \
33 }
34
35 static const struct qca8k_mib_desc ar8327_mib[] = {
36 MIB_DESC(1, 0x00, "RxBroad"),
37 MIB_DESC(1, 0x04, "RxPause"),
38 MIB_DESC(1, 0x08, "RxMulti"),
39 MIB_DESC(1, 0x0c, "RxFcsErr"),
40 MIB_DESC(1, 0x10, "RxAlignErr"),
41 MIB_DESC(1, 0x14, "RxRunt"),
42 MIB_DESC(1, 0x18, "RxFragment"),
43 MIB_DESC(1, 0x1c, "Rx64Byte"),
44 MIB_DESC(1, 0x20, "Rx128Byte"),
45 MIB_DESC(1, 0x24, "Rx256Byte"),
46 MIB_DESC(1, 0x28, "Rx512Byte"),
47 MIB_DESC(1, 0x2c, "Rx1024Byte"),
48 MIB_DESC(1, 0x30, "Rx1518Byte"),
49 MIB_DESC(1, 0x34, "RxMaxByte"),
50 MIB_DESC(1, 0x38, "RxTooLong"),
51 MIB_DESC(2, 0x3c, "RxGoodByte"),
52 MIB_DESC(2, 0x44, "RxBadByte"),
53 MIB_DESC(1, 0x4c, "RxOverFlow"),
54 MIB_DESC(1, 0x50, "Filtered"),
55 MIB_DESC(1, 0x54, "TxBroad"),
56 MIB_DESC(1, 0x58, "TxPause"),
57 MIB_DESC(1, 0x5c, "TxMulti"),
58 MIB_DESC(1, 0x60, "TxUnderRun"),
59 MIB_DESC(1, 0x64, "Tx64Byte"),
60 MIB_DESC(1, 0x68, "Tx128Byte"),
61 MIB_DESC(1, 0x6c, "Tx256Byte"),
62 MIB_DESC(1, 0x70, "Tx512Byte"),
63 MIB_DESC(1, 0x74, "Tx1024Byte"),
64 MIB_DESC(1, 0x78, "Tx1518Byte"),
65 MIB_DESC(1, 0x7c, "TxMaxByte"),
66 MIB_DESC(1, 0x80, "TxOverSize"),
67 MIB_DESC(2, 0x84, "TxByte"),
68 MIB_DESC(1, 0x8c, "TxCollision"),
69 MIB_DESC(1, 0x90, "TxAbortCol"),
70 MIB_DESC(1, 0x94, "TxMultiCol"),
71 MIB_DESC(1, 0x98, "TxSingleCol"),
72 MIB_DESC(1, 0x9c, "TxExcDefer"),
73 MIB_DESC(1, 0xa0, "TxDefer"),
74 MIB_DESC(1, 0xa4, "TxLateCol"),
75 MIB_DESC(1, 0xa8, "RXUnicast"),
76 MIB_DESC(1, 0xac, "TXunicast"),
77 };
78
79 static int
80 qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
81 {
82 return regmap_read(priv->regmap, reg, val);
83 }
84
85 static int
86 qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
87 {
88 return regmap_write(priv->regmap, reg, val);
89 }
90
91 static int
92 qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
93 {
94 return regmap_update_bits(priv->regmap, reg, mask, write_val);
95 }
96
97 static int
98 qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)
99 {
100 return regmap_set_bits(priv->regmap, reg, val);
101 }
102
103 static int
104 qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)
105 {
106 return regmap_clear_bits(priv->regmap, reg, val);
107 }
108
109 static const struct regmap_range qca8k_readable_ranges[] = {
110 regmap_reg_range(0x0000, 0x00e4), /* Global control */
111 regmap_reg_range(0x0100, 0x0168), /* EEE control */
112 regmap_reg_range(0x0200, 0x0270), /* Parser control */
113 regmap_reg_range(0x0400, 0x0454), /* ACL */
114 regmap_reg_range(0x0600, 0x0718), /* Lookup */
115 regmap_reg_range(0x0800, 0x0b70), /* QM */
116 regmap_reg_range(0x0c00, 0x0c80), /* PKT */
117 regmap_reg_range(0x0e00, 0x0e98), /* L3 */
118 regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
119 regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
120 regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
121 regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
122 regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
123 regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
124 regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
125
126 };
127
128 static const struct regmap_access_table qca8k_readable_table = {
129 .yes_ranges = qca8k_readable_ranges,
130 .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
131 };
132
133 static struct regmap_config qca8k_ipq4019_regmap_config = {
134 .reg_bits = 32,
135 .val_bits = 32,
136 .reg_stride = 4,
137 .max_register = 0x16ac, /* end MIB - Port6 range */
138 .rd_table = &qca8k_readable_table,
139 };
140
141 static struct regmap_config qca8k_ipq4019_psgmii_phy_regmap_config = {
142 .name = "psgmii-phy",
143 .reg_bits = 32,
144 .val_bits = 32,
145 .reg_stride = 4,
146 .max_register = 0x7fc,
147 };
148
149 static int
150 qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
151 {
152 u32 val;
153
154 return regmap_read_poll_timeout(priv->regmap, reg, val,
155 !(val & mask),
156 0,
157 QCA8K_BUSY_WAIT_TIMEOUT);
158 }
159
160 static int
161 qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
162 {
163 u32 reg[4], val;
164 int i, ret;
165
166 /* load the ARL table into an array */
167 for (i = 0; i < 4; i++) {
168 ret = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4), &val);
169 if (ret < 0)
170 return ret;
171
172 reg[i] = val;
173 }
174
175 /* vid - 83:72 */
176 fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
177 /* aging - 67:64 */
178 fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
179 /* portmask - 54:48 */
180 fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
181 /* mac - 47:0 */
182 fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
183 fdb->mac[1] = reg[1] & 0xff;
184 fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
185 fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
186 fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
187 fdb->mac[5] = reg[0] & 0xff;
188
189 return 0;
190 }
191
192 static void
193 qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
194 u8 aging)
195 {
196 u32 reg[3] = { 0 };
197 int i;
198
199 /* vid - 83:72 */
200 reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
201 /* aging - 67:64 */
202 reg[2] |= aging & QCA8K_ATU_STATUS_M;
203 /* portmask - 54:48 */
204 reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
205 /* mac - 47:0 */
206 reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
207 reg[1] |= mac[1];
208 reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
209 reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
210 reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
211 reg[0] |= mac[5];
212
213 /* load the array into the ARL table */
214 for (i = 0; i < 3; i++)
215 qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]);
216 }
217
218 static int
219 qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
220 {
221 u32 reg;
222 int ret;
223
224 /* Set the command and FDB index */
225 reg = QCA8K_ATU_FUNC_BUSY;
226 reg |= cmd;
227 if (port >= 0) {
228 reg |= QCA8K_ATU_FUNC_PORT_EN;
229 reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
230 }
231
232 /* Write the function register triggering the table access */
233 ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
234 if (ret)
235 return ret;
236
237 /* wait for completion */
238 ret = qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY);
239 if (ret)
240 return ret;
241
242 /* Check for table full violation when adding an entry */
243 if (cmd == QCA8K_FDB_LOAD) {
244 ret = qca8k_read(priv, QCA8K_REG_ATU_FUNC, &reg);
245 if (ret < 0)
246 return ret;
247 if (reg & QCA8K_ATU_FUNC_FULL)
248 return -1;
249 }
250
251 return 0;
252 }
253
254 static int
255 qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port)
256 {
257 int ret;
258
259 qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
260 ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
261 if (ret < 0)
262 return ret;
263
264 return qca8k_fdb_read(priv, fdb);
265 }
266
267 static int
268 qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask,
269 u16 vid, u8 aging)
270 {
271 int ret;
272
273 mutex_lock(&priv->reg_mutex);
274 qca8k_fdb_write(priv, vid, port_mask, mac, aging);
275 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
276 mutex_unlock(&priv->reg_mutex);
277
278 return ret;
279 }
280
281 static int
282 qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid)
283 {
284 int ret;
285
286 mutex_lock(&priv->reg_mutex);
287 qca8k_fdb_write(priv, vid, port_mask, mac, 0);
288 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
289 mutex_unlock(&priv->reg_mutex);
290
291 return ret;
292 }
293
294 static void
295 qca8k_fdb_flush(struct qca8k_priv *priv)
296 {
297 mutex_lock(&priv->reg_mutex);
298 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
299 mutex_unlock(&priv->reg_mutex);
300 }
301
302 static int
303 qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid)
304 {
305 u32 reg;
306 int ret;
307
308 /* Set the command and VLAN index */
309 reg = QCA8K_VTU_FUNC1_BUSY;
310 reg |= cmd;
311 reg |= vid << QCA8K_VTU_FUNC1_VID_S;
312
313 /* Write the function register triggering the table access */
314 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
315 if (ret)
316 return ret;
317
318 /* wait for completion */
319 ret = qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY);
320 if (ret)
321 return ret;
322
323 /* Check for table full violation when adding an entry */
324 if (cmd == QCA8K_VLAN_LOAD) {
325 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC1, &reg);
326 if (ret < 0)
327 return ret;
328 if (reg & QCA8K_VTU_FUNC1_FULL)
329 return -ENOMEM;
330 }
331
332 return 0;
333 }
334
335 static int
336 qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged)
337 {
338 u32 reg;
339 int ret;
340
341 /*
342 We do the right thing with VLAN 0 and treat it as untagged while
343 preserving the tag on egress.
344 */
345 if (vid == 0)
346 return 0;
347
348 mutex_lock(&priv->reg_mutex);
349 ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
350 if (ret < 0)
351 goto out;
352
353 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
354 if (ret < 0)
355 goto out;
356 reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;
357 reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port));
358 if (untagged)
359 reg |= QCA8K_VTU_FUNC0_EG_MODE_UNTAG <<
360 QCA8K_VTU_FUNC0_EG_MODE_S(port);
361 else
362 reg |= QCA8K_VTU_FUNC0_EG_MODE_TAG <<
363 QCA8K_VTU_FUNC0_EG_MODE_S(port);
364
365 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
366 if (ret)
367 goto out;
368 ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
369
370 out:
371 mutex_unlock(&priv->reg_mutex);
372
373 return ret;
374 }
375
376 static int
377 qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid)
378 {
379 u32 reg, mask;
380 int ret, i;
381 bool del;
382
383 mutex_lock(&priv->reg_mutex);
384 ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
385 if (ret < 0)
386 goto out;
387
388 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
389 if (ret < 0)
390 goto out;
391 reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port));
392 reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT <<
393 QCA8K_VTU_FUNC0_EG_MODE_S(port);
394
395 /* Check if we're the last member to be removed */
396 del = true;
397 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
398 mask = QCA8K_VTU_FUNC0_EG_MODE_NOT;
399 mask <<= QCA8K_VTU_FUNC0_EG_MODE_S(i);
400
401 if ((reg & mask) != mask) {
402 del = false;
403 break;
404 }
405 }
406
407 if (del) {
408 ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid);
409 } else {
410 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
411 if (ret)
412 goto out;
413 ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
414 }
415
416 out:
417 mutex_unlock(&priv->reg_mutex);
418
419 return ret;
420 }
421
422 static int
423 qca8k_mib_init(struct qca8k_priv *priv)
424 {
425 int ret;
426
427 mutex_lock(&priv->reg_mutex);
428 ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
429 if (ret)
430 goto exit;
431
432 ret = qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
433 if (ret)
434 goto exit;
435
436 ret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
437 if (ret)
438 goto exit;
439
440 ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
441
442 exit:
443 mutex_unlock(&priv->reg_mutex);
444 return ret;
445 }
446
447 static void
448 qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
449 {
450 u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
451
452 /* Port 0 is internally connected to the CPU
453 * TODO: Probably check for RGMII as well if it doesnt work
454 * in RGMII mode.
455 */
456 if (port > QCA8K_CPU_PORT)
457 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
458
459 if (enable)
460 qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask);
461 else
462 qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);
463 }
464
465 static int
466 qca8k_setup_port(struct dsa_switch *ds, int port)
467 {
468 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
469 int ret;
470
471 /* CPU port gets connected to all user ports of the switch */
472 if (dsa_is_cpu_port(ds, port)) {
473 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
474 QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
475 if (ret)
476 return ret;
477
478 /* Disable CPU ARP Auto-learning by default */
479 ret = qca8k_reg_clear(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
480 QCA8K_PORT_LOOKUP_LEARN);
481 if (ret)
482 return ret;
483 }
484
485 /* Individual user ports get connected to CPU port only */
486 if (dsa_is_user_port(ds, port)) {
487 int shift = 16 * (port % 2);
488
489 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
490 QCA8K_PORT_LOOKUP_MEMBER,
491 BIT(QCA8K_CPU_PORT));
492 if (ret)
493 return ret;
494
495 /* Enable ARP Auto-learning by default */
496 ret = qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(port),
497 QCA8K_PORT_LOOKUP_LEARN);
498 if (ret)
499 return ret;
500
501 /* For port based vlans to work we need to set the
502 * default egress vid
503 */
504 ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
505 0xfff << shift,
506 QCA8K_PORT_VID_DEF << shift);
507 if (ret)
508 return ret;
509
510 ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
511 QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
512 QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
513 if (ret)
514 return ret;
515 }
516
517 return 0;
518 }
519
520 static int
521 qca8k_setup(struct dsa_switch *ds)
522 {
523 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
524 int ret, i;
525
526 /* Make sure that port 0 is the cpu port */
527 if (!dsa_is_cpu_port(ds, 0)) {
528 dev_err(priv->dev, "port 0 is not the CPU port");
529 return -EINVAL;
530 }
531
532 /* Enable CPU Port */
533 ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
534 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
535 if (ret) {
536 dev_err(priv->dev, "failed enabling CPU port");
537 return ret;
538 }
539
540 /* Enable MIB counters */
541 ret = qca8k_mib_init(priv);
542 if (ret)
543 dev_warn(priv->dev, "MIB init failed");
544
545 /* Enable QCA header mode on the cpu port */
546 ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
547 QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
548 QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
549 if (ret) {
550 dev_err(priv->dev, "failed enabling QCA header mode");
551 return ret;
552 }
553
554 /* Disable forwarding by default on all ports */
555 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
556 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
557 QCA8K_PORT_LOOKUP_MEMBER, 0);
558 if (ret)
559 return ret;
560 }
561
562 /* Disable MAC by default on all ports */
563 for (i = 1; i < QCA8K_NUM_PORTS; i++)
564 qca8k_port_set_status(priv, i, 0);
565
566 /* Forward all unknown frames to CPU port for Linux processing */
567 ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
568 BIT(QCA8K_CPU_PORT) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
569 BIT(QCA8K_CPU_PORT) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
570 BIT(QCA8K_CPU_PORT) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
571 BIT(QCA8K_CPU_PORT) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
572 if (ret)
573 return ret;
574
575 /* Setup connection between CPU port & user ports */
576 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
577 ret = qca8k_setup_port(ds, i);
578 if (ret)
579 return ret;
580 }
581
582 /* Setup our port MTUs to match power on defaults */
583 for (i = 0; i < QCA8K_NUM_PORTS; i++)
584 /* Set per port MTU to 1500 as the MTU change function
585 * will add the overhead and if its set to 1518 then it
586 * will apply the overhead again and we will end up with
587 * MTU of 1536 instead of 1518
588 */
589 priv->port_mtu[i] = ETH_DATA_LEN;
590 ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
591 if (ret)
592 dev_warn(priv->dev, "failed setting MTU settings");
593
594 /* Flush the FDB table */
595 qca8k_fdb_flush(priv);
596
597 /* We don't have interrupts for link changes, so we need to poll */
598 ds->pcs_poll = true;
599
600 /* CPU port HW learning doesnt work correctly, so let DSA handle it */
601 ds->assisted_learning_on_cpu_port = true;
602
603 return 0;
604 }
605
606 static int psgmii_vco_calibrate(struct qca8k_priv *priv)
607 {
608 int val, ret;
609
610 if (!priv->psgmii_ethphy) {
611 dev_err(priv->dev, "PSGMII eth PHY missing, calibration failed!\n");
612 return -ENODEV;
613 }
614
615 /* Fix PSGMII RX 20bit */
616 ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5b);
617 /* Reset PHY PSGMII */
618 ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x1b);
619 /* Release PHY PSGMII reset */
620 ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5b);
621
622 /* Poll for VCO PLL calibration finish - Malibu(QCA8075) */
623 ret = phy_read_mmd_poll_timeout(priv->psgmii_ethphy,
624 MDIO_MMD_PMAPMD,
625 0x28, val,
626 (val & BIT(0)),
627 10000, 1000000,
628 false);
629 if (ret) {
630 dev_err(priv->dev, "QCA807x PSGMII VCO calibration PLL not ready\n");
631 return ret;
632 }
633 mdelay(50);
634
635 /* Freeze PSGMII RX CDR */
636 ret = phy_write(priv->psgmii_ethphy, MII_RESV2, 0x2230);
637
638 /* Start PSGMIIPHY VCO PLL calibration */
639 ret = regmap_set_bits(priv->psgmii,
640 PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_1,
641 PSGMIIPHY_REG_PLL_VCO_CALIB_RESTART);
642
643 /* Poll for PSGMIIPHY PLL calibration finish - Dakota(IPQ40xx) */
644 ret = regmap_read_poll_timeout(priv->psgmii,
645 PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_2,
646 val, val & PSGMIIPHY_REG_PLL_VCO_CALIB_READY,
647 10000, 1000000);
648 if (ret) {
649 dev_err(priv->dev, "IPQ PSGMIIPHY VCO calibration PLL not ready\n");
650 return ret;
651 }
652 mdelay(50);
653
654 /* Release PSGMII RX CDR */
655 ret = phy_write(priv->psgmii_ethphy, MII_RESV2, 0x3230);
656 /* Release PSGMII RX 20bit */
657 ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5f);
658 mdelay(200);
659
660 return ret;
661 }
662
663 static void
664 qca8k_switch_port_loopback_on_off(struct qca8k_priv *priv, int port, int on)
665 {
666 u32 val = QCA8K_PORT_LOOKUP_LOOPBACK;
667
668 if (on == 0)
669 val = 0;
670
671 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
672 QCA8K_PORT_LOOKUP_LOOPBACK, val);
673 }
674
675 static int
676 qca8k_wait_for_phy_link_state(struct phy_device *phy, int need_status)
677 {
678 int a;
679 u16 status;
680
681 for (a = 0; a < 100; a++) {
682 status = phy_read(phy, MII_QCA8075_SSTATUS);
683 status &= QCA8075_PHY_SPEC_STATUS_LINK;
684 status = !!status;
685 if (status == need_status)
686 return 0;
687 mdelay(8);
688 }
689
690 return -1;
691 }
692
693 static void
694 qca8k_phy_loopback_on_off(struct qca8k_priv *priv, struct phy_device *phy,
695 int sw_port, int on)
696 {
697 if (on) {
698 phy_write(phy, MII_BMCR, BMCR_ANENABLE | BMCR_RESET);
699 phy_modify(phy, MII_BMCR, BMCR_PDOWN, BMCR_PDOWN);
700 qca8k_wait_for_phy_link_state(phy, 0);
701 qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port), 0);
702 phy_write(phy, MII_BMCR,
703 BMCR_SPEED1000 |
704 BMCR_FULLDPLX |
705 BMCR_LOOPBACK);
706 qca8k_wait_for_phy_link_state(phy, 1);
707 qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port),
708 QCA8K_PORT_STATUS_SPEED_1000 |
709 QCA8K_PORT_STATUS_TXMAC |
710 QCA8K_PORT_STATUS_RXMAC |
711 QCA8K_PORT_STATUS_DUPLEX);
712 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(sw_port),
713 QCA8K_PORT_LOOKUP_STATE_FORWARD,
714 QCA8K_PORT_LOOKUP_STATE_FORWARD);
715 } else { /* off */
716 qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port), 0);
717 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(sw_port),
718 QCA8K_PORT_LOOKUP_STATE_DISABLED,
719 QCA8K_PORT_LOOKUP_STATE_DISABLED);
720 phy_write(phy, MII_BMCR, BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_RESET);
721 /* turn off the power of the phys - so that unused
722 ports do not raise links */
723 phy_modify(phy, MII_BMCR, BMCR_PDOWN, BMCR_PDOWN);
724 }
725 }
726
727 static void
728 qca8k_phy_pkt_gen_prep(struct qca8k_priv *priv, struct phy_device *phy,
729 int pkts_num, int on)
730 {
731 if (on) {
732 /* enable CRC checker and packets counters */
733 phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT, 0);
734 phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT,
735 QCA8075_MMD7_CNT_FRAME_CHK_EN | QCA8075_MMD7_CNT_SELFCLR);
736 qca8k_wait_for_phy_link_state(phy, 1);
737 /* packet number */
738 phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_NUMB, pkts_num);
739 /* pkt size - 1504 bytes + 20 bytes */
740 phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_SIZE, 1504);
741 } else { /* off */
742 /* packet number */
743 phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_NUMB, 0);
744 /* disable CRC checker and packet counter */
745 phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT, 0);
746 /* disable traffic gen */
747 phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL, 0);
748 }
749 }
750
751 static void
752 qca8k_wait_for_phy_pkt_gen_fin(struct qca8k_priv *priv, struct phy_device *phy)
753 {
754 int val;
755 /* wait for all traffic end: 4096(pkt num)*1524(size)*8ns(125MHz)=49938us */
756 phy_read_mmd_poll_timeout(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL,
757 val, !(val & QCA8075_MMD7_PKT_GEN_INPROGR),
758 50000, 1000000, true);
759 }
760
761 static void
762 qca8k_start_phy_pkt_gen(struct phy_device *phy)
763 {
764 /* start traffic gen */
765 phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL,
766 QCA8075_MMD7_PKT_GEN_START | QCA8075_MMD7_PKT_GEN_INPROGR);
767 }
768
769 static int
770 qca8k_start_all_phys_pkt_gens(struct qca8k_priv *priv)
771 {
772 struct phy_device *phy;
773 phy = phy_device_create(priv->bus, QCA8075_MDIO_BRDCST_PHY_ADDR,
774 0, 0, NULL);
775 if (!phy) {
776 dev_err(priv->dev, "unable to create mdio broadcast PHY(0x%x)\n",
777 QCA8075_MDIO_BRDCST_PHY_ADDR);
778 return -ENODEV;
779 }
780
781 qca8k_start_phy_pkt_gen(phy);
782
783 phy_device_free(phy);
784 return 0;
785 }
786
787 static int
788 qca8k_get_phy_pkt_gen_test_result(struct phy_device *phy, int pkts_num)
789 {
790 u32 tx_ok, tx_error;
791 u32 rx_ok, rx_error;
792 u32 tx_ok_high16;
793 u32 rx_ok_high16;
794 u32 tx_all_ok, rx_all_ok;
795
796 /* check counters */
797 tx_ok = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_RECV_CNT_LO);
798 tx_ok_high16 = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_RECV_CNT_HI);
799 tx_error = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_ERR_CNT);
800 rx_ok = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_RECV_CNT_LO);
801 rx_ok_high16 = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_RECV_CNT_HI);
802 rx_error = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_ERR_CNT);
803 tx_all_ok = tx_ok + (tx_ok_high16 << 16);
804 rx_all_ok = rx_ok + (rx_ok_high16 << 16);
805
806 if (tx_all_ok < pkts_num)
807 return -1;
808 if(rx_all_ok < pkts_num)
809 return -2;
810 if(tx_error)
811 return -3;
812 if(rx_error)
813 return -4;
814 return 0; /* test is ok */
815 }
816
817 static
818 void qca8k_phy_broadcast_write_on_off(struct qca8k_priv *priv,
819 struct phy_device *phy, int on)
820 {
821 u32 val;
822
823 val = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_MDIO_BRDCST_WRITE);
824
825 if (on == 0)
826 val &= ~QCA8075_MMD7_MDIO_BRDCST_WRITE_EN;
827 else
828 val |= QCA8075_MMD7_MDIO_BRDCST_WRITE_EN;
829
830 phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_MDIO_BRDCST_WRITE, val);
831 }
832
833 static int
834 qca8k_test_dsa_port_for_errors(struct qca8k_priv *priv, struct phy_device *phy,
835 int port, int test_phase)
836 {
837 int res = 0;
838 const int test_pkts_num = QCA8075_PKT_GEN_PKTS_COUNT;
839
840 if (test_phase == 1) { /* start test preps */
841 qca8k_phy_loopback_on_off(priv, phy, port, 1);
842 qca8k_switch_port_loopback_on_off(priv, port, 1);
843 qca8k_phy_broadcast_write_on_off(priv, phy, 1);
844 qca8k_phy_pkt_gen_prep(priv, phy, test_pkts_num, 1);
845 } else if (test_phase == 2) {
846 /* wait for test results, collect it and cleanup */
847 qca8k_wait_for_phy_pkt_gen_fin(priv, phy);
848 res = qca8k_get_phy_pkt_gen_test_result(phy, test_pkts_num);
849 qca8k_phy_pkt_gen_prep(priv, phy, test_pkts_num, 0);
850 qca8k_phy_broadcast_write_on_off(priv, phy, 0);
851 qca8k_switch_port_loopback_on_off(priv, port, 0);
852 qca8k_phy_loopback_on_off(priv, phy, port, 0);
853 }
854
855 return res;
856 }
857
858 static int
859 qca8k_do_dsa_sw_ports_self_test(struct qca8k_priv *priv, int parallel_test)
860 {
861 struct device_node *dn = priv->dev->of_node;
862 struct device_node *ports, *port;
863 struct device_node *phy_dn;
864 struct phy_device *phy;
865 int reg, err = 0, test_phase;
866 u32 tests_result = 0;
867
868 ports = of_get_child_by_name(dn, "ports");
869 if (!ports) {
870 dev_err(priv->dev, "no ports child node found\n");
871 return -EINVAL;
872 }
873
874 for (test_phase = 1; test_phase <= 2; test_phase++) {
875 if (parallel_test && test_phase == 2) {
876 err = qca8k_start_all_phys_pkt_gens(priv);
877 if (err)
878 goto error;
879 }
880 for_each_available_child_of_node(ports, port) {
881 err = of_property_read_u32(port, "reg", &reg);
882 if (err)
883 goto error;
884 if (reg >= QCA8K_NUM_PORTS) {
885 err = -EINVAL;
886 goto error;
887 }
888 phy_dn = of_parse_phandle(port, "phy-handle", 0);
889 if (phy_dn) {
890 phy = of_phy_find_device(phy_dn);
891 of_node_put(phy_dn);
892 if (phy) {
893 int result;
894 result = qca8k_test_dsa_port_for_errors(priv,
895 phy, reg, test_phase);
896 if (!parallel_test && test_phase == 1)
897 qca8k_start_phy_pkt_gen(phy);
898 put_device(&phy->mdio.dev);
899 if (test_phase == 2) {
900 tests_result <<= 1;
901 if (result)
902 tests_result |= 1;
903 }
904 }
905 }
906 }
907 }
908
909 end:
910 of_node_put(ports);
911 qca8k_fdb_flush(priv);
912 return tests_result;
913 error:
914 tests_result |= 0xf000;
915 goto end;
916 }
917
918 static int
919 psgmii_vco_calibrate_and_test(struct dsa_switch *ds)
920 {
921 int ret, a, test_result;
922 struct qca8k_priv *priv = ds->priv;
923
924 for (a = 0; a <= QCA8K_PSGMII_CALB_NUM; a++) {
925 ret = psgmii_vco_calibrate(priv);
926 if (ret)
927 return ret;
928 /* first we run serial test */
929 test_result = qca8k_do_dsa_sw_ports_self_test(priv, 0);
930 /* and if it is ok then we run the test in parallel */
931 if (!test_result)
932 test_result = qca8k_do_dsa_sw_ports_self_test(priv, 1);
933 if (!test_result) {
934 if (a > 0) {
935 dev_warn(priv->dev, "PSGMII work was stabilized after %d "
936 "calibration retries !\n", a);
937 }
938 return 0;
939 } else {
940 schedule();
941 if (a > 0 && a % 10 == 0) {
942 dev_err(priv->dev, "PSGMII work is unstable !!! "
943 "Let's try to wait a bit ... %d\n", a);
944 set_current_state(TASK_INTERRUPTIBLE);
945 schedule_timeout(msecs_to_jiffies(a * 100));
946 }
947 }
948 }
949
950 panic("PSGMII work is unstable !!! "
951 "Repeated recalibration attempts did not help(0x%x) !\n",
952 test_result);
953
954 return -EFAULT;
955 }
956
957 static int
958 ipq4019_psgmii_configure(struct dsa_switch *ds)
959 {
960 struct qca8k_priv *priv = ds->priv;
961 int ret;
962
963 if (!priv->psgmii_calibrated) {
964 ret = psgmii_vco_calibrate_and_test(ds);
965
966 ret = regmap_clear_bits(priv->psgmii, PSGMIIPHY_MODE_CONTROL,
967 PSGMIIPHY_MODE_ATHR_CSCO_MODE_25M);
968 ret = regmap_write(priv->psgmii, PSGMIIPHY_TX_CONTROL,
969 PSGMIIPHY_TX_CONTROL_MAGIC_VALUE);
970
971 priv->psgmii_calibrated = true;
972
973 return ret;
974 }
975
976 return 0;
977 }
978
979 static void
980 qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
981 const struct phylink_link_state *state)
982 {
983 struct qca8k_priv *priv = ds->priv;
984
985 switch (port) {
986 case 0:
987 /* CPU port, no configuration needed */
988 return;
989 case 1:
990 case 2:
991 case 3:
992 if (state->interface == PHY_INTERFACE_MODE_PSGMII)
993 if (ipq4019_psgmii_configure(ds))
994 dev_err(ds->dev, "PSGMII configuration failed!\n");
995 return;
996 case 4:
997 case 5:
998 if (state->interface == PHY_INTERFACE_MODE_RGMII ||
999 state->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1000 state->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1001 state->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
1002 qca8k_reg_set(priv, QCA8K_REG_RGMII_CTRL, QCA8K_RGMII_CTRL_CLK);
1003 }
1004
1005 if (state->interface == PHY_INTERFACE_MODE_PSGMII)
1006 if (ipq4019_psgmii_configure(ds))
1007 dev_err(ds->dev, "PSGMII configuration failed!\n");
1008 return;
1009 default:
1010 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1011 return;
1012 }
1013 }
1014
1015 static void
1016 qca8k_phylink_validate(struct dsa_switch *ds, int port,
1017 unsigned long *supported,
1018 struct phylink_link_state *state)
1019 {
1020 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1021
1022 switch (port) {
1023 case 0: /* CPU port */
1024 if (state->interface != PHY_INTERFACE_MODE_INTERNAL)
1025 goto unsupported;
1026 break;
1027 case 1:
1028 case 2:
1029 case 3:
1030 /* Only PSGMII mode is supported */
1031 if (state->interface != PHY_INTERFACE_MODE_PSGMII)
1032 goto unsupported;
1033 break;
1034 case 4:
1035 case 5:
1036 /* PSGMII and RGMII modes are supported */
1037 if (state->interface != PHY_INTERFACE_MODE_PSGMII &&
1038 state->interface != PHY_INTERFACE_MODE_RGMII &&
1039 state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1040 state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1041 state->interface != PHY_INTERFACE_MODE_RGMII_TXID)
1042 goto unsupported;
1043 break;
1044 default:
1045 unsupported:
1046 dev_warn(ds->dev, "interface '%s' (%d) on port %d is not supported\n",
1047 phy_modes(state->interface), state->interface, port);
1048 linkmode_zero(supported);
1049 return;
1050 }
1051
1052 if (port == 0) {
1053 phylink_set_port_modes(mask);
1054
1055 phylink_set(mask, 1000baseT_Full);
1056
1057 phylink_set(mask, Pause);
1058 phylink_set(mask, Asym_Pause);
1059
1060 linkmode_and(supported, supported, mask);
1061 linkmode_and(state->advertising, state->advertising, mask);
1062 } else {
1063 /* Simply copy what PHYs tell us */
1064 linkmode_copy(state->advertising, supported);
1065 }
1066 }
1067
1068 static int
1069 qca8k_phylink_mac_link_state(struct dsa_switch *ds, int port,
1070 struct phylink_link_state *state)
1071 {
1072 struct qca8k_priv *priv = ds->priv;
1073 u32 reg;
1074 int ret;
1075
1076 ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), &reg);
1077 if (ret < 0)
1078 return ret;
1079
1080 state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
1081 state->an_complete = state->link;
1082 state->an_enabled = !!(reg & QCA8K_PORT_STATUS_LINK_AUTO);
1083 state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL :
1084 DUPLEX_HALF;
1085
1086 switch (reg & QCA8K_PORT_STATUS_SPEED) {
1087 case QCA8K_PORT_STATUS_SPEED_10:
1088 state->speed = SPEED_10;
1089 break;
1090 case QCA8K_PORT_STATUS_SPEED_100:
1091 state->speed = SPEED_100;
1092 break;
1093 case QCA8K_PORT_STATUS_SPEED_1000:
1094 state->speed = SPEED_1000;
1095 break;
1096 default:
1097 state->speed = SPEED_UNKNOWN;
1098 break;
1099 }
1100
1101 state->pause = MLO_PAUSE_NONE;
1102 if (reg & QCA8K_PORT_STATUS_RXFLOW)
1103 state->pause |= MLO_PAUSE_RX;
1104 if (reg & QCA8K_PORT_STATUS_TXFLOW)
1105 state->pause |= MLO_PAUSE_TX;
1106
1107 return 1;
1108 }
1109
1110 static void
1111 qca8k_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
1112 phy_interface_t interface)
1113 {
1114 struct qca8k_priv *priv = ds->priv;
1115
1116 qca8k_port_set_status(priv, port, 0);
1117 }
1118
1119 static void
1120 qca8k_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
1121 phy_interface_t interface, struct phy_device *phydev,
1122 int speed, int duplex, bool tx_pause, bool rx_pause)
1123 {
1124 struct qca8k_priv *priv = ds->priv;
1125 u32 reg;
1126
1127 if (phylink_autoneg_inband(mode)) {
1128 reg = QCA8K_PORT_STATUS_LINK_AUTO;
1129 } else {
1130 switch (speed) {
1131 case SPEED_10:
1132 reg = QCA8K_PORT_STATUS_SPEED_10;
1133 break;
1134 case SPEED_100:
1135 reg = QCA8K_PORT_STATUS_SPEED_100;
1136 break;
1137 case SPEED_1000:
1138 reg = QCA8K_PORT_STATUS_SPEED_1000;
1139 break;
1140 default:
1141 reg = QCA8K_PORT_STATUS_LINK_AUTO;
1142 break;
1143 }
1144
1145 if (duplex == DUPLEX_FULL)
1146 reg |= QCA8K_PORT_STATUS_DUPLEX;
1147
1148 if (rx_pause || dsa_is_cpu_port(ds, port))
1149 reg |= QCA8K_PORT_STATUS_RXFLOW;
1150
1151 if (tx_pause || dsa_is_cpu_port(ds, port))
1152 reg |= QCA8K_PORT_STATUS_TXFLOW;
1153 }
1154
1155 reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
1156
1157 qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
1158 }
1159
1160 static void
1161 qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)
1162 {
1163 int i;
1164
1165 if (stringset != ETH_SS_STATS)
1166 return;
1167
1168 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)
1169 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
1170 ETH_GSTRING_LEN);
1171 }
1172
1173 static void
1174 qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
1175 uint64_t *data)
1176 {
1177 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1178 const struct qca8k_mib_desc *mib;
1179 u32 reg, i, val;
1180 u32 hi = 0;
1181 int ret;
1182
1183 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
1184 mib = &ar8327_mib[i];
1185 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
1186
1187 ret = qca8k_read(priv, reg, &val);
1188 if (ret < 0)
1189 continue;
1190
1191 if (mib->size == 2) {
1192 ret = qca8k_read(priv, reg + 4, &hi);
1193 if (ret < 0)
1194 continue;
1195 }
1196
1197 data[i] = val;
1198 if (mib->size == 2)
1199 data[i] |= (u64)hi << 32;
1200 }
1201 }
1202
1203 static int
1204 qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
1205 {
1206 if (sset != ETH_SS_STATS)
1207 return 0;
1208
1209 return ARRAY_SIZE(ar8327_mib);
1210 }
1211
1212 static int
1213 qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
1214 {
1215 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1216 u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
1217 u32 reg;
1218 int ret;
1219
1220 mutex_lock(&priv->reg_mutex);
1221 ret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, &reg);
1222 if (ret < 0)
1223 goto exit;
1224
1225 if (eee->eee_enabled)
1226 reg |= lpi_en;
1227 else
1228 reg &= ~lpi_en;
1229 ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
1230
1231 exit:
1232 mutex_unlock(&priv->reg_mutex);
1233 return ret;
1234 }
1235
1236 static int
1237 qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1238 {
1239 /* Nothing to do on the port's MAC */
1240 return 0;
1241 }
1242
1243 static void
1244 qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1245 {
1246 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1247 u32 stp_state;
1248
1249 switch (state) {
1250 case BR_STATE_DISABLED:
1251 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
1252 break;
1253 case BR_STATE_BLOCKING:
1254 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
1255 break;
1256 case BR_STATE_LISTENING:
1257 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
1258 break;
1259 case BR_STATE_LEARNING:
1260 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
1261 break;
1262 case BR_STATE_FORWARDING:
1263 default:
1264 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
1265 break;
1266 }
1267
1268 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1269 QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
1270 }
1271
1272 static int
1273 qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
1274 {
1275 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1276 int port_mask, cpu_port;
1277 int i, ret;
1278
1279 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1280 port_mask = BIT(cpu_port);
1281
1282 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1283 if (dsa_is_cpu_port(ds, i))
1284 continue;
1285 if (dsa_to_port(ds, i)->bridge_dev != br)
1286 continue;
1287 /* Add this port to the portvlan mask of the other ports
1288 * in the bridge
1289 */
1290 ret = qca8k_reg_set(priv,
1291 QCA8K_PORT_LOOKUP_CTRL(i),
1292 BIT(port));
1293 if (ret)
1294 return ret;
1295 if (i != port)
1296 port_mask |= BIT(i);
1297 }
1298
1299 /* Add all other ports to this ports portvlan mask */
1300 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1301 QCA8K_PORT_LOOKUP_MEMBER, port_mask);
1302
1303 return ret;
1304 }
1305
1306 static void
1307 qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)
1308 {
1309 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1310 int cpu_port, i;
1311
1312 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1313
1314 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1315 if (dsa_is_cpu_port(ds, i))
1316 continue;
1317 if (dsa_to_port(ds, i)->bridge_dev != br)
1318 continue;
1319 /* Remove this port to the portvlan mask of the other ports
1320 * in the bridge
1321 */
1322 qca8k_reg_clear(priv,
1323 QCA8K_PORT_LOOKUP_CTRL(i),
1324 BIT(port));
1325 }
1326
1327 /* Set the cpu port to be the only one in the portvlan mask of
1328 * this port
1329 */
1330 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1331 QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port));
1332 }
1333
1334 void qca8k_port_fast_age(struct dsa_switch *ds, int port)
1335 {
1336 struct qca8k_priv *priv = ds->priv;
1337
1338 mutex_lock(&priv->reg_mutex);
1339 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH_PORT, port);
1340 mutex_unlock(&priv->reg_mutex);
1341 }
1342
1343 int qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
1344 {
1345 struct qca8k_priv *priv = ds->priv;
1346 unsigned int secs = msecs / 1000;
1347 u32 val;
1348
1349 /* AGE_TIME reg is set in 7s step */
1350 val = secs / 7;
1351
1352 /* Handle case with 0 as val to NOT disable
1353 * learning
1354 */
1355 if (!val)
1356 val = 1;
1357
1358 return qca8k_rmw(priv, QCA8K_REG_ATU_CTRL,
1359 QCA8K_ATU_AGE_TIME_MASK,
1360 QCA8K_ATU_AGE_TIME(val));
1361 }
1362
1363 static int
1364 qca8k_port_enable(struct dsa_switch *ds, int port,
1365 struct phy_device *phy)
1366 {
1367 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1368
1369 qca8k_port_set_status(priv, port, 1);
1370 priv->port_sts[port].enabled = 1;
1371
1372 if (dsa_is_user_port(ds, port))
1373 phy_support_asym_pause(phy);
1374
1375 return 0;
1376 }
1377
1378 static void
1379 qca8k_port_disable(struct dsa_switch *ds, int port)
1380 {
1381 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1382
1383 qca8k_port_set_status(priv, port, 0);
1384 priv->port_sts[port].enabled = 0;
1385 }
1386
1387 static int
1388 qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1389 {
1390 struct qca8k_priv *priv = ds->priv;
1391 int i, mtu = 0;
1392
1393 priv->port_mtu[port] = new_mtu;
1394
1395 for (i = 0; i < QCA8K_NUM_PORTS; i++)
1396 if (priv->port_mtu[i] > mtu)
1397 mtu = priv->port_mtu[i];
1398
1399 /* Include L2 header / FCS length */
1400 return qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN);
1401 }
1402
1403 static int
1404 qca8k_port_max_mtu(struct dsa_switch *ds, int port)
1405 {
1406 return QCA8K_MAX_MTU;
1407 }
1408
1409 static int
1410 qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
1411 u16 port_mask, u16 vid)
1412 {
1413 /* Set the vid to the port vlan id if no vid is set */
1414 if (!vid)
1415 vid = QCA8K_PORT_VID_DEF;
1416
1417 return qca8k_fdb_add(priv, addr, port_mask, vid,
1418 QCA8K_ATU_STATUS_STATIC);
1419 }
1420
1421 static int
1422 qca8k_port_fdb_add(struct dsa_switch *ds, int port,
1423 const unsigned char *addr, u16 vid)
1424 {
1425 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1426 u16 port_mask = BIT(port);
1427
1428 return qca8k_port_fdb_insert(priv, addr, port_mask, vid);
1429 }
1430
1431 static int
1432 qca8k_port_fdb_del(struct dsa_switch *ds, int port,
1433 const unsigned char *addr, u16 vid)
1434 {
1435 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1436 u16 port_mask = BIT(port);
1437
1438 if (!vid)
1439 vid = QCA8K_PORT_VID_DEF;
1440
1441 return qca8k_fdb_del(priv, addr, port_mask, vid);
1442 }
1443
1444 static int
1445 qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
1446 dsa_fdb_dump_cb_t *cb, void *data)
1447 {
1448 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1449 struct qca8k_fdb _fdb = { 0 };
1450 int cnt = QCA8K_NUM_FDB_RECORDS;
1451 bool is_static;
1452 int ret = 0;
1453
1454 mutex_lock(&priv->reg_mutex);
1455 while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
1456 if (!_fdb.aging)
1457 break;
1458 is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC);
1459 ret = cb(_fdb.mac, _fdb.vid, is_static, data);
1460 if (ret)
1461 break;
1462 }
1463 mutex_unlock(&priv->reg_mutex);
1464
1465 return 0;
1466 }
1467
1468 static int
1469 qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1470 struct netlink_ext_ack *extack)
1471 {
1472 struct qca8k_priv *priv = ds->priv;
1473
1474 if (vlan_filtering) {
1475 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1476 QCA8K_PORT_LOOKUP_VLAN_MODE,
1477 QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE);
1478 } else {
1479 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1480 QCA8K_PORT_LOOKUP_VLAN_MODE,
1481 QCA8K_PORT_LOOKUP_VLAN_MODE_NONE);
1482 }
1483
1484 return 0;
1485 }
1486
1487 static int
1488 qca8k_port_vlan_add(struct dsa_switch *ds, int port,
1489 const struct switchdev_obj_port_vlan *vlan,
1490 struct netlink_ext_ack *extack)
1491 {
1492 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1493 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1494 struct qca8k_priv *priv = ds->priv;
1495 int ret = 0;
1496
1497 ret = qca8k_vlan_add(priv, port, vlan->vid, untagged);
1498 if (ret) {
1499 dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret);
1500 return ret;
1501 }
1502
1503 if (pvid) {
1504 int shift = 16 * (port % 2);
1505
1506 qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
1507 0xfff << shift, vlan->vid << shift);
1508 qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
1509 QCA8K_PORT_VLAN_CVID(vlan->vid) |
1510 QCA8K_PORT_VLAN_SVID(vlan->vid));
1511 }
1512 return 0;
1513 }
1514
1515 static int
1516 qca8k_port_vlan_del(struct dsa_switch *ds, int port,
1517 const struct switchdev_obj_port_vlan *vlan)
1518 {
1519 struct qca8k_priv *priv = ds->priv;
1520 int ret = 0;
1521
1522 ret = qca8k_vlan_del(priv, port, vlan->vid);
1523 if (ret)
1524 dev_err(priv->dev, "Failed to delete VLAN from port %d (%d)", port, ret);
1525
1526 return ret;
1527 }
1528
1529 static enum dsa_tag_protocol
1530 qca8k_get_tag_protocol(struct dsa_switch *ds, int port,
1531 enum dsa_tag_protocol mp)
1532 {
1533 return DSA_TAG_PROTO_IPQ4019;
1534 }
1535
1536 static const struct dsa_switch_ops qca8k_switch_ops = {
1537 .get_tag_protocol = qca8k_get_tag_protocol,
1538 .setup = qca8k_setup,
1539 .get_strings = qca8k_get_strings,
1540 .get_ethtool_stats = qca8k_get_ethtool_stats,
1541 .get_sset_count = qca8k_get_sset_count,
1542 .set_ageing_time = qca8k_set_ageing_time,
1543 .get_mac_eee = qca8k_get_mac_eee,
1544 .set_mac_eee = qca8k_set_mac_eee,
1545 .port_enable = qca8k_port_enable,
1546 .port_disable = qca8k_port_disable,
1547 .port_change_mtu = qca8k_port_change_mtu,
1548 .port_max_mtu = qca8k_port_max_mtu,
1549 .port_stp_state_set = qca8k_port_stp_state_set,
1550 .port_bridge_join = qca8k_port_bridge_join,
1551 .port_bridge_leave = qca8k_port_bridge_leave,
1552 .port_fast_age = qca8k_port_fast_age,
1553 .port_fdb_add = qca8k_port_fdb_add,
1554 .port_fdb_del = qca8k_port_fdb_del,
1555 .port_fdb_dump = qca8k_port_fdb_dump,
1556 .port_vlan_filtering = qca8k_port_vlan_filtering,
1557 .port_vlan_add = qca8k_port_vlan_add,
1558 .port_vlan_del = qca8k_port_vlan_del,
1559 .phylink_validate = qca8k_phylink_validate,
1560 .phylink_mac_link_state = qca8k_phylink_mac_link_state,
1561 .phylink_mac_config = qca8k_phylink_mac_config,
1562 .phylink_mac_link_down = qca8k_phylink_mac_link_down,
1563 .phylink_mac_link_up = qca8k_phylink_mac_link_up,
1564 };
1565
1566 static int
1567 qca8k_ipq4019_probe(struct platform_device *pdev)
1568 {
1569 struct qca8k_priv *priv;
1570 void __iomem *base, *psgmii;
1571 struct device_node *np = pdev->dev.of_node, *mdio_np, *psgmii_ethphy_np;
1572 int ret;
1573
1574 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1575 if (!priv)
1576 return -ENOMEM;
1577
1578 priv->dev = &pdev->dev;
1579
1580 base = devm_platform_ioremap_resource_byname(pdev, "base");
1581 if (IS_ERR(base))
1582 return PTR_ERR(base);
1583
1584 priv->regmap = devm_regmap_init_mmio(priv->dev, base,
1585 &qca8k_ipq4019_regmap_config);
1586 if (IS_ERR(priv->regmap)) {
1587 ret = PTR_ERR(priv->regmap);
1588 dev_err(priv->dev, "base regmap initialization failed, %d\n", ret);
1589 return ret;
1590 }
1591
1592 psgmii = devm_platform_ioremap_resource_byname(pdev, "psgmii_phy");
1593 if (IS_ERR(psgmii))
1594 return PTR_ERR(psgmii);
1595
1596 priv->psgmii = devm_regmap_init_mmio(priv->dev, psgmii,
1597 &qca8k_ipq4019_psgmii_phy_regmap_config);
1598 if (IS_ERR(priv->psgmii)) {
1599 ret = PTR_ERR(priv->psgmii);
1600 dev_err(priv->dev, "PSGMII regmap initialization failed, %d\n", ret);
1601 return ret;
1602 }
1603
1604 mdio_np = of_parse_phandle(np, "mdio", 0);
1605 if (!mdio_np) {
1606 dev_err(&pdev->dev, "unable to get MDIO bus phandle\n");
1607 of_node_put(mdio_np);
1608 return -EINVAL;
1609 }
1610
1611 priv->bus = of_mdio_find_bus(mdio_np);
1612 of_node_put(mdio_np);
1613 if (!priv->bus) {
1614 dev_err(&pdev->dev, "unable to find MDIO bus\n");
1615 return -EPROBE_DEFER;
1616 }
1617
1618 psgmii_ethphy_np = of_parse_phandle(np, "psgmii-ethphy", 0);
1619 if (!psgmii_ethphy_np) {
1620 dev_dbg(&pdev->dev, "unable to get PSGMII eth PHY phandle\n");
1621 of_node_put(psgmii_ethphy_np);
1622 }
1623
1624 if (psgmii_ethphy_np) {
1625 priv->psgmii_ethphy = of_phy_find_device(psgmii_ethphy_np);
1626 of_node_put(psgmii_ethphy_np);
1627 if (!priv->psgmii_ethphy) {
1628 dev_err(&pdev->dev, "unable to get PSGMII eth PHY\n");
1629 return -ENODEV;
1630 }
1631 }
1632
1633 priv->ds = devm_kzalloc(priv->dev, sizeof(*priv->ds), GFP_KERNEL);
1634 if (!priv->ds)
1635 return -ENOMEM;
1636
1637 priv->ds->dev = priv->dev;
1638 priv->ds->num_ports = QCA8K_NUM_PORTS;
1639 priv->ds->priv = priv;
1640 priv->ops = qca8k_switch_ops;
1641 priv->ds->ops = &priv->ops;
1642
1643 mutex_init(&priv->reg_mutex);
1644 platform_set_drvdata(pdev, priv);
1645
1646 return dsa_register_switch(priv->ds);
1647 }
1648
1649 static int
1650 qca8k_ipq4019_remove(struct platform_device *pdev)
1651 {
1652 struct qca8k_priv *priv = dev_get_drvdata(&pdev->dev);
1653 int i;
1654
1655 if (!priv)
1656 return 0;
1657
1658 for (i = 0; i < QCA8K_NUM_PORTS; i++)
1659 qca8k_port_set_status(priv, i, 0);
1660
1661 dsa_unregister_switch(priv->ds);
1662
1663 dev_set_drvdata(&pdev->dev, NULL);
1664
1665 return 0;
1666 }
1667
1668 static const struct of_device_id qca8k_ipq4019_of_match[] = {
1669 { .compatible = "qca,ipq4019-qca8337n" },
1670 { /* sentinel */ },
1671 };
1672
1673 static struct platform_driver qca8k_ipq4019_driver = {
1674 .probe = qca8k_ipq4019_probe,
1675 .remove = qca8k_ipq4019_remove,
1676 .driver = {
1677 .name = "qca8k-ipq4019",
1678 .of_match_table = qca8k_ipq4019_of_match,
1679 },
1680 };
1681
1682 module_platform_driver(qca8k_ipq4019_driver);
1683
1684 MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
1685 MODULE_AUTHOR("Gabor Juhos <j4g8y7@gmail.com>, Robert Marko <robert.marko@sartura.hr>");
1686 MODULE_DESCRIPTION("Qualcomm IPQ4019 built-in switch driver");
1687 MODULE_LICENSE("GPL v2");
Staging tree of Jo-Philipp Wich