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kernel: backport phylink changes from mainline Linux
[openwrt/staging/jow.git] / target / linux / generic / backport-6.1 / 750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch
1 From 94f825a7eadfc8b4c8828efdb7705d9703f9c73e Mon Sep 17 00:00:00 2001
2 From: Lorenzo Bianconi <lorenzo@kernel.org>
3 Date: Tue, 25 Jul 2023 01:57:42 +0100
4 Subject: [PATCH 105/250] net: ethernet: mtk_eth_soc: add basic support for
5 MT7988 SoC
6
7 Introduce support for ethernet chip available in MT7988 SoC to
8 mtk_eth_soc driver. As a first step support only the first GMAC which
9 is hard-wired to the internal DSA switch having 4 built-in gigabit
10 Ethernet PHYs.
11
12 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
13 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
14 Link: https://lore.kernel.org/r/25c8377095b95d186872eeda7aa055da83e8f0ca.1690246605.git.daniel@makrotopia.org
15 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
16 ---
17 drivers/net/ethernet/mediatek/mtk_eth_path.c | 14 +-
18 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 201 +++++++++++++++++--
19 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 86 +++++++-
20 3 files changed, 273 insertions(+), 28 deletions(-)
21
22 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
23 +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
24 @@ -43,7 +43,7 @@ static const char *mtk_eth_path_name(u64
25 static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path)
26 {
27 bool updated = true;
28 - u32 val, mask, set;
29 + u32 mask, set, reg;
30
31 switch (path) {
32 case MTK_ETH_PATH_GMAC1_SGMII:
33 @@ -59,11 +59,13 @@ static int set_mux_gdm1_to_gmac1_esw(str
34 break;
35 }
36
37 - if (updated) {
38 - val = mtk_r32(eth, MTK_MAC_MISC);
39 - val = (val & mask) | set;
40 - mtk_w32(eth, val, MTK_MAC_MISC);
41 - }
42 + if (mtk_is_netsys_v3_or_greater(eth))
43 + reg = MTK_MAC_MISC_V3;
44 + else
45 + reg = MTK_MAC_MISC;
46 +
47 + if (updated)
48 + mtk_m32(eth, mask, set, reg);
49
50 dev_dbg(eth->dev, "path %s in %s updated = %d\n",
51 mtk_eth_path_name(path), __func__, updated);
52 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
53 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
54 @@ -152,6 +152,54 @@ static const struct mtk_reg_map mt7986_r
55 .pse_oq_sta = 0x01a0,
56 };
57
58 +static const struct mtk_reg_map mt7988_reg_map = {
59 + .tx_irq_mask = 0x461c,
60 + .tx_irq_status = 0x4618,
61 + .pdma = {
62 + .rx_ptr = 0x6900,
63 + .rx_cnt_cfg = 0x6904,
64 + .pcrx_ptr = 0x6908,
65 + .glo_cfg = 0x6a04,
66 + .rst_idx = 0x6a08,
67 + .delay_irq = 0x6a0c,
68 + .irq_status = 0x6a20,
69 + .irq_mask = 0x6a28,
70 + .adma_rx_dbg0 = 0x6a38,
71 + .int_grp = 0x6a50,
72 + },
73 + .qdma = {
74 + .qtx_cfg = 0x4400,
75 + .qtx_sch = 0x4404,
76 + .rx_ptr = 0x4500,
77 + .rx_cnt_cfg = 0x4504,
78 + .qcrx_ptr = 0x4508,
79 + .glo_cfg = 0x4604,
80 + .rst_idx = 0x4608,
81 + .delay_irq = 0x460c,
82 + .fc_th = 0x4610,
83 + .int_grp = 0x4620,
84 + .hred = 0x4644,
85 + .ctx_ptr = 0x4700,
86 + .dtx_ptr = 0x4704,
87 + .crx_ptr = 0x4710,
88 + .drx_ptr = 0x4714,
89 + .fq_head = 0x4720,
90 + .fq_tail = 0x4724,
91 + .fq_count = 0x4728,
92 + .fq_blen = 0x472c,
93 + .tx_sch_rate = 0x4798,
94 + },
95 + .gdm1_cnt = 0x1c00,
96 + .gdma_to_ppe = 0x3333,
97 + .ppe_base = 0x2000,
98 + .wdma_base = {
99 + [0] = 0x4800,
100 + [1] = 0x4c00,
101 + },
102 + .pse_iq_sta = 0x0180,
103 + .pse_oq_sta = 0x01a0,
104 +};
105 +
106 /* strings used by ethtool */
107 static const struct mtk_ethtool_stats {
108 char str[ETH_GSTRING_LEN];
109 @@ -179,10 +227,54 @@ static const struct mtk_ethtool_stats {
110 };
111
112 static const char * const mtk_clks_source_name[] = {
113 - "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll",
114 - "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
115 - "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb",
116 - "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1"
117 + "ethif",
118 + "sgmiitop",
119 + "esw",
120 + "gp0",
121 + "gp1",
122 + "gp2",
123 + "gp3",
124 + "xgp1",
125 + "xgp2",
126 + "xgp3",
127 + "crypto",
128 + "fe",
129 + "trgpll",
130 + "sgmii_tx250m",
131 + "sgmii_rx250m",
132 + "sgmii_cdr_ref",
133 + "sgmii_cdr_fb",
134 + "sgmii2_tx250m",
135 + "sgmii2_rx250m",
136 + "sgmii2_cdr_ref",
137 + "sgmii2_cdr_fb",
138 + "sgmii_ck",
139 + "eth2pll",
140 + "wocpu0",
141 + "wocpu1",
142 + "netsys0",
143 + "netsys1",
144 + "ethwarp_wocpu2",
145 + "ethwarp_wocpu1",
146 + "ethwarp_wocpu0",
147 + "top_usxgmii0_sel",
148 + "top_usxgmii1_sel",
149 + "top_sgm0_sel",
150 + "top_sgm1_sel",
151 + "top_xfi_phy0_xtal_sel",
152 + "top_xfi_phy1_xtal_sel",
153 + "top_eth_gmii_sel",
154 + "top_eth_refck_50m_sel",
155 + "top_eth_sys_200m_sel",
156 + "top_eth_sys_sel",
157 + "top_eth_xgmii_sel",
158 + "top_eth_mii_sel",
159 + "top_netsys_sel",
160 + "top_netsys_500m_sel",
161 + "top_netsys_pao_2x_sel",
162 + "top_netsys_sync_250m_sel",
163 + "top_netsys_ppefb_250m_sel",
164 + "top_netsys_warp_sel",
165 };
166
167 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
168 @@ -195,7 +287,7 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
169 return __raw_readl(eth->base + reg);
170 }
171
172 -static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg)
173 +u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg)
174 {
175 u32 val;
176
177 @@ -369,6 +461,19 @@ static void mtk_gmac0_rgmii_adjust(struc
178 dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n");
179 }
180
181 +static void mtk_setup_bridge_switch(struct mtk_eth *eth)
182 +{
183 + /* Force Port1 XGMAC Link Up */
184 + mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID),
185 + MTK_XGMAC_STS(MTK_GMAC1_ID));
186 +
187 + /* Adjust GSW bridge IPG to 11 */
188 + mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK,
189 + (GSW_IPG_11 << GSWTX_IPG_SHIFT) |
190 + (GSW_IPG_11 << GSWRX_IPG_SHIFT),
191 + MTK_GSW_CFG);
192 +}
193 +
194 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
195 phy_interface_t interface)
196 {
197 @@ -438,6 +543,8 @@ static void mtk_mac_config(struct phylin
198 goto init_err;
199 }
200 break;
201 + case PHY_INTERFACE_MODE_INTERNAL:
202 + break;
203 default:
204 goto err_phy;
205 }
206 @@ -515,6 +622,15 @@ static void mtk_mac_config(struct phylin
207 return;
208 }
209
210 + /* Setup gmac */
211 + if (mtk_is_netsys_v3_or_greater(eth) &&
212 + mac->interface == PHY_INTERFACE_MODE_INTERNAL) {
213 + mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
214 + mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
215 +
216 + mtk_setup_bridge_switch(eth);
217 + }
218 +
219 return;
220
221 err_phy:
222 @@ -725,11 +841,15 @@ static int mtk_mdio_init(struct mtk_eth
223 }
224 divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
225
226 + /* Configure MDC Turbo Mode */
227 + if (mtk_is_netsys_v3_or_greater(eth))
228 + mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3);
229 +
230 /* Configure MDC Divider */
231 - val = mtk_r32(eth, MTK_PPSC);
232 - val &= ~PPSC_MDC_CFG;
233 - val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO;
234 - mtk_w32(eth, val, MTK_PPSC);
235 + val = FIELD_PREP(PPSC_MDC_CFG, divider);
236 + if (!mtk_is_netsys_v3_or_greater(eth))
237 + val |= PPSC_MDC_TURBO;
238 + mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC);
239
240 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
241
242 @@ -1190,10 +1310,19 @@ static void mtk_tx_set_dma_desc_v2(struc
243 data |= TX_DMA_LS0;
244 WRITE_ONCE(desc->txd3, data);
245
246 - if (mac->id == MTK_GMAC3_ID)
247 - data = PSE_GDM3_PORT;
248 - else
249 - data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */
250 + /* set forward port */
251 + switch (mac->id) {
252 + case MTK_GMAC1_ID:
253 + data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2;
254 + break;
255 + case MTK_GMAC2_ID:
256 + data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2;
257 + break;
258 + case MTK_GMAC3_ID:
259 + data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2;
260 + break;
261 + }
262 +
263 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
264 WRITE_ONCE(desc->txd4, data);
265
266 @@ -4360,6 +4489,17 @@ static int mtk_add_mac(struct mtk_eth *e
267 mac->phylink_config.supported_interfaces);
268 }
269
270 + if (mtk_is_netsys_v3_or_greater(mac->hw) &&
271 + MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) &&
272 + id == MTK_GMAC1_ID) {
273 + mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
274 + MAC_SYM_PAUSE |
275 + MAC_10000FD;
276 + phy_interface_zero(mac->phylink_config.supported_interfaces);
277 + __set_bit(PHY_INTERFACE_MODE_INTERNAL,
278 + mac->phylink_config.supported_interfaces);
279 + }
280 +
281 phylink = phylink_create(&mac->phylink_config,
282 of_fwnode_handle(mac->of_node),
283 phy_mode, &mtk_phylink_ops);
284 @@ -4880,6 +5020,24 @@ static const struct mtk_soc_data mt7986_
285 },
286 };
287
288 +static const struct mtk_soc_data mt7988_data = {
289 + .reg_map = &mt7988_reg_map,
290 + .ana_rgc3 = 0x128,
291 + .caps = MT7988_CAPS,
292 + .hw_features = MTK_HW_FEATURES,
293 + .required_clks = MT7988_CLKS_BITMAP,
294 + .required_pctl = false,
295 + .version = 3,
296 + .txrx = {
297 + .txd_size = sizeof(struct mtk_tx_dma_v2),
298 + .rxd_size = sizeof(struct mtk_rx_dma_v2),
299 + .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
300 + .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
301 + .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
302 + .dma_len_offset = 8,
303 + },
304 +};
305 +
306 static const struct mtk_soc_data rt5350_data = {
307 .reg_map = &mt7628_reg_map,
308 .caps = MT7628_CAPS,
309 @@ -4898,14 +5056,15 @@ static const struct mtk_soc_data rt5350_
310 };
311
312 const struct of_device_id of_mtk_match[] = {
313 - { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
314 - { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data},
315 - { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
316 - { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
317 - { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
318 - { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data},
319 - { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data},
320 - { .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
321 + { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data },
322 + { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
323 + { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data },
324 + { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data },
325 + { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data },
326 + { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data },
327 + { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data },
328 + { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data },
329 + { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
330 {},
331 };
332 MODULE_DEVICE_TABLE(of, of_mtk_match);
333 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
334 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
335 @@ -117,7 +117,8 @@
336 #define MTK_CDMP_EG_CTRL 0x404
337
338 /* GDM Exgress Control Register */
339 -#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
340 +#define MTK_GDMA_FWD_CFG(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \
341 + 0x540 : 0x500 + (_x * 0x1000); })
342 #define MTK_GDMA_SPECIAL_TAG BIT(24)
343 #define MTK_GDMA_ICS_EN BIT(22)
344 #define MTK_GDMA_TCS_EN BIT(21)
345 @@ -126,6 +127,11 @@
346 #define MTK_GDMA_TO_PDMA 0x0
347 #define MTK_GDMA_DROP_ALL 0x7777
348
349 +/* GDM Egress Control Register */
350 +#define MTK_GDMA_EG_CTRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \
351 + 0x544 : 0x504 + (_x * 0x1000); })
352 +#define MTK_GDMA_XGDM_SEL BIT(31)
353 +
354 /* Unicast Filter MAC Address Register - Low */
355 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
356
357 @@ -389,7 +395,26 @@
358 #define PHY_IAC_TIMEOUT HZ
359
360 #define MTK_MAC_MISC 0x1000c
361 +#define MTK_MAC_MISC_V3 0x10010
362 #define MTK_MUX_TO_ESW BIT(0)
363 +#define MISC_MDC_TURBO BIT(4)
364 +
365 +/* XMAC status registers */
366 +#define MTK_XGMAC_STS(x) (((x) == MTK_GMAC3_ID) ? 0x1001C : 0x1000C)
367 +#define MTK_XGMAC_FORCE_LINK(x) (((x) == MTK_GMAC2_ID) ? BIT(31) : BIT(15))
368 +#define MTK_USXGMII_PCS_LINK BIT(8)
369 +#define MTK_XGMAC_RX_FC BIT(5)
370 +#define MTK_XGMAC_TX_FC BIT(4)
371 +#define MTK_USXGMII_PCS_MODE GENMASK(3, 1)
372 +#define MTK_XGMAC_LINK_STS BIT(0)
373 +
374 +/* GSW bridge registers */
375 +#define MTK_GSW_CFG (0x10080)
376 +#define GSWTX_IPG_MASK GENMASK(19, 16)
377 +#define GSWTX_IPG_SHIFT 16
378 +#define GSWRX_IPG_MASK GENMASK(3, 0)
379 +#define GSWRX_IPG_SHIFT 0
380 +#define GSW_IPG_11 11
381
382 /* Mac control registers */
383 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
384 @@ -647,6 +672,11 @@ enum mtk_clks_map {
385 MTK_CLK_GP0,
386 MTK_CLK_GP1,
387 MTK_CLK_GP2,
388 + MTK_CLK_GP3,
389 + MTK_CLK_XGP1,
390 + MTK_CLK_XGP2,
391 + MTK_CLK_XGP3,
392 + MTK_CLK_CRYPTO,
393 MTK_CLK_FE,
394 MTK_CLK_TRGPLL,
395 MTK_CLK_SGMII_TX_250M,
396 @@ -663,6 +693,27 @@ enum mtk_clks_map {
397 MTK_CLK_WOCPU1,
398 MTK_CLK_NETSYS0,
399 MTK_CLK_NETSYS1,
400 + MTK_CLK_ETHWARP_WOCPU2,
401 + MTK_CLK_ETHWARP_WOCPU1,
402 + MTK_CLK_ETHWARP_WOCPU0,
403 + MTK_CLK_TOP_USXGMII_SBUS_0_SEL,
404 + MTK_CLK_TOP_USXGMII_SBUS_1_SEL,
405 + MTK_CLK_TOP_SGM_0_SEL,
406 + MTK_CLK_TOP_SGM_1_SEL,
407 + MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL,
408 + MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL,
409 + MTK_CLK_TOP_ETH_GMII_SEL,
410 + MTK_CLK_TOP_ETH_REFCK_50M_SEL,
411 + MTK_CLK_TOP_ETH_SYS_200M_SEL,
412 + MTK_CLK_TOP_ETH_SYS_SEL,
413 + MTK_CLK_TOP_ETH_XGMII_SEL,
414 + MTK_CLK_TOP_ETH_MII_SEL,
415 + MTK_CLK_TOP_NETSYS_SEL,
416 + MTK_CLK_TOP_NETSYS_500M_SEL,
417 + MTK_CLK_TOP_NETSYS_PAO_2X_SEL,
418 + MTK_CLK_TOP_NETSYS_SYNC_250M_SEL,
419 + MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL,
420 + MTK_CLK_TOP_NETSYS_WARP_SEL,
421 MTK_CLK_MAX
422 };
423
424 @@ -716,6 +767,36 @@ enum mtk_clks_map {
425 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
426 BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
427 BIT_ULL(MTK_CLK_SGMII2_CDR_FB))
428 +#define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \
429 + BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
430 + BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
431 + BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
432 + BIT_ULL(MTK_CLK_CRYPTO) | \
433 + BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
434 + BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
435 + BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
436 + BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
437 + BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \
438 + BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \
439 + BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \
440 + BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \
441 + BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \
442 + BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \
443 + BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \
444 + BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \
445 + BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \
446 + BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
447 + BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
448 + BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
449 + BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \
450 + BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \
451 + BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \
452 + BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \
453 + BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \
454 + BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \
455 + BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \
456 + BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \
457 + BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL))
458
459 enum mtk_dev_state {
460 MTK_HW_INIT,
461 @@ -964,6 +1045,8 @@ enum mkt_eth_capabilities {
462 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
463 MTK_RSTCTRL_PPE1)
464
465 +#define MT7988_CAPS (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1)
466 +
467 struct mtk_tx_dma_desc_info {
468 dma_addr_t addr;
469 u32 size;
470 @@ -1309,6 +1392,7 @@ void mtk_stats_update_mac(struct mtk_mac
471
472 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
473 u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
474 +u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
475
476 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
477 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
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