projects / openwrt / staging / jow.git / blob
? search:


7cc0ab225ebeeb34a2ed20f202ce4a0aa05df3da
[openwrt/staging/jow.git] / target / linux / generic / backport-5.15 / 714-v6.0-net-ethernet-mtk_eth_soc-move-ppe-table-hash-offset-.patch
1 From patchwork Thu Sep 8 19:33:38 2022
2 Content-Type: text/plain; charset="utf-8"
3 MIME-Version: 1.0
4 Content-Transfer-Encoding: 7bit
5 X-Patchwork-Submitter: Lorenzo Bianconi <lorenzo@kernel.org>
6 X-Patchwork-Id: 12970557
7 X-Patchwork-Delegate: kuba@kernel.org
8 From: Lorenzo Bianconi <lorenzo@kernel.org>
9 To: netdev@vger.kernel.org
10 Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com,
11 Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com,
12 kuba@kernel.org, pabeni@redhat.com, matthias.bgg@gmail.com,
13 linux-mediatek@lists.infradead.org, lorenzo.bianconi@redhat.com,
14 Bo.Jiao@mediatek.com, sujuan.chen@mediatek.com,
15 ryder.Lee@mediatek.com, evelyn.tsai@mediatek.com,
16 devicetree@vger.kernel.org, robh@kernel.org
17 Subject: [PATCH net-next 04/12] net: ethernet: mtk_eth_soc: move ppe table
18 hash offset to mtk_soc_data structure
19 Date: Thu, 8 Sep 2022 21:33:38 +0200
20 Message-Id:
21 <cc263ffeaa3e1d7314e36a4f941e96d38e41a6bf.1662661555.git.lorenzo@kernel.org>
22 X-Mailer: git-send-email 2.37.3
23 In-Reply-To: <cover.1662661555.git.lorenzo@kernel.org>
24 References: <cover.1662661555.git.lorenzo@kernel.org>
25 MIME-Version: 1.0
26 Precedence: bulk
27 List-ID: <netdev.vger.kernel.org>
28 X-Mailing-List: netdev@vger.kernel.org
29 X-Patchwork-Delegate: kuba@kernel.org
30
31 This is a preliminary patch to introduce mt7986 hw packet engine.
32
33 Co-developed-by: Bo Jiao <Bo.Jiao@mediatek.com>
34 Signed-off-by: Bo Jiao <Bo.Jiao@mediatek.com>
35 Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
36 Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
37 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
38 ---
39 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 4 ++++
40 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 ++
41 drivers/net/ethernet/mediatek/mtk_ppe.c | 24 +++++++++++++++------
42 drivers/net/ethernet/mediatek/mtk_ppe.h | 2 +-
43 4 files changed, 25 insertions(+), 7 deletions(-)
44
45 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
46 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
47 @@ -4144,6 +4144,7 @@ static const struct mtk_soc_data mt7621_
48 .required_clks = MT7621_CLKS_BITMAP,
49 .required_pctl = false,
50 .offload_version = 2,
51 + .hash_offset = 2,
52 .txrx = {
53 .txd_size = sizeof(struct mtk_tx_dma),
54 .rxd_size = sizeof(struct mtk_rx_dma),
55 @@ -4162,6 +4163,7 @@ static const struct mtk_soc_data mt7622_
56 .required_clks = MT7622_CLKS_BITMAP,
57 .required_pctl = false,
58 .offload_version = 2,
59 + .hash_offset = 2,
60 .txrx = {
61 .txd_size = sizeof(struct mtk_tx_dma),
62 .rxd_size = sizeof(struct mtk_rx_dma),
63 @@ -4179,6 +4181,7 @@ static const struct mtk_soc_data mt7623_
64 .required_clks = MT7623_CLKS_BITMAP,
65 .required_pctl = true,
66 .offload_version = 2,
67 + .hash_offset = 2,
68 .txrx = {
69 .txd_size = sizeof(struct mtk_tx_dma),
70 .rxd_size = sizeof(struct mtk_rx_dma),
71 @@ -4212,6 +4215,7 @@ static const struct mtk_soc_data mt7986_
72 .caps = MT7986_CAPS,
73 .required_clks = MT7986_CLKS_BITMAP,
74 .required_pctl = false,
75 + .hash_offset = 4,
76 .txrx = {
77 .txd_size = sizeof(struct mtk_tx_dma_v2),
78 .rxd_size = sizeof(struct mtk_rx_dma_v2),
79 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
80 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
81 @@ -967,6 +967,7 @@ struct mtk_reg_map {
82 * the target SoC
83 * @required_pctl A bool value to show whether the SoC requires
84 * the extra setup for those pins used by GMAC.
85 + * @hash_offset Flow table hash offset.
86 * @txd_size Tx DMA descriptor size.
87 * @rxd_size Rx DMA descriptor size.
88 * @rx_irq_done_mask Rx irq done register mask.
89 @@ -981,6 +982,7 @@ struct mtk_soc_data {
90 u32 required_clks;
91 bool required_pctl;
92 u8 offload_version;
93 + u8 hash_offset;
94 netdev_features_t hw_features;
95 struct {
96 u32 txd_size;
97 --- a/drivers/net/ethernet/mediatek/mtk_ppe.c
98 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
99 @@ -88,7 +88,7 @@ static void mtk_ppe_cache_enable(struct
100 enable * MTK_PPE_CACHE_CTL_EN);
101 }
102
103 -static u32 mtk_ppe_hash_entry(struct mtk_foe_entry *e)
104 +static u32 mtk_ppe_hash_entry(struct mtk_eth *eth, struct mtk_foe_entry *e)
105 {
106 u32 hv1, hv2, hv3;
107 u32 hash;
108 @@ -122,7 +122,7 @@ static u32 mtk_ppe_hash_entry(struct mtk
109 hash = (hash >> 24) | ((hash & 0xffffff) << 8);
110 hash ^= hv1 ^ hv2 ^ hv3;
111 hash ^= hash >> 16;
112 - hash <<= 1;
113 + hash <<= (ffs(eth->soc->hash_offset) - 1);
114 hash &= MTK_PPE_ENTRIES - 1;
115
116 return hash;
117 @@ -540,15 +540,16 @@ mtk_foe_entry_commit_l2(struct mtk_ppe *
118 int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)
119 {
120 int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->data.ib1);
121 + const struct mtk_soc_data *soc = ppe->eth->soc;
122 u32 hash;
123
124 if (type == MTK_PPE_PKT_TYPE_BRIDGE)
125 return mtk_foe_entry_commit_l2(ppe, entry);
126
127 - hash = mtk_ppe_hash_entry(&entry->data);
128 + hash = mtk_ppe_hash_entry(ppe->eth, &entry->data);
129 entry->hash = 0xffff;
130 spin_lock_bh(&ppe_lock);
131 - hlist_add_head(&entry->list, &ppe->foe_flow[hash / 2]);
132 + hlist_add_head(&entry->list, &ppe->foe_flow[hash / soc->hash_offset]);
133 spin_unlock_bh(&ppe_lock);
134
135 return 0;
136 @@ -558,6 +559,7 @@ static void
137 mtk_foe_entry_commit_subflow(struct mtk_ppe *ppe, struct mtk_flow_entry *entry,
138 u16 hash)
139 {
140 + const struct mtk_soc_data *soc = ppe->eth->soc;
141 struct mtk_flow_entry *flow_info;
142 struct mtk_foe_entry foe, *hwe;
143 struct mtk_foe_mac_info *l2;
144 @@ -572,7 +574,8 @@ mtk_foe_entry_commit_subflow(struct mtk_
145 flow_info->l2_data.base_flow = entry;
146 flow_info->type = MTK_FLOW_TYPE_L2_SUBFLOW;
147 flow_info->hash = hash;
148 - hlist_add_head(&flow_info->list, &ppe->foe_flow[hash / 2]);
149 + hlist_add_head(&flow_info->list,
150 + &ppe->foe_flow[hash / soc->hash_offset]);
151 hlist_add_head(&flow_info->l2_data.list, &entry->l2_flows);
152
153 hwe = &ppe->foe_table[hash];
154 @@ -596,7 +599,8 @@ mtk_foe_entry_commit_subflow(struct mtk_
155
156 void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash)
157 {
158 - struct hlist_head *head = &ppe->foe_flow[hash / 2];
159 + const struct mtk_soc_data *soc = ppe->eth->soc;
160 + struct hlist_head *head = &ppe->foe_flow[hash / soc->hash_offset];
161 struct mtk_foe_entry *hwe = &ppe->foe_table[hash];
162 struct mtk_flow_entry *entry;
163 struct mtk_foe_bridge key = {};
164 @@ -680,9 +684,11 @@ int mtk_foe_entry_idle_time(struct mtk_p
165 struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base,
166 int version)
167 {
168 + const struct mtk_soc_data *soc = eth->soc;
169 struct device *dev = eth->dev;
170 struct mtk_foe_entry *foe;
171 struct mtk_ppe *ppe;
172 + u32 foe_flow_size;
173
174 ppe = devm_kzalloc(dev, sizeof(*ppe), GFP_KERNEL);
175 if (!ppe)
176 @@ -705,6 +711,12 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
177
178 ppe->foe_table = foe;
179
180 + foe_flow_size = (MTK_PPE_ENTRIES / soc->hash_offset) *
181 + sizeof(*ppe->foe_flow);
182 + ppe->foe_flow = devm_kzalloc(dev, foe_flow_size, GFP_KERNEL);
183 + if (!ppe->foe_flow)
184 + return NULL;
185 +
186 mtk_ppe_debugfs_init(ppe);
187
188 return ppe;
189 --- a/drivers/net/ethernet/mediatek/mtk_ppe.h
190 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
191 @@ -270,7 +270,7 @@ struct mtk_ppe {
192 dma_addr_t foe_phys;
193
194 u16 foe_check_time[MTK_PPE_ENTRIES];
195 - struct hlist_head foe_flow[MTK_PPE_ENTRIES / 2];
196 + struct hlist_head *foe_flow;
197
198 struct rhashtable l2_flows;
199
Staging tree of Jo-Philipp Wich