target/linux/ath79/patches-4.14/0035-MIPS-ath79-fix-QCA956x-boot.patch

   1 --- a/arch/mips/ath79/clock.c   2018-06-01 13:56:30.376729328 +0300
   2 +++ b/arch/mips/ath79/clock.c   2018-06-04 02:06:57.039616840 +0300
   3 @@ -525,6 +525,14 @@
   4         u32 cpu_pll, ddr_pll;
   5         u32 bootstrap;
   6
   7 +       /* QCA956x timer init workaround has to be applied right before setting
   8 +       * up the clock. Else, there will be no jiffies */
   9 +       u32 misc;
  10 +
  11 +       misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
  12 +       misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
  13 +       ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
  14 +
  15         bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
  16         if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
  17                 ref_rate = 40 * 1000 * 1000;