target/linux/ath79/patches-4.14/0031-MIPS-ath79-make-specifying-the-reference-clock-in-DT.patch

   1 From: Felix Fietkau <nbd@nbd.name>
   2 Date: Tue, 6 Mar 2018 13:24:07 +0100
   3 Subject: [PATCH] MIPS: ath79: make specifying the reference clock in DT
   4  optional
   5
   6 It can be autodetected for many SoCs using the strapping options.
   7 If the clock is specified in DT, the autodetected value is ignored
   8
   9 Signed-off-by: Felix Fietkau <nbd@nbd.name>
  10 ---
  11
  12 --- a/arch/mips/ath79/clock.c
  13 +++ b/arch/mips/ath79/clock.c
  14 @@ -79,6 +79,18 @@ static struct clk * __init ath79_set_ff_
  15         return clk;
  16  }
  17
  18 +static unsigned long __init ath79_setup_ref_clk(unsigned long rate)
  19 +{
  20 +       struct clk *clk = clks[ATH79_CLK_REF];
  21 +
  22 +       if (clk)
  23 +               rate = clk_get_rate(clk);
  24 +       else
  25 +               clk = ath79_set_clk(ATH79_CLK_REF, rate);
  26 +
  27 +       return rate;
  28 +}
  29 +
  30  static void __init ar71xx_clocks_init(void __iomem *pll_base)
  31  {
  32         unsigned long ref_rate;
  33 @@ -89,7 +101,7 @@ static void __init ar71xx_clocks_init(vo
  34         u32 freq;
  35         u32 div;
  36
  37 -       ref_rate = AR71XX_BASE_FREQ;
  38 +       ref_rate = ath79_setup_ref_clk(AR71XX_BASE_FREQ);
  39
  40         pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
  41
  42 @@ -105,16 +117,17 @@ static void __init ar71xx_clocks_init(vo
  43         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
  44         ahb_rate = cpu_rate / div;
  45
  46 -       ath79_set_clk(ATH79_CLK_REF, ref_rate);
  47         ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
  48         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
  49         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
  50  }
  51
  52 -static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
  53 +static void __init ar724x_clocks_init(void __iomem *pll_base)
  54  {
  55 -       u32 pll;
  56         u32 mult, div, ddr_div, ahb_div;
  57 +       u32 pll;
  58 +
  59 +       ath79_setup_ref_clk(AR71XX_BASE_FREQ);
  60
  61         pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
  62
  63 @@ -129,17 +142,9 @@ static void __init ar724x_clk_init(struc
  64         ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
  65  }
  66
  67 -static void __init ar724x_clocks_init(void __iomem *pll_base)
  68 -{
  69 -       struct clk *ref_clk;
  70 -
  71 -       ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
  72 -
  73 -       ar724x_clk_init(ref_clk, pll_base);
  74 -}
  75 -
  76 -static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
  77 +static void __init ar933x_clocks_init(void __iomem *pll_base)
  78  {
  79 +       unsigned long ref_rate;
  80         u32 clock_ctrl;
  81         u32 ref_div;
  82         u32 ninit_mul;
  83 @@ -148,6 +153,15 @@ static void __init ar9330_clk_init(struc
  84         u32 cpu_div;
  85         u32 ddr_div;
  86         u32 ahb_div;
  87 +       u32 t;
  88 +
  89 +       t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
  90 +       if (t & AR933X_BOOTSTRAP_REF_CLK_40)
  91 +               ref_rate = (40 * 1000 * 1000);
  92 +       else
  93 +               ref_rate = (25 * 1000 * 1000);
  94 +
  95 +       ath79_setup_ref_clk(ref_rate);
  96
  97         clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
  98         if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
  99 @@ -196,23 +210,6 @@ static void __init ar9330_clk_init(struc
 100                          ref_div * out_div * ahb_div);
 101  }
 102
 103 -static void __init ar933x_clocks_init(void __iomem *pll_base)
 104 -{
 105 -       struct clk *ref_clk;
 106 -       unsigned long ref_rate;
 107 -       u32 t;
 108 -
 109 -       t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
 110 -       if (t & AR933X_BOOTSTRAP_REF_CLK_40)
 111 -               ref_rate = (40 * 1000 * 1000);
 112 -       else
 113 -               ref_rate = (25 * 1000 * 1000);
 114 -
 115 -       ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
 116 -
 117 -       ar9330_clk_init(ref_clk, ath79_pll_base);
 118 -}
 119 -
 120  static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
 121                                       u32 frac, u32 out_div)
 122  {
 123 @@ -252,6 +249,8 @@ static void __init ar934x_clocks_init(vo
 124         else
 125                 ref_rate = 25 * 1000 * 1000;
 126
 127 +       ref_rate = ath79_setup_ref_clk(ref_rate);
 128 +
 129         pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
 130         if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
 131                 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
 132 @@ -338,7 +337,6 @@ static void __init ar934x_clocks_init(vo
 133         else
 134                 ahb_rate = cpu_pll / (postdiv + 1);
 135
 136 -       ath79_set_clk(ATH79_CLK_REF, ref_rate);
 137         ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
 138         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
 139         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
 140 @@ -362,6 +360,8 @@ static void __init qca953x_clocks_init(v
 141         else
 142                 ref_rate = 25 * 1000 * 1000;
 143
 144 +       ref_rate = ath79_setup_ref_clk(ref_rate);
 145 +
 146         pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
 147         out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 148                   QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
 149 @@ -422,7 +422,6 @@ static void __init qca953x_clocks_init(v
 150         else
 151                 ahb_rate = cpu_pll / (postdiv + 1);
 152
 153 -       ath79_set_clk(ATH79_CLK_REF, ref_rate);
 154         ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
 155         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
 156         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
 157 @@ -444,6 +443,8 @@ static void __init qca955x_clocks_init(v
 158         else
 159                 ref_rate = 25 * 1000 * 1000;
 160
 161 +       ref_rate = ath79_setup_ref_clk(ref_rate);
 162 +
 163         pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
 164         out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 165                   QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
 166 @@ -504,7 +505,6 @@ static void __init qca955x_clocks_init(v
 167         else
 168                 ahb_rate = cpu_pll / (postdiv + 1);
 169
 170 -       ath79_set_clk(ATH79_CLK_REF, ref_rate);
 171         ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
 172         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
 173         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
 174 @@ -526,6 +526,8 @@ static void __init qca956x_clocks_init(v
 175         else
 176                 ref_rate = 25 * 1000 * 1000;
 177
 178 +       ref_rate = ath79_setup_ref_clk(ref_rate);
 179 +
 180         pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
 181         out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 182                   QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
 183 @@ -595,7 +597,6 @@ static void __init qca956x_clocks_init(v
 184         else
 185                 ahb_rate = cpu_pll / (postdiv + 1);
 186
 187 -       ath79_set_clk(ATH79_CLK_REF, ref_rate);
 188         ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
 189         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
 190         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
 191 @@ -671,10 +672,8 @@ static void __init ath79_clocks_init_dt_
 192         void __iomem *pll_base;
 193
 194         ref_clk = of_clk_get(np, 0);
 195 -       if (IS_ERR(ref_clk)) {
 196 -               pr_err("%pOF: of_clk_get failed\n", np);
 197 -               goto err;
 198 -       }
 199 +       if (!IS_ERR(ref_clk))
 200 +               clks[ATH79_CLK_REF] = ref_clk;
 201
 202         pll_base = of_iomap(np, 0);
 203         if (!pll_base) {
 204 @@ -683,9 +682,9 @@ static void __init ath79_clocks_init_dt_
 205         }
 206
 207         if (of_device_is_compatible(np, "qca,ar9130-pll"))
 208 -               ar724x_clk_init(ref_clk, pll_base);
 209 +               ar724x_clocks_init(pll_base);
 210         else if (of_device_is_compatible(np, "qca,ar9330-pll"))
 211 -               ar9330_clk_init(ref_clk, pll_base);
 212 +               ar933x_clocks_init(pll_base);
 213         else {
 214                 pr_err("%pOF: could not find any appropriate clk_init()\n", np);
 215                 goto err_iounmap;
 216 @@ -703,9 +702,6 @@ err_iounmap:
 217
 218  err_clk:
 219         clk_put(ref_clk);
 220 -
 221 -err:
 222 -       return;
 223  }
 224  CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
 225  CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);