package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch

   1 From fd7d9124ffa6761f27747daeea599e0ab874c1fa Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Wed, 19 Jul 2023 17:17:54 +0800
   4 Subject: [PATCH 29/29] board: mediatek: add MT7988 reference boards
   5
   6 This patch adds general board files based on MT7988 SoCs.
   7
   8 MT7988 uses one mmc controller for booting from both SD and eMMC,
   9 and the pins of mmc controller booting from SD are also shared with
  10 one of spi controllers.
  11 So two configs are need for these boot types:
  12
  13 1. mt7988_rfb_defconfig - SPI-NOR, SPI-NAND and eMMC
  14 2. mt7988_sd_rfb_defconfig - SPI-NAND and SD
  15
  16 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  17 ---
  18  arch/arm/dts/Makefile              |   2 +
  19  arch/arm/dts/mt7988-rfb.dts        | 182 +++++++++++++++++++++++++++++
  20  arch/arm/dts/mt7988-sd-rfb.dts     | 134 +++++++++++++++++++++
  21  board/mediatek/mt7988/MAINTAINERS  |   7 ++
  22  board/mediatek/mt7988/Makefile     |   3 +
  23  board/mediatek/mt7988/mt7988_rfb.c |  10 ++
  24  configs/mt7988_rfb_defconfig       |  83 +++++++++++++
  25  configs/mt7988_sd_rfb_defconfig    |  71 +++++++++++
  26  include/configs/mt7988.h           |  14 +++
  27  9 files changed, 506 insertions(+)
  28  create mode 100644 arch/arm/dts/mt7988-rfb.dts
  29  create mode 100644 arch/arm/dts/mt7988-sd-rfb.dts
  30  create mode 100644 board/mediatek/mt7988/MAINTAINERS
  31  create mode 100644 board/mediatek/mt7988/Makefile
  32  create mode 100644 board/mediatek/mt7988/mt7988_rfb.c
  33  create mode 100644 configs/mt7988_rfb_defconfig
  34  create mode 100644 configs/mt7988_sd_rfb_defconfig
  35  create mode 100644 include/configs/mt7988.h
  36
  37 --- a/arch/arm/dts/Makefile
  38 +++ b/arch/arm/dts/Makefile
  39 @@ -1319,6 +1319,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
  40         mt7986b-sd-rfb.dtb \
  41         mt7986a-emmc-rfb.dtb \
  42         mt7986b-emmc-rfb.dtb \
  43 +       mt7988-rfb.dtb \
  44 +       mt7988-sd-rfb.dtb \
  45         mt8183-pumpkin.dtb \
  46         mt8512-bm1-emmc.dtb \
  47         mt8516-pumpkin.dtb \
  48 --- /dev/null
  49 +++ b/arch/arm/dts/mt7988-rfb.dts
  50 @@ -0,0 +1,182 @@
  51 +// SPDX-License-Identifier: GPL-2.0
  52 +/*
  53 + * Copyright (c) 2022 MediaTek Inc.
  54 + * Author: Sam Shih <sam.shih@mediatek.com>
  55 + */
  56 +
  57 +/dts-v1/;
  58 +#include "mt7988.dtsi"
  59 +#include <dt-bindings/gpio/gpio.h>
  60 +
  61 +/ {
  62 +       model = "mt7988-rfb";
  63 +       compatible = "mediatek,mt7988-rfb";
  64 +
  65 +       chosen {
  66 +               stdout-path = &uart0;
  67 +       };
  68 +
  69 +       memory@40000000 {
  70 +               device_type = "memory";
  71 +               reg = <0 0x40000000 0 0x10000000>;
  72 +       };
  73 +
  74 +       reg_3p3v: regulator-3p3v {
  75 +               compatible = "regulator-fixed";
  76 +               regulator-name = "fixed-3.3V";
  77 +               regulator-min-microvolt = <3300000>;
  78 +               regulator-max-microvolt = <3300000>;
  79 +               regulator-boot-on;
  80 +               regulator-always-on;
  81 +       };
  82 +
  83 +       reg_1p8v: regulator-1p8v {
  84 +               compatible = "regulator-fixed";
  85 +               regulator-name = "fixed-1.8V";
  86 +               regulator-min-microvolt = <1800000>;
  87 +               regulator-max-microvolt = <1800000>;
  88 +               regulator-boot-on;
  89 +               regulator-always-on;
  90 +       };
  91 +};
  92 +
  93 +&uart0 {
  94 +       status = "okay";
  95 +};
  96 +
  97 +&i2c1 {
  98 +       pinctrl-names = "default";
  99 +       pinctrl-0 = <&i2c1_pins>;
 100 +       status = "okay";
 101 +};
 102 +
 103 +&eth {
 104 +       status = "okay";
 105 +       mediatek,gmac-id = <0>;
 106 +       phy-mode = "usxgmii";
 107 +       mediatek,switch = "mt7988";
 108 +
 109 +       fixed-link {
 110 +               speed = <1000>;
 111 +               full-duplex;
 112 +               pause;
 113 +       };
 114 +};
 115 +
 116 +&pinctrl {
 117 +       i2c1_pins: i2c1-pins {
 118 +               mux {
 119 +                       function = "i2c";
 120 +                       groups = "i2c1_0";
 121 +               };
 122 +       };
 123 +
 124 +       pwm_pins: pwm-pins {
 125 +               mux {
 126 +                       function = "pwm";
 127 +                       groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
 128 +                                "pwm5", "pwm6", "pwm7";
 129 +               };
 130 +       };
 131 +
 132 +       spi0_pins: spi0-pins {
 133 +               mux {
 134 +                       function = "spi";
 135 +                       groups = "spi0", "spi0_wp_hold";
 136 +               };
 137 +       };
 138 +
 139 +       spi2_pins: spi2-pins {
 140 +               mux {
 141 +                       function = "spi";
 142 +                       groups = "spi2", "spi2_wp_hold";
 143 +               };
 144 +       };
 145 +
 146 +       mmc0_pins_default: mmc0default {
 147 +               mux {
 148 +                       function = "flash";
 149 +                       groups =  "emmc_51";
 150 +               };
 151 +
 152 +               conf-cmd-dat {
 153 +                       pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
 154 +                              "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
 155 +                              "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
 156 +                       input-enable;
 157 +               };
 158 +
 159 +               conf-clk {
 160 +                       pins = "EMMC_CK";
 161 +               };
 162 +
 163 +               conf-dsl {
 164 +                       pins = "EMMC_DSL";
 165 +               };
 166 +
 167 +               conf-rst {
 168 +                       pins = "EMMC_RSTB";
 169 +               };
 170 +       };
 171 +};
 172 +
 173 +&pwm {
 174 +       pinctrl-names = "default";
 175 +       pinctrl-0 = <&pwm_pins>;
 176 +       status = "okay";
 177 +};
 178 +
 179 +&spi0 {
 180 +       pinctrl-names = "default";
 181 +       pinctrl-0 = <&spi0_pins>;
 182 +       #address-cells = <1>;
 183 +       #size-cells = <0>;
 184 +       status = "okay";
 185 +       must_tx;
 186 +       enhance_timing;
 187 +       dma_ext;
 188 +       ipm_design;
 189 +       support_quad;
 190 +       tick_dly = <2>;
 191 +       sample_sel = <0>;
 192 +
 193 +       spi_nand@0 {
 194 +               compatible = "spi-nand";
 195 +               reg = <0>;
 196 +               spi-max-frequency = <52000000>;
 197 +       };
 198 +};
 199 +
 200 +&spi2 {
 201 +       pinctrl-names = "default";
 202 +       pinctrl-0 = <&spi2_pins>;
 203 +       #address-cells = <1>;
 204 +       #size-cells = <0>;
 205 +       status = "okay";
 206 +       must_tx;
 207 +       enhance_timing;
 208 +       dma_ext;
 209 +       ipm_design;
 210 +       support_quad;
 211 +       tick_dly = <2>;
 212 +       sample_sel = <0>;
 213 +
 214 +       spi_nor@0 {
 215 +               compatible = "jedec,spi-nor";
 216 +               reg = <0>;
 217 +               spi-max-frequency = <52000000>;
 218 +       };
 219 +};
 220 +
 221 +&mmc0 {
 222 +       pinctrl-names = "default";
 223 +       pinctrl-0 = <&mmc0_pins_default>;
 224 +       max-frequency = <52000000>;
 225 +       bus-width = <8>;
 226 +       cap-mmc-highspeed;
 227 +       cap-mmc-hw-reset;
 228 +       vmmc-supply = <&reg_3p3v>;
 229 +       vqmmc-supply = <&reg_1p8v>;
 230 +       non-removable;
 231 +       status = "okay";
 232 +};
 233 --- /dev/null
 234 +++ b/arch/arm/dts/mt7988-sd-rfb.dts
 235 @@ -0,0 +1,134 @@
 236 +// SPDX-License-Identifier: GPL-2.0
 237 +/*
 238 + * Copyright (c) 2022 MediaTek Inc.
 239 + * Author: Sam Shih <sam.shih@mediatek.com>
 240 + */
 241 +
 242 +/dts-v1/;
 243 +#include "mt7988.dtsi"
 244 +#include <dt-bindings/gpio/gpio.h>
 245 +
 246 +/ {
 247 +       model = "mt7988-rfb";
 248 +       compatible = "mediatek,mt7988-rfb", "mediatek,mt7988-sd-rfb";
 249 +
 250 +       chosen {
 251 +               stdout-path = &uart0;
 252 +       };
 253 +
 254 +       memory@40000000 {
 255 +               device_type = "memory";
 256 +               reg = <0 0x40000000 0 0x10000000>;
 257 +       };
 258 +
 259 +       reg_3p3v: regulator-3p3v {
 260 +               compatible = "regulator-fixed";
 261 +               regulator-name = "fixed-3.3V";
 262 +               regulator-min-microvolt = <3300000>;
 263 +               regulator-max-microvolt = <3300000>;
 264 +               regulator-boot-on;
 265 +               regulator-always-on;
 266 +       };
 267 +};
 268 +
 269 +&uart0 {
 270 +       status = "okay";
 271 +};
 272 +
 273 +&i2c1 {
 274 +       pinctrl-names = "default";
 275 +       pinctrl-0 = <&i2c1_pins>;
 276 +       status = "okay";
 277 +};
 278 +
 279 +&eth {
 280 +       status = "okay";
 281 +       mediatek,gmac-id = <0>;
 282 +       phy-mode = "usxgmii";
 283 +       mediatek,switch = "mt7988";
 284 +
 285 +       fixed-link {
 286 +               speed = <1000>;
 287 +               full-duplex;
 288 +               pause;
 289 +       };
 290 +};
 291 +
 292 +&pinctrl {
 293 +       i2c1_pins: i2c1-pins {
 294 +               mux {
 295 +                       function = "i2c";
 296 +                       groups = "i2c1_0";
 297 +               };
 298 +       };
 299 +
 300 +       pwm_pins: pwm-pins {
 301 +               mux {
 302 +                       function = "pwm";
 303 +                       groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
 304 +                                "pwm5", "pwm6", "pwm7";
 305 +               };
 306 +       };
 307 +
 308 +       spi0_pins: spi0-pins {
 309 +               mux {
 310 +                       function = "spi";
 311 +                       groups = "spi0", "spi0_wp_hold";
 312 +               };
 313 +       };
 314 +
 315 +       mmc1_pins_default: mmc1default {
 316 +               mux {
 317 +                       function = "flash";
 318 +                       groups =  "emmc_45";
 319 +               };
 320 +
 321 +               conf-cmd-dat {
 322 +                       pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI",
 323 +                              "SPI2_CLK", "SPI2_HOLD";
 324 +                       input-enable;
 325 +               };
 326 +
 327 +               conf-clk {
 328 +                       pins = "SPI2_WP";
 329 +               };
 330 +       };
 331 +};
 332 +
 333 +&pwm {
 334 +       pinctrl-names = "default";
 335 +       pinctrl-0 = <&pwm_pins>;
 336 +       status = "okay";
 337 +};
 338 +
 339 +&spi0 {
 340 +       pinctrl-names = "default";
 341 +       pinctrl-0 = <&spi0_pins>;
 342 +       #address-cells = <1>;
 343 +       #size-cells = <0>;
 344 +       status = "okay";
 345 +       must_tx;
 346 +       enhance_timing;
 347 +       dma_ext;
 348 +       ipm_design;
 349 +       support_quad;
 350 +       tick_dly = <2>;
 351 +       sample_sel = <0>;
 352 +
 353 +       spi_nand@0 {
 354 +               compatible = "spi-nand";
 355 +               reg = <0>;
 356 +               spi-max-frequency = <52000000>;
 357 +       };
 358 +};
 359 +
 360 +&mmc0 {
 361 +       pinctrl-names = "default";
 362 +       pinctrl-0 = <&mmc1_pins_default>;
 363 +       max-frequency = <52000000>;
 364 +       bus-width = <4>;
 365 +       cap-sd-highspeed;
 366 +       vmmc-supply = <&reg_3p3v>;
 367 +       vqmmc-supply = <&reg_3p3v>;
 368 +       status = "okay";
 369 +};
 370 --- /dev/null
 371 +++ b/board/mediatek/mt7988/MAINTAINERS
 372 @@ -0,0 +1,7 @@
 373 +MT7988
 374 +M:     Sam Shih <sam.shih@mediatek.com>
 375 +S:     Maintained
 376 +F:     board/mediatek/mt7988
 377 +F:     include/configs/mt7988.h
 378 +F:     configs/mt7988_rfb_defconfig
 379 +F:     configs/mt7988_sd_rfb_defconfig
 380 --- /dev/null
 381 +++ b/board/mediatek/mt7988/Makefile
 382 @@ -0,0 +1,3 @@
 383 +# SPDX-License-Identifier:     GPL-2.0
 384 +
 385 +obj-y  += mt7988_rfb.o
 386 --- /dev/null
 387 +++ b/board/mediatek/mt7988/mt7988_rfb.c
 388 @@ -0,0 +1,10 @@
 389 +// SPDX-License-Identifier: GPL-2.0
 390 +/*
 391 + * Copyright (C) 2022 MediaTek Inc.
 392 + * Author: Sam Shih <sam.shih@mediatek.com>
 393 + */
 394 +
 395 +int board_init(void)
 396 +{
 397 +       return 0;
 398 +}
 399 --- /dev/null
 400 +++ b/configs/mt7988_rfb_defconfig
 401 @@ -0,0 +1,83 @@
 402 +CONFIG_ARM=y
 403 +CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 404 +CONFIG_POSITION_INDEPENDENT=y
 405 +CONFIG_ARCH_MEDIATEK=y
 406 +CONFIG_TEXT_BASE=0x41e00000
 407 +CONFIG_SYS_MALLOC_F_LEN=0x4000
 408 +CONFIG_NR_DRAM_BANKS=1
 409 +CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb"
 410 +CONFIG_SYS_PROMPT="MT7988> "
 411 +CONFIG_TARGET_MT7988=y
 412 +CONFIG_DEBUG_UART_BASE=0x11000000
 413 +CONFIG_DEBUG_UART_CLOCK=40000000
 414 +CONFIG_SYS_LOAD_ADDR=0x50000000
 415 +CONFIG_DEBUG_UART=y
 416 +# CONFIG_AUTOBOOT is not set
 417 +CONFIG_DEFAULT_FDT_FILE="mt7988-rfb"
 418 +CONFIG_LOGLEVEL=7
 419 +CONFIG_LOG=y
 420 +CONFIG_SYS_CBSIZE=512
 421 +CONFIG_SYS_PBSIZE=1049
 422 +# CONFIG_BOOTM_NETBSD is not set
 423 +# CONFIG_BOOTM_PLAN9 is not set
 424 +# CONFIG_BOOTM_RTEMS is not set
 425 +# CONFIG_BOOTM_VXWORKS is not set
 426 +# CONFIG_CMD_ELF is not set
 427 +CONFIG_CMD_CLK=y
 428 +CONFIG_CMD_DM=y
 429 +CONFIG_CMD_GPIO=y
 430 +CONFIG_CMD_PWM=y
 431 +CONFIG_CMD_MMC=y
 432 +CONFIG_CMD_MTD=y
 433 +CONFIG_CMD_PING=y
 434 +CONFIG_CMD_SMC=y
 435 +CONFIG_DOS_PARTITION=y
 436 +CONFIG_EFI_PARTITION=y
 437 +CONFIG_PARTITION_TYPE_GUID=y
 438 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 439 +CONFIG_NET_RANDOM_ETHADDR=y
 440 +CONFIG_USE_IPADDR=y
 441 +CONFIG_IPADDR="192.168.1.1"
 442 +CONFIG_USE_NETMASK=y
 443 +CONFIG_NETMASK="255.255.255.0"
 444 +CONFIG_USE_SERVERIP=y
 445 +CONFIG_SERVERIP="192.168.1.2"
 446 +CONFIG_PROT_TCP=y
 447 +CONFIG_REGMAP=y
 448 +CONFIG_SYSCON=y
 449 +CONFIG_CLK=y
 450 +CONFIG_MMC_HS200_SUPPORT=y
 451 +CONFIG_MMC_MTK=y
 452 +CONFIG_MTD=y
 453 +CONFIG_DM_MTD=y
 454 +CONFIG_MTD_SPI_NAND=y
 455 +CONFIG_DM_SPI_FLASH=y
 456 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 457 +CONFIG_SPI_FLASH_EON=y
 458 +CONFIG_SPI_FLASH_GIGADEVICE=y
 459 +CONFIG_SPI_FLASH_ISSI=y
 460 +CONFIG_SPI_FLASH_MACRONIX=y
 461 +CONFIG_SPI_FLASH_SPANSION=y
 462 +CONFIG_SPI_FLASH_STMICRO=y
 463 +CONFIG_SPI_FLASH_WINBOND=y
 464 +CONFIG_SPI_FLASH_XMC=y
 465 +CONFIG_SPI_FLASH_XTX=y
 466 +CONFIG_SPI_FLASH_MTD=y
 467 +CONFIG_PHY_FIXED=y
 468 +CONFIG_MEDIATEK_ETH=y
 469 +CONFIG_PINCTRL=y
 470 +CONFIG_PINCONF=y
 471 +CONFIG_PINCTRL_MT7988=y
 472 +CONFIG_POWER_DOMAIN=y
 473 +CONFIG_MTK_POWER_DOMAIN=y
 474 +CONFIG_DM_PWM=y
 475 +CONFIG_PWM_MTK=y
 476 +CONFIG_RAM=y
 477 +CONFIG_DM_SERIAL=y
 478 +CONFIG_MTK_SERIAL=y
 479 +CONFIG_SPI=y
 480 +CONFIG_DM_SPI=y
 481 +CONFIG_MTK_SPIM=y
 482 +CONFIG_LZO=y
 483 +CONFIG_HEXDUMP=y
 484 +# CONFIG_EFI_LOADER is not set
 485 --- /dev/null
 486 +++ b/configs/mt7988_sd_rfb_defconfig
 487 @@ -0,0 +1,71 @@
 488 +CONFIG_ARM=y
 489 +CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 490 +CONFIG_POSITION_INDEPENDENT=y
 491 +CONFIG_ARCH_MEDIATEK=y
 492 +CONFIG_TEXT_BASE=0x41e00000
 493 +CONFIG_SYS_MALLOC_F_LEN=0x4000
 494 +CONFIG_NR_DRAM_BANKS=1
 495 +CONFIG_DEFAULT_DEVICE_TREE="mt7988-sd-rfb"
 496 +CONFIG_SYS_PROMPT="MT7988> "
 497 +CONFIG_TARGET_MT7988=y
 498 +CONFIG_DEBUG_UART_BASE=0x11000000
 499 +CONFIG_DEBUG_UART_CLOCK=40000000
 500 +CONFIG_SYS_LOAD_ADDR=0x50000000
 501 +CONFIG_DEBUG_UART=y
 502 +# CONFIG_AUTOBOOT is not set
 503 +CONFIG_DEFAULT_FDT_FILE="mt7988-sd-rfb"
 504 +CONFIG_LOGLEVEL=7
 505 +CONFIG_LOG=y
 506 +CONFIG_SYS_CBSIZE=512
 507 +CONFIG_SYS_PBSIZE=1049
 508 +# CONFIG_BOOTM_NETBSD is not set
 509 +# CONFIG_BOOTM_PLAN9 is not set
 510 +# CONFIG_BOOTM_RTEMS is not set
 511 +# CONFIG_BOOTM_VXWORKS is not set
 512 +# CONFIG_CMD_ELF is not set
 513 +CONFIG_CMD_CLK=y
 514 +CONFIG_CMD_DM=y
 515 +CONFIG_CMD_GPIO=y
 516 +CONFIG_CMD_PWM=y
 517 +CONFIG_CMD_MMC=y
 518 +CONFIG_CMD_MTD=y
 519 +CONFIG_CMD_PING=y
 520 +CONFIG_CMD_SMC=y
 521 +CONFIG_DOS_PARTITION=y
 522 +CONFIG_EFI_PARTITION=y
 523 +CONFIG_PARTITION_TYPE_GUID=y
 524 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 525 +CONFIG_NET_RANDOM_ETHADDR=y
 526 +CONFIG_USE_IPADDR=y
 527 +CONFIG_IPADDR="192.168.1.1"
 528 +CONFIG_USE_NETMASK=y
 529 +CONFIG_NETMASK="255.255.255.0"
 530 +CONFIG_USE_SERVERIP=y
 531 +CONFIG_SERVERIP="192.168.1.2"
 532 +CONFIG_PROT_TCP=y
 533 +CONFIG_REGMAP=y
 534 +CONFIG_SYSCON=y
 535 +CONFIG_CLK=y
 536 +CONFIG_MMC_HS200_SUPPORT=y
 537 +CONFIG_MMC_MTK=y
 538 +CONFIG_MTD=y
 539 +CONFIG_DM_MTD=y
 540 +CONFIG_MTD_SPI_NAND=y
 541 +CONFIG_PHY_FIXED=y
 542 +CONFIG_MEDIATEK_ETH=y
 543 +CONFIG_PINCTRL=y
 544 +CONFIG_PINCONF=y
 545 +CONFIG_PINCTRL_MT7988=y
 546 +CONFIG_POWER_DOMAIN=y
 547 +CONFIG_MTK_POWER_DOMAIN=y
 548 +CONFIG_DM_PWM=y
 549 +CONFIG_PWM_MTK=y
 550 +CONFIG_RAM=y
 551 +CONFIG_DM_SERIAL=y
 552 +CONFIG_MTK_SERIAL=y
 553 +CONFIG_SPI=y
 554 +CONFIG_DM_SPI=y
 555 +CONFIG_MTK_SPIM=y
 556 +CONFIG_LZO=y
 557 +CONFIG_HEXDUMP=y
 558 +# CONFIG_EFI_LOADER is not set
 559 --- /dev/null
 560 +++ b/include/configs/mt7988.h
 561 @@ -0,0 +1,14 @@
 562 +/* SPDX-License-Identifier: GPL-2.0 */
 563 +/*
 564 + * Configuration for MediaTek MT7988 SoC
 565 + *
 566 + * Copyright (C) 2022 MediaTek Inc.
 567 + * Author: Sam Shih <sam.shih@mediatek.com>
 568 + */
 569 +
 570 +#ifndef __MT7988_H
 571 +#define __MT7988_H
 572 +
 573 +#define CFG_MAX_MEM_MAPPED             0xC0000000
 574 +
 575 +#endif