package/boot/uboot-mediatek/patches/101-20-net-mediatek-add-support-for-SGMII-1Gbps-auto-negoti.patch

   1 From 8e59c3cc700a6efb8db574f3c8e18b6181b4a07d Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Wed, 19 Jul 2023 17:17:13 +0800
   4 Subject: [PATCH 20/29] net: mediatek: add support for SGMII 1Gbps
   5  auto-negotiation mode
   6
   7 Existing SGMII support of mtk-eth is actually a MediaTek-specific
   8 2.5Gbps high-speed SGMII (HSGMII) which does not support
   9 auto-negotiation mode.
  10
  11 This patch adds SGMII 1Gbps auto-negotiation mode and rename the
  12 existing HSGMII to 2500basex.
  13
  14 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  15 ---
  16  drivers/net/mtk_eth.c | 46 +++++++++++++++++++++++++++++++++++++------
  17  drivers/net/mtk_eth.h |  2 ++
  18  2 files changed, 42 insertions(+), 6 deletions(-)
  19
  20 --- a/drivers/net/mtk_eth.c
  21 +++ b/drivers/net/mtk_eth.c
  22 @@ -893,7 +893,7 @@ static int mt7531_setup(struct mtk_eth_p
  23                 if (!port5_sgmii)
  24                         mt7531_port_rgmii_init(priv, 5);
  25                 break;
  26 -       case PHY_INTERFACE_MODE_SGMII:
  27 +       case PHY_INTERFACE_MODE_2500BASEX:
  28                 mt7531_port_sgmii_init(priv, 6);
  29                 if (port5_sgmii)
  30                         mt7531_port_sgmii_init(priv, 5);
  31 @@ -986,6 +986,7 @@ static void mtk_phy_link_adjust(struct m
  32               (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) |
  33               MAC_MODE | FORCE_MODE |
  34               MAC_TX_EN | MAC_RX_EN |
  35 +             DEL_RXFIFO_CLR |
  36               BKOFF_EN | BACKPR_EN;
  37
  38         switch (priv->phydev->speed) {
  39 @@ -996,6 +997,7 @@ static void mtk_phy_link_adjust(struct m
  40                 mcr |= (SPEED_100M << FORCE_SPD_S);
  41                 break;
  42         case SPEED_1000:
  43 +       case SPEED_2500:
  44                 mcr |= (SPEED_1000M << FORCE_SPD_S);
  45                 break;
  46         };
  47 @@ -1048,7 +1050,8 @@ static int mtk_phy_start(struct mtk_eth_
  48                 return 0;
  49         }
  50
  51 -       mtk_phy_link_adjust(priv);
  52 +       if (!priv->force_mode)
  53 +               mtk_phy_link_adjust(priv);
  54
  55         debug("Speed: %d, %s duplex%s\n", phydev->speed,
  56               (phydev->duplex) ? "full" : "half",
  57 @@ -1076,7 +1079,31 @@ static int mtk_phy_probe(struct udevice
  58         return 0;
  59  }
  60
  61 -static void mtk_sgmii_init(struct mtk_eth_priv *priv)
  62 +static void mtk_sgmii_an_init(struct mtk_eth_priv *priv)
  63 +{
  64 +       /* Set SGMII GEN1 speed(1G) */
  65 +       clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
  66 +                       SGMSYS_SPEED_2500, 0);
  67 +
  68 +       /* Enable SGMII AN */
  69 +       setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
  70 +                    SGMII_AN_ENABLE);
  71 +
  72 +       /* SGMII AN mode setting */
  73 +       writel(SGMII_AN_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE);
  74 +
  75 +       /* SGMII PN SWAP setting */
  76 +       if (priv->pn_swap) {
  77 +               setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL,
  78 +                            SGMII_PN_SWAP_TX_RX);
  79 +       }
  80 +
  81 +       /* Release PHYA power down state */
  82 +       clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL,
  83 +                       SGMII_PHYA_PWD, 0);
  84 +}
  85 +
  86 +static void mtk_sgmii_force_init(struct mtk_eth_priv *priv)
  87  {
  88         /* Set SGMII GEN2 speed(2.5G) */
  89         setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
  90 @@ -1111,10 +1138,14 @@ static void mtk_mac_init(struct mtk_eth_
  91                 ge_mode = GE_MODE_RGMII;
  92                 break;
  93         case PHY_INTERFACE_MODE_SGMII:
  94 +       case PHY_INTERFACE_MODE_2500BASEX:
  95                 ge_mode = GE_MODE_RGMII;
  96                 mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
  97                                SYSCFG0_SGMII_SEL(priv->gmac_id));
  98 -               mtk_sgmii_init(priv);
  99 +               if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
 100 +                       mtk_sgmii_an_init(priv);
 101 +               else
 102 +                       mtk_sgmii_force_init(priv);
 103                 break;
 104         case PHY_INTERFACE_MODE_MII:
 105         case PHY_INTERFACE_MODE_GMII:
 106 @@ -1148,6 +1179,7 @@ static void mtk_mac_init(struct mtk_eth_
 107                         mcr |= SPEED_100M << FORCE_SPD_S;
 108                         break;
 109                 case SPEED_1000:
 110 +               case SPEED_2500:
 111                         mcr |= SPEED_1000M << FORCE_SPD_S;
 112                         break;
 113                 }
 114 @@ -1490,13 +1522,15 @@ static int mtk_eth_of_to_plat(struct ude
 115                 priv->duplex = ofnode_read_bool(subnode, "full-duplex");
 116
 117                 if (priv->speed != SPEED_10 && priv->speed != SPEED_100 &&
 118 -                   priv->speed != SPEED_1000) {
 119 +                   priv->speed != SPEED_1000 && priv->speed != SPEED_2500 &&
 120 +                   priv->speed != SPEED_10000) {
 121                         printf("error: no valid speed set in fixed-link\n");
 122                         return -EINVAL;
 123                 }
 124         }
 125
 126 -       if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) {
 127 +       if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII ||
 128 +           priv->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
 129                 /* get corresponding sgmii phandle */
 130                 ret = dev_read_phandle_with_args(dev, "mediatek,sgmiisys",
 131                                                  NULL, 0, 0, &args);
 132 --- a/drivers/net/mtk_eth.h
 133 +++ b/drivers/net/mtk_eth.h
 134 @@ -69,6 +69,7 @@ enum mkt_eth_capabilities {
 135  #define SGMII_AN_RESTART               BIT(9)
 136
 137  #define SGMSYS_SGMII_MODE              0x20
 138 +#define SGMII_AN_MODE                  0x31120103
 139  #define SGMII_FORCE_MODE               0x31120019
 140
 141  #define SGMSYS_QPHY_PWR_STATE_CTRL     0xe8
 142 @@ -168,6 +169,7 @@ enum mkt_eth_capabilities {
 143  #define FORCE_MODE                     BIT(15)
 144  #define MAC_TX_EN                      BIT(14)
 145  #define MAC_RX_EN                      BIT(13)
 146 +#define DEL_RXFIFO_CLR                 BIT(12)
 147  #define BKOFF_EN                       BIT(9)
 148  #define BACKPR_EN                      BIT(8)
 149  #define FORCE_RX_FC                    BIT(5)