package/boot/uboot-mediatek/patches/101-15-pinctrl-mediatek-add-pinctrl-driver-for-MT7988-SoC.patch

   1 From 5e821f4ebd9da4ccf3c8871e402996f6a6eb8d1c Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Wed, 19 Jul 2023 17:16:50 +0800
   4 Subject: [PATCH 15/29] pinctrl: mediatek: add pinctrl driver for MT7988 SoC
   5
   6 This patch adds pinctrl and gpio support for MT7988 SoC
   7
   8 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
   9 ---
  10  drivers/pinctrl/mediatek/Kconfig          |    4 +
  11  drivers/pinctrl/mediatek/Makefile         |    1 +
  12  drivers/pinctrl/mediatek/pinctrl-mt7988.c | 1274 +++++++++++++++++++++
  13  3 files changed, 1279 insertions(+)
  14  create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7988.c
  15
  16 --- a/drivers/pinctrl/mediatek/Kconfig
  17 +++ b/drivers/pinctrl/mediatek/Kconfig
  18 @@ -24,6 +24,10 @@ config PINCTRL_MT7986
  19         bool "MT7986 SoC pinctrl driver"
  20         select PINCTRL_MTK
  21
  22 +config PINCTRL_MT7988
  23 +       bool "MT7988 SoC pinctrl driver"
  24 +       select PINCTRL_MTK
  25 +
  26  config PINCTRL_MT8512
  27         bool "MT8512 SoC pinctrl driver"
  28         select PINCTRL_MTK
  29 --- a/drivers/pinctrl/mediatek/Makefile
  30 +++ b/drivers/pinctrl/mediatek/Makefile
  31 @@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-
  32  obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
  33  obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
  34  obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
  35 +obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o
  36  obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o
  37  obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
  38  obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o
  39 --- /dev/null
  40 +++ b/drivers/pinctrl/mediatek/pinctrl-mt7988.c
  41 @@ -0,0 +1,1274 @@
  42 +// SPDX-License-Identifier: GPL-2.0
  43 +/*
  44 + * Copyright (C) 2022 MediaTek Inc.
  45 + * Author: Sam Shih <sam.shih@mediatek.com>
  46 + */
  47 +
  48 +#include <dm.h>
  49 +#include "pinctrl-mtk-common.h"
  50 +
  51 +enum MT7988_PINCTRL_REG_PAGE {
  52 +       GPIO_BASE,
  53 +       IOCFG_TR_BASE,
  54 +       IOCFG_BR_BASE,
  55 +       IOCFG_RB_BASE,
  56 +       IOCFG_LB_BASE,
  57 +       IOCFG_TL_BASE,
  58 +};
  59 +
  60 +#define MT7988_TYPE0_PIN(_number, _name)                                       \
  61 +       MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0)
  62 +
  63 +#define MT7988_TYPE1_PIN(_number, _name)                                       \
  64 +       MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1)
  65 +
  66 +#define MT7988_TYPE2_PIN(_number, _name)                                       \
  67 +       MTK_TYPED_PIN(_number, _name, DRV_FIXED, IO_TYPE_GRP2)
  68 +
  69 +#define PIN_FIELD_GPIO(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)     \
  70 +       PIN_FIELD_BASE_CALC(_s_pin, _e_pin, GPIO_BASE, _s_addr, _x_addrs,      \
  71 +                           _s_bit, _x_bits, 32, 0)
  72 +
  73 +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,     \
  74 +                      _x_bits)                                                \
  75 +       PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs,        \
  76 +                           _s_bit, _x_bits, 32, 0)
  77 +
  78 +#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,    \
  79 +                       _x_bits)                                               \
  80 +       PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs,        \
  81 +                           _s_bit, _x_bits, 32, 1)
  82 +
  83 +static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = {
  84 +       PIN_FIELD_GPIO(0, 83, 0x300, 0x10, 0, 4),
  85 +};
  86 +
  87 +static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = {
  88 +       PIN_FIELD_GPIO(0, 83, 0x0, 0x10, 0, 1),
  89 +};
  90 +
  91 +static const struct mtk_pin_field_calc mt7988_pin_di_range[] = {
  92 +       PIN_FIELD_GPIO(0, 83, 0x200, 0x10, 0, 1),
  93 +};
  94 +
  95 +static const struct mtk_pin_field_calc mt7988_pin_do_range[] = {
  96 +       PIN_FIELD_GPIO(0, 83, 0x100, 0x10, 0, 1),
  97 +};
  98 +
  99 +static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
 100 +       PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x30, 0x10, 13, 1),
 101 +       PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x30, 0x10, 14, 1),
 102 +       PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x30, 0x10, 11, 1),
 103 +       PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x30, 0x10, 12, 1),
 104 +       PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x30, 0x10, 0, 1),
 105 +       PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x30, 0x10, 9, 1),
 106 +       PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x30, 0x10, 10, 1),
 107 +
 108 +       PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x30, 0x10, 8, 1),
 109 +       PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x30, 0x10, 6, 1),
 110 +       PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x30, 0x10, 5, 1),
 111 +       PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x30, 0x10, 3, 1),
 112 +
 113 +       PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x40, 0x10, 0, 1),
 114 +       PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x40, 0x10, 21, 1),
 115 +       PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x40, 0x10, 1, 1),
 116 +       PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x40, 0x10, 2, 1),
 117 +
 118 +       PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0x30, 0x10, 7, 1),
 119 +       PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0x30, 0x10, 8, 1),
 120 +       PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0x30, 0x10, 3, 1),
 121 +       PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0x30, 0x10, 4, 1),
 122 +
 123 +       PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x30, 0x10, 7, 1),
 124 +       PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x30, 0x10, 4, 1),
 125 +
 126 +       PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x50, 0x10, 17, 1),
 127 +       PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x50, 0x10, 23, 1),
 128 +       PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x50, 0x10, 20, 1),
 129 +       PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x50, 0x10, 19, 1),
 130 +       PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x50, 0x10, 21, 1),
 131 +       PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x50, 0x10, 22, 1),
 132 +       PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x50, 0x10, 18, 1),
 133 +       PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x50, 0x10, 25, 1),
 134 +       PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x50, 0x10, 26, 1),
 135 +       PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x50, 0x10, 27, 1),
 136 +       PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x50, 0x10, 24, 1),
 137 +       PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x50, 0x10, 28, 1),
 138 +       PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x60, 0x10, 0, 1),
 139 +       PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x50, 0x10, 31, 1),
 140 +       PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x50, 0x10, 29, 1),
 141 +       PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x50, 0x10, 30, 1),
 142 +       PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x60, 0x10, 1, 1),
 143 +       PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x50, 0x10, 11, 1),
 144 +       PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x50, 0x10, 10, 1),
 145 +       PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x50, 0x10, 0, 1),
 146 +       PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x50, 0x10, 1, 1),
 147 +       PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x50, 0x10, 9, 1),
 148 +       PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x50, 0x10, 8, 1),
 149 +       PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x50, 0x10, 7, 1),
 150 +       PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x50, 0x10, 6, 1),
 151 +       PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x50, 0x10, 5, 1),
 152 +       PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x50, 0x10, 4, 1),
 153 +       PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x50, 0x10, 3, 1),
 154 +       PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x50, 0x10, 2, 1),
 155 +       PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x50, 0x10, 15, 1),
 156 +       PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x50, 0x10, 12, 1),
 157 +       PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x50, 0x10, 13, 1),
 158 +       PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x50, 0x10, 14, 1),
 159 +       PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x50, 0x10, 16, 1),
 160 +
 161 +       PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x40, 0x10, 14, 1),
 162 +       PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x40, 0x10, 15, 1),
 163 +       PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x40, 0x10, 13, 1),
 164 +       PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x40, 0x10, 4, 1),
 165 +       PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x40, 0x10, 5, 1),
 166 +       PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x40, 0x10, 6, 1),
 167 +       PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x40, 0x10, 3, 1),
 168 +       PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x40, 0x10, 7, 1),
 169 +       PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x40, 0x10, 20, 1),
 170 +       PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x40, 0x10, 8, 1),
 171 +       PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x40, 0x10, 9, 1),
 172 +       PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x40, 0x10, 10, 1),
 173 +       PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x40, 0x10, 11, 1),
 174 +       PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x40, 0x10, 12, 1),
 175 +
 176 +       PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x30, 0x10, 1, 1),
 177 +       PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x30, 0x10, 2, 1),
 178 +       PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0x30, 0x10, 5, 1),
 179 +       PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0x30, 0x10, 6, 1),
 180 +
 181 +       PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x30, 0x10, 10, 1),
 182 +       PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x30, 0x10, 1, 1),
 183 +       PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x30, 0x10, 11, 1),
 184 +       PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x30, 0x10, 9, 1),
 185 +       PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x30, 0x10, 2, 1),
 186 +       PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x30, 0x10, 0, 1),
 187 +       PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x30, 0x10, 12, 1),
 188 +
 189 +       PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x40, 0x10, 18, 1),
 190 +       PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x40, 0x10, 19, 1),
 191 +       PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x40, 0x10, 16, 1),
 192 +       PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x40, 0x10, 17, 1),
 193 +};
 194 +
 195 +static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
 196 +       PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0xc0, 0x10, 13, 1),
 197 +       PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0xc0, 0x10, 14, 1),
 198 +       PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0xc0, 0x10, 11, 1),
 199 +       PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0xc0, 0x10, 12, 1),
 200 +       PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0xc0, 0x10, 0, 1),
 201 +       PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0xc0, 0x10, 9, 1),
 202 +       PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0xc0, 0x10, 10, 1),
 203 +
 204 +       PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0xb0, 0x10, 8, 1),
 205 +       PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0xb0, 0x10, 6, 1),
 206 +       PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0xb0, 0x10, 5, 1),
 207 +       PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0xb0, 0x10, 3, 1),
 208 +
 209 +       PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0xe0, 0x10, 0, 1),
 210 +       PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0xe0, 0x10, 21, 1),
 211 +       PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0xe0, 0x10, 1, 1),
 212 +       PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0xe0, 0x10, 2, 1),
 213 +
 214 +       PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0xc0, 0x10, 7, 1),
 215 +       PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0xc0, 0x10, 8, 1),
 216 +       PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0xc0, 0x10, 3, 1),
 217 +       PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0xc0, 0x10, 4, 1),
 218 +
 219 +       PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0xb0, 0x10, 7, 1),
 220 +       PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0xb0, 0x10, 4, 1),
 221 +
 222 +       PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x140, 0x10, 17, 1),
 223 +       PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x140, 0x10, 23, 1),
 224 +       PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x140, 0x10, 20, 1),
 225 +       PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x140, 0x10, 19, 1),
 226 +       PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x140, 0x10, 21, 1),
 227 +       PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x140, 0x10, 22, 1),
 228 +       PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x140, 0x10, 18, 1),
 229 +       PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x140, 0x10, 25, 1),
 230 +       PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x140, 0x10, 26, 1),
 231 +       PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x140, 0x10, 27, 1),
 232 +       PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x140, 0x10, 24, 1),
 233 +       PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x140, 0x10, 28, 1),
 234 +       PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x150, 0x10, 0, 1),
 235 +       PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x140, 0x10, 31, 1),
 236 +       PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x140, 0x10, 29, 1),
 237 +       PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x140, 0x10, 30, 1),
 238 +       PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x150, 0x10, 1, 1),
 239 +       PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x140, 0x10, 11, 1),
 240 +       PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x140, 0x10, 10, 1),
 241 +       PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x140, 0x10, 0, 1),
 242 +       PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x140, 0x10, 1, 1),
 243 +       PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x140, 0x10, 9, 1),
 244 +       PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x140, 0x10, 8, 1),
 245 +       PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x140, 0x10, 7, 1),
 246 +       PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x140, 0x10, 6, 1),
 247 +       PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x140, 0x10, 5, 1),
 248 +       PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x140, 0x10, 4, 1),
 249 +       PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x140, 0x10, 3, 1),
 250 +       PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x140, 0x10, 2, 1),
 251 +       PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x140, 0x10, 15, 1),
 252 +       PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x140, 0x10, 12, 1),
 253 +       PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x140, 0x10, 13, 1),
 254 +       PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x140, 0x10, 14, 1),
 255 +       PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x140, 0x10, 16, 1),
 256 +
 257 +       PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0xe0, 0x10, 14, 1),
 258 +       PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0xe0, 0x10, 15, 1),
 259 +       PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0xe0, 0x10, 13, 1),
 260 +       PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0xe0, 0x10, 4, 1),
 261 +       PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0xe0, 0x10, 5, 1),
 262 +       PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0xe0, 0x10, 6, 1),
 263 +       PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0xe0, 0x10, 3, 1),
 264 +       PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0xe0, 0x10, 7, 1),
 265 +       PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0xe0, 0x10, 20, 1),
 266 +       PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0xe0, 0x10, 8, 1),
 267 +       PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0xe0, 0x10, 9, 1),
 268 +       PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0xe0, 0x10, 10, 1),
 269 +       PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0xe0, 0x10, 11, 1),
 270 +       PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0xe0, 0x10, 12, 1),
 271 +
 272 +       PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0xc0, 0x10, 1, 1),
 273 +       PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0xc0, 0x10, 2, 1),
 274 +       PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0xc0, 0x10, 5, 1),
 275 +       PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0xc0, 0x10, 6, 1),
 276 +
 277 +       PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0xb0, 0x10, 10, 1),
 278 +       PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0xb0, 0x10, 1, 1),
 279 +       PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0xb0, 0x10, 11, 1),
 280 +       PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0xb0, 0x10, 9, 1),
 281 +       PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0xb0, 0x10, 2, 1),
 282 +       PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0xb0, 0x10, 0, 1),
 283 +       PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0xb0, 0x10, 12, 1),
 284 +
 285 +       PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0xe0, 0x10, 18, 1),
 286 +       PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0xe0, 0x10, 19, 1),
 287 +       PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0xe0, 0x10, 16, 1),
 288 +       PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0xe0, 0x10, 17, 1),
 289 +};
 290 +
 291 +static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
 292 +       PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x60, 0x10, 5, 1),
 293 +       PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x60, 0x10, 4, 1),
 294 +       PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x60, 0x10, 3, 1),
 295 +       PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
 296 +
 297 +       PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x70, 0x10, 0, 1),
 298 +       PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x70, 0x10, 1, 1),
 299 +       PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x70, 0x10, 2, 1),
 300 +
 301 +       PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x60, 0x10, 7, 1),
 302 +       PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x60, 0x10, 6, 1),
 303 +       PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x60, 0x10, 1, 1),
 304 +       PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x60, 0x10, 0, 1),
 305 +       PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x60, 0x10, 8, 1),
 306 +};
 307 +
 308 +static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
 309 +       PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x40, 0x10, 5, 1),
 310 +       PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x40, 0x10, 4, 1),
 311 +       PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x40, 0x10, 3, 1),
 312 +       PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x40, 0x10, 2, 1),
 313 +
 314 +       PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x50, 0x10, 0, 1),
 315 +       PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x50, 0x10, 1, 1),
 316 +
 317 +       PIN_FIELD_BASE(15, 15, IOCFG_TL_BASE, 0x40, 0x10, 4, 1),
 318 +       PIN_FIELD_BASE(16, 16, IOCFG_TL_BASE, 0x40, 0x10, 5, 1),
 319 +       PIN_FIELD_BASE(17, 17, IOCFG_TL_BASE, 0x40, 0x10, 0, 1),
 320 +       PIN_FIELD_BASE(18, 18, IOCFG_TL_BASE, 0x40, 0x10, 1, 1),
 321 +
 322 +       PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x50, 0x10, 2, 1),
 323 +       PIN_FIELD_BASE(71, 71, IOCFG_TL_BASE, 0x40, 0x10, 2, 1),
 324 +       PIN_FIELD_BASE(72, 72, IOCFG_TL_BASE, 0x40, 0x10, 3, 1),
 325 +
 326 +       PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x40, 0x10, 7, 1),
 327 +       PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x40, 0x10, 6, 1),
 328 +       PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x40, 0x10, 1, 1),
 329 +       PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x40, 0x10, 0, 1),
 330 +       PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x40, 0x10, 8, 1),
 331 +};
 332 +
 333 +static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
 334 +       PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x00, 0x10, 21, 3),
 335 +       PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x00, 0x10, 24, 3),
 336 +       PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x00, 0x10, 15, 3),
 337 +       PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x00, 0x10, 18, 3),
 338 +       PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x00, 0x10, 0, 3),
 339 +       PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x00, 0x10, 9, 3),
 340 +       PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x00, 0x10, 12, 3),
 341 +
 342 +       PIN_FIELD_BASE(7, 7, IOCFG_LB_BASE, 0x00, 0x10, 24, 3),
 343 +       PIN_FIELD_BASE(8, 8, IOCFG_LB_BASE, 0x00, 0x10, 28, 3),
 344 +       PIN_FIELD_BASE(9, 9, IOCFG_LB_BASE, 0x00, 0x10, 15, 3),
 345 +       PIN_FIELD_BASE(10, 10, IOCFG_LB_BASE, 0x00, 0x10, 9, 3),
 346 +
 347 +       PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x00, 0x10, 0, 3),
 348 +       PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x20, 0x10, 3, 3),
 349 +       PIN_FIELD_BASE(13, 13, IOCFG_TR_BASE, 0x00, 0x10, 3, 3),
 350 +       PIN_FIELD_BASE(14, 14, IOCFG_TR_BASE, 0x00, 0x10, 6, 3),
 351 +
 352 +       PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x00, 0x10, 21, 3),
 353 +       PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x00, 0x10, 12, 3),
 354 +
 355 +       PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x10, 0x10, 21, 3),
 356 +       PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x20, 0x10, 9, 3),
 357 +       PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x20, 0x10, 0, 3),
 358 +       PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x10, 0x10, 27, 3),
 359 +       PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x20, 0x10, 3, 3),
 360 +       PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x20, 0x10, 6, 3),
 361 +       PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x10, 0x10, 24, 3),
 362 +       PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x20, 0x10, 15, 3),
 363 +       PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x20, 0x10, 18, 3),
 364 +       PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x20, 0x10, 21, 3),
 365 +       PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x20, 0x10, 12, 3),
 366 +       PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x20, 0x10, 24, 3),
 367 +       PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x30, 0x10, 6, 3),
 368 +       PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x30, 0x10, 3, 3),
 369 +       PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x20, 0x10, 27, 3),
 370 +       PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x30, 0x10, 0, 3),
 371 +       PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x30, 0x10, 9, 3),
 372 +       PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x10, 0x10, 3, 3),
 373 +       PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 0, 3),
 374 +       PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x00, 0x10, 0, 3),
 375 +       PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x00, 0x10, 3, 3),
 376 +       PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x00, 0x10, 27, 3),
 377 +       PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x00, 0x10, 24, 3),
 378 +       PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x00, 0x10, 21, 3),
 379 +       PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x00, 0x10, 18, 3),
 380 +       PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x00, 0x10, 15, 3),
 381 +       PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x00, 0x10, 12, 3),
 382 +       PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x00, 0x10, 9, 3),
 383 +       PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x00, 0x10, 6, 3),
 384 +       PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x10, 0x10, 15, 3),
 385 +       PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x10, 0x10, 6, 3),
 386 +       PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x10, 0x10, 9, 3),
 387 +       PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x10, 0x10, 12, 3),
 388 +       PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x10, 0x10, 18, 3),
 389 +
 390 +       PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x10, 0x10, 12, 3),
 391 +       PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x10, 0x10, 15, 3),
 392 +       PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x10, 0x10, 9, 3),
 393 +       PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x00, 0x10, 12, 3),
 394 +       PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x00, 0x10, 15, 3),
 395 +       PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x00, 0x10, 18, 3),
 396 +       PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x00, 0x10, 9, 3),
 397 +       PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x00, 0x10, 21, 3),
 398 +       PIN_FIELD_BASE(63, 63, IOCFG_TR_BASE, 0x20, 0x10, 0, 3),
 399 +       PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x00, 0x10, 24, 3),
 400 +       PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x00, 0x10, 27, 3),
 401 +       PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x10, 0x10, 0, 3),
 402 +       PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x10, 0x10, 3, 3),
 403 +       PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x10, 0x10, 6, 3),
 404 +
 405 +       PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x00, 0x10, 3, 3),
 406 +       PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x00, 0x10, 6, 3),
 407 +
 408 +       PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x10, 0x10, 0, 3),
 409 +       PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x00, 0x10, 3, 3),
 410 +       PIN_FIELD_BASE(75, 75, IOCFG_LB_BASE, 0x10, 0x10, 3, 3),
 411 +       PIN_FIELD_BASE(76, 76, IOCFG_LB_BASE, 0x00, 0x10, 27, 3),
 412 +       PIN_FIELD_BASE(77, 77, IOCFG_LB_BASE, 0x00, 0x10, 6, 3),
 413 +       PIN_FIELD_BASE(78, 78, IOCFG_LB_BASE, 0x00, 0x10, 0, 3),
 414 +       PIN_FIELD_BASE(79, 79, IOCFG_LB_BASE, 0x10, 0x10, 6, 3),
 415 +
 416 +       PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x10, 0x10, 24, 3),
 417 +       PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x10, 0x10, 27, 3),
 418 +       PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x10, 0x10, 18, 3),
 419 +       PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x10, 0x10, 21, 3),
 420 +};
 421 +
 422 +static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
 423 +       PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x50, 0x10, 7, 1),
 424 +       PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
 425 +       PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x50, 0x10, 5, 1),
 426 +       PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x50, 0x10, 6, 1),
 427 +       PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x50, 0x10, 0, 1),
 428 +       PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x50, 0x10, 3, 1),
 429 +       PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x50, 0x10, 4, 1),
 430 +
 431 +       PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x60, 0x10, 0, 1),
 432 +       PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x60, 0x10, 18, 1),
 433 +
 434 +       PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x50, 0x10, 2, 1),
 435 +       PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x50, 0x10, 1, 1),
 436 +
 437 +       PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x70, 0x10, 17, 1),
 438 +       PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x70, 0x10, 23, 1),
 439 +       PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x70, 0x10, 20, 1),
 440 +       PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x70, 0x10, 19, 1),
 441 +       PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x70, 0x10, 21, 1),
 442 +       PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x70, 0x10, 22, 1),
 443 +       PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x70, 0x10, 18, 1),
 444 +       PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x70, 0x10, 25, 1),
 445 +       PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x70, 0x10, 26, 1),
 446 +       PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x70, 0x10, 27, 1),
 447 +       PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x70, 0x10, 24, 1),
 448 +       PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x70, 0x10, 28, 1),
 449 +       PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0x80, 0x10, 0, 1),
 450 +       PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x70, 0x10, 31, 1),
 451 +       PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x70, 0x10, 29, 1),
 452 +       PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x70, 0x10, 30, 1),
 453 +       PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0x80, 0x10, 1, 1),
 454 +       PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x70, 0x10, 11, 1),
 455 +       PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x70, 0x10, 10, 1),
 456 +       PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x70, 0x10, 0, 1),
 457 +       PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 1, 1),
 458 +       PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x70, 0x10, 9, 1),
 459 +       PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x70, 0x10, 8, 1),
 460 +       PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x70, 0x10, 7, 1),
 461 +       PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x70, 0x10, 6, 1),
 462 +       PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x70, 0x10, 5, 1),
 463 +       PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x70, 0x10, 4, 1),
 464 +       PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x70, 0x10, 3, 1),
 465 +       PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x70, 0x10, 2, 1),
 466 +       PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x70, 0x10, 15, 1),
 467 +       PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x70, 0x10, 12, 1),
 468 +       PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x70, 0x10, 13, 1),
 469 +       PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x70, 0x10, 14, 1),
 470 +       PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x70, 0x10, 16, 1),
 471 +
 472 +       PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x60, 0x10, 12, 1),
 473 +       PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x60, 0x10, 13, 1),
 474 +       PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x60, 0x10, 11, 1),
 475 +       PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x60, 0x10, 2, 1),
 476 +       PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x60, 0x10, 3, 1),
 477 +       PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x60, 0x10, 4, 1),
 478 +       PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x60, 0x10, 1, 1),
 479 +       PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x60, 0x10, 5, 1),
 480 +       PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x60, 0x10, 6, 1),
 481 +       PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x60, 0x10, 7, 1),
 482 +       PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x60, 0x10, 8, 1),
 483 +       PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x60, 0x10, 9, 1),
 484 +       PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x60, 0x10, 10, 1),
 485 +
 486 +       PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x50, 0x10, 1, 1),
 487 +       PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x50, 0x10, 2, 1),
 488 +
 489 +       PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x50, 0x10, 3, 1),
 490 +       PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x50, 0x10, 0, 1),
 491 +
 492 +       PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x60, 0x10, 16, 1),
 493 +       PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x60, 0x10, 17, 1),
 494 +       PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x60, 0x10, 14, 1),
 495 +       PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x60, 0x10, 15, 1),
 496 +};
 497 +
 498 +static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
 499 +       PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x60, 0x10, 7, 1),
 500 +       PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x60, 0x10, 8, 1),
 501 +       PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x60, 0x10, 5, 1),
 502 +       PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x60, 0x10, 6, 1),
 503 +       PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x60, 0x10, 0, 1),
 504 +       PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x60, 0x10, 3, 1),
 505 +       PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x60, 0x10, 4, 1),
 506 +
 507 +       PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x80, 0x10, 0, 1),
 508 +       PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x80, 0x10, 18, 1),
 509 +
 510 +       PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x70, 0x10, 2, 1),
 511 +       PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x70, 0x10, 1, 1),
 512 +
 513 +       PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0x90, 0x10, 17, 1),
 514 +       PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0x90, 0x10, 23, 1),
 515 +       PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0x90, 0x10, 20, 1),
 516 +       PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0x90, 0x10, 19, 1),
 517 +       PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0x90, 0x10, 21, 1),
 518 +       PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0x90, 0x10, 22, 1),
 519 +       PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0x90, 0x10, 18, 1),
 520 +       PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0x90, 0x10, 25, 1),
 521 +       PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0x90, 0x10, 26, 1),
 522 +       PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0x90, 0x10, 27, 1),
 523 +       PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0x90, 0x10, 24, 1),
 524 +       PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0x90, 0x10, 28, 1),
 525 +       PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0xa0, 0x10, 0, 1),
 526 +       PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0x90, 0x10, 31, 1),
 527 +       PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0x90, 0x10, 29, 1),
 528 +       PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0x90, 0x10, 30, 1),
 529 +       PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0xa0, 0x10, 1, 1),
 530 +       PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0x90, 0x10, 11, 1),
 531 +       PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x90, 0x10, 10, 1),
 532 +       PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x90, 0x10, 0, 1),
 533 +       PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x90, 0x10, 1, 1),
 534 +       PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x90, 0x10, 9, 1),
 535 +       PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x90, 0x10, 8, 1),
 536 +       PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x90, 0x10, 7, 1),
 537 +       PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x90, 0x10, 6, 1),
 538 +       PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x90, 0x10, 5, 1),
 539 +       PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x90, 0x10, 4, 1),
 540 +       PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x90, 0x10, 3, 1),
 541 +       PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x90, 0x10, 2, 1),
 542 +       PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0x90, 0x10, 15, 1),
 543 +       PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0x90, 0x10, 12, 1),
 544 +       PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0x90, 0x10, 13, 1),
 545 +       PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0x90, 0x10, 14, 1),
 546 +       PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0x90, 0x10, 16, 1),
 547 +
 548 +       PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x80, 0x10, 12, 1),
 549 +       PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x80, 0x10, 13, 1),
 550 +       PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x80, 0x10, 11, 1),
 551 +       PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x80, 0x10, 2, 1),
 552 +       PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x80, 0x10, 3, 1),
 553 +       PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x80, 0x10, 4, 1),
 554 +       PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x80, 0x10, 1, 1),
 555 +       PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x80, 0x10, 5, 1),
 556 +       PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x80, 0x10, 6, 1),
 557 +       PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x80, 0x10, 7, 1),
 558 +       PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x80, 0x10, 8, 1),
 559 +       PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x80, 0x10, 9, 1),
 560 +       PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x80, 0x10, 10, 1),
 561 +
 562 +       PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x60, 0x10, 1, 1),
 563 +       PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x60, 0x10, 2, 1),
 564 +
 565 +       PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x70, 0x10, 3, 1),
 566 +       PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x70, 0x10, 0, 1),
 567 +
 568 +       PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x80, 0x10, 16, 1),
 569 +       PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x80, 0x10, 17, 1),
 570 +       PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x80, 0x10, 14, 1),
 571 +       PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x80, 0x10, 15, 1),
 572 +};
 573 +
 574 +static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
 575 +       PIN_FIELD_BASE(0, 0, IOCFG_TL_BASE, 0x70, 0x10, 7, 1),
 576 +       PIN_FIELD_BASE(1, 1, IOCFG_TL_BASE, 0x70, 0x10, 8, 1),
 577 +       PIN_FIELD_BASE(2, 2, IOCFG_TL_BASE, 0x70, 0x10, 5, 1),
 578 +       PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x70, 0x10, 6, 1),
 579 +       PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x70, 0x10, 0, 1),
 580 +       PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x70, 0x10, 3, 1),
 581 +       PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x70, 0x10, 4, 1),
 582 +
 583 +       PIN_FIELD_BASE(11, 11, IOCFG_TR_BASE, 0x90, 0x10, 0, 1),
 584 +       PIN_FIELD_BASE(12, 12, IOCFG_TR_BASE, 0x90, 0x10, 18, 1),
 585 +
 586 +       PIN_FIELD_BASE(19, 19, IOCFG_LB_BASE, 0x80, 0x10, 2, 1),
 587 +       PIN_FIELD_BASE(20, 20, IOCFG_LB_BASE, 0x80, 0x10, 1, 1),
 588 +
 589 +       PIN_FIELD_BASE(21, 21, IOCFG_RB_BASE, 0xb0, 0x10, 17, 1),
 590 +       PIN_FIELD_BASE(22, 22, IOCFG_RB_BASE, 0xb0, 0x10, 23, 1),
 591 +       PIN_FIELD_BASE(23, 23, IOCFG_RB_BASE, 0xb0, 0x10, 20, 1),
 592 +       PIN_FIELD_BASE(24, 24, IOCFG_RB_BASE, 0xb0, 0x10, 19, 1),
 593 +       PIN_FIELD_BASE(25, 25, IOCFG_RB_BASE, 0xb0, 0x10, 21, 1),
 594 +       PIN_FIELD_BASE(26, 26, IOCFG_RB_BASE, 0xb0, 0x10, 22, 1),
 595 +       PIN_FIELD_BASE(27, 27, IOCFG_RB_BASE, 0xb0, 0x10, 18, 1),
 596 +       PIN_FIELD_BASE(28, 28, IOCFG_RB_BASE, 0xb0, 0x10, 25, 1),
 597 +       PIN_FIELD_BASE(29, 29, IOCFG_RB_BASE, 0xb0, 0x10, 26, 1),
 598 +       PIN_FIELD_BASE(30, 30, IOCFG_RB_BASE, 0xb0, 0x10, 27, 1),
 599 +       PIN_FIELD_BASE(31, 31, IOCFG_RB_BASE, 0xb0, 0x10, 24, 1),
 600 +       PIN_FIELD_BASE(32, 32, IOCFG_RB_BASE, 0xb0, 0x10, 28, 1),
 601 +       PIN_FIELD_BASE(33, 33, IOCFG_RB_BASE, 0xc0, 0x10, 0, 1),
 602 +       PIN_FIELD_BASE(34, 34, IOCFG_RB_BASE, 0xb0, 0x10, 31, 1),
 603 +       PIN_FIELD_BASE(35, 35, IOCFG_RB_BASE, 0xb0, 0x10, 29, 1),
 604 +       PIN_FIELD_BASE(36, 36, IOCFG_RB_BASE, 0xb0, 0x10, 30, 1),
 605 +       PIN_FIELD_BASE(37, 37, IOCFG_RB_BASE, 0xc0, 0x10, 1, 1),
 606 +       PIN_FIELD_BASE(38, 38, IOCFG_RB_BASE, 0xb0, 0x10, 11, 1),
 607 +       PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0xb0, 0x10, 10, 1),
 608 +       PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0xb0, 0x10, 0, 1),
 609 +       PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xb0, 0x10, 1, 1),
 610 +       PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0xb0, 0x10, 9, 1),
 611 +       PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0xb0, 0x10, 8, 1),
 612 +       PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0xb0, 0x10, 7, 1),
 613 +       PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0xb0, 0x10, 6, 1),
 614 +       PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0xb0, 0x10, 5, 1),
 615 +       PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0xb0, 0x10, 4, 1),
 616 +       PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0xb0, 0x10, 3, 1),
 617 +       PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0xb0, 0x10, 2, 1),
 618 +       PIN_FIELD_BASE(50, 50, IOCFG_RB_BASE, 0xb0, 0x10, 15, 1),
 619 +       PIN_FIELD_BASE(51, 51, IOCFG_RB_BASE, 0xb0, 0x10, 12, 1),
 620 +       PIN_FIELD_BASE(52, 52, IOCFG_RB_BASE, 0xb0, 0x10, 13, 1),
 621 +       PIN_FIELD_BASE(53, 53, IOCFG_RB_BASE, 0xb0, 0x10, 14, 1),
 622 +       PIN_FIELD_BASE(54, 54, IOCFG_RB_BASE, 0xb0, 0x10, 16, 1),
 623 +
 624 +       PIN_FIELD_BASE(55, 55, IOCFG_TR_BASE, 0x90, 0x10, 12, 1),
 625 +       PIN_FIELD_BASE(56, 56, IOCFG_TR_BASE, 0x90, 0x10, 13, 1),
 626 +       PIN_FIELD_BASE(57, 57, IOCFG_TR_BASE, 0x90, 0x10, 11, 1),
 627 +       PIN_FIELD_BASE(58, 58, IOCFG_TR_BASE, 0x90, 0x10, 2, 1),
 628 +       PIN_FIELD_BASE(59, 59, IOCFG_TR_BASE, 0x90, 0x10, 3, 1),
 629 +       PIN_FIELD_BASE(60, 60, IOCFG_TR_BASE, 0x90, 0x10, 4, 1),
 630 +       PIN_FIELD_BASE(61, 61, IOCFG_TR_BASE, 0x90, 0x10, 1, 1),
 631 +       PIN_FIELD_BASE(62, 62, IOCFG_TR_BASE, 0x90, 0x10, 5, 1),
 632 +       PIN_FIELD_BASE(64, 64, IOCFG_TR_BASE, 0x90, 0x10, 6, 1),
 633 +       PIN_FIELD_BASE(65, 65, IOCFG_TR_BASE, 0x90, 0x10, 7, 1),
 634 +       PIN_FIELD_BASE(66, 66, IOCFG_TR_BASE, 0x90, 0x10, 8, 1),
 635 +       PIN_FIELD_BASE(67, 67, IOCFG_TR_BASE, 0x90, 0x10, 9, 1),
 636 +       PIN_FIELD_BASE(68, 68, IOCFG_TR_BASE, 0x90, 0x10, 10, 1),
 637 +
 638 +       PIN_FIELD_BASE(69, 69, IOCFG_TL_BASE, 0x70, 0x10, 1, 1),
 639 +       PIN_FIELD_BASE(70, 70, IOCFG_TL_BASE, 0x70, 0x10, 2, 1),
 640 +
 641 +       PIN_FIELD_BASE(73, 73, IOCFG_LB_BASE, 0x80, 0x10, 3, 1),
 642 +       PIN_FIELD_BASE(74, 74, IOCFG_LB_BASE, 0x80, 0x10, 0, 1),
 643 +
 644 +       PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x90, 0x10, 16, 1),
 645 +       PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x90, 0x10, 17, 1),
 646 +       PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x90, 0x10, 14, 1),
 647 +       PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x90, 0x10, 15, 1),
 648 +};
 649 +
 650 +static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
 651 +       [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range),
 652 +       [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range),
 653 +       [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range),
 654 +       [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range),
 655 +       [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range),
 656 +       [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range),
 657 +       [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range),
 658 +       [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range),
 659 +       [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range),
 660 +       [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range),
 661 +       [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range),
 662 +       [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range),
 663 +};
 664 +
 665 +static const struct mtk_pin_desc mt7988_pins[] = {
 666 +       MT7988_TYPE0_PIN(0, "UART2_RXD"),
 667 +       MT7988_TYPE0_PIN(1, "UART2_TXD"),
 668 +       MT7988_TYPE0_PIN(2, "UART2_CTS"),
 669 +       MT7988_TYPE0_PIN(3, "UART2_RTS"),
 670 +       MT7988_TYPE0_PIN(4, "GPIO_A"),
 671 +       MT7988_TYPE0_PIN(5, "SMI_0_MDC"),
 672 +       MT7988_TYPE0_PIN(6, "SMI_0_MDIO"),
 673 +       MT7988_TYPE1_PIN(7, "PCIE30_2L_0_WAKE_N"),
 674 +       MT7988_TYPE1_PIN(8, "PCIE30_2L_0_CLKREQ_N"),
 675 +       MT7988_TYPE1_PIN(9, "PCIE30_1L_1_WAKE_N"),
 676 +       MT7988_TYPE1_PIN(10, "PCIE30_1L_1_CLKREQ_N"),
 677 +       MT7988_TYPE0_PIN(11, "GPIO_P"),
 678 +       MT7988_TYPE0_PIN(12, "WATCHDOG"),
 679 +       MT7988_TYPE1_PIN(13, "GPIO_RESET"),
 680 +       MT7988_TYPE1_PIN(14, "GPIO_WPS"),
 681 +       MT7988_TYPE2_PIN(15, "PMIC_I2C_SCL"),
 682 +       MT7988_TYPE2_PIN(16, "PMIC_I2C_SDA"),
 683 +       MT7988_TYPE2_PIN(17, "I2C_1_SCL"),
 684 +       MT7988_TYPE2_PIN(18, "I2C_1_SDA"),
 685 +       MT7988_TYPE0_PIN(19, "PCIE30_2L_0_PRESET_N"),
 686 +       MT7988_TYPE0_PIN(20, "PCIE30_1L_1_PRESET_N"),
 687 +       MT7988_TYPE0_PIN(21, "PWMD1"),
 688 +       MT7988_TYPE0_PIN(22, "SPI0_WP"),
 689 +       MT7988_TYPE0_PIN(23, "SPI0_HOLD"),
 690 +       MT7988_TYPE0_PIN(24, "SPI0_CSB"),
 691 +       MT7988_TYPE0_PIN(25, "SPI0_MISO"),
 692 +       MT7988_TYPE0_PIN(26, "SPI0_MOSI"),
 693 +       MT7988_TYPE0_PIN(27, "SPI0_CLK"),
 694 +       MT7988_TYPE0_PIN(28, "SPI1_CSB"),
 695 +       MT7988_TYPE0_PIN(29, "SPI1_MISO"),
 696 +       MT7988_TYPE0_PIN(30, "SPI1_MOSI"),
 697 +       MT7988_TYPE0_PIN(31, "SPI1_CLK"),
 698 +       MT7988_TYPE0_PIN(32, "SPI2_CLK"),
 699 +       MT7988_TYPE0_PIN(33, "SPI2_MOSI"),
 700 +       MT7988_TYPE0_PIN(34, "SPI2_MISO"),
 701 +       MT7988_TYPE0_PIN(35, "SPI2_CSB"),
 702 +       MT7988_TYPE0_PIN(36, "SPI2_HOLD"),
 703 +       MT7988_TYPE0_PIN(37, "SPI2_WP"),
 704 +       MT7988_TYPE0_PIN(38, "EMMC_RSTB"),
 705 +       MT7988_TYPE0_PIN(39, "EMMC_DSL"),
 706 +       MT7988_TYPE0_PIN(40, "EMMC_CK"),
 707 +       MT7988_TYPE0_PIN(41, "EMMC_CMD"),
 708 +       MT7988_TYPE0_PIN(42, "EMMC_DATA_7"),
 709 +       MT7988_TYPE0_PIN(43, "EMMC_DATA_6"),
 710 +       MT7988_TYPE0_PIN(44, "EMMC_DATA_5"),
 711 +       MT7988_TYPE0_PIN(45, "EMMC_DATA_4"),
 712 +       MT7988_TYPE0_PIN(46, "EMMC_DATA_3"),
 713 +       MT7988_TYPE0_PIN(47, "EMMC_DATA_2"),
 714 +       MT7988_TYPE0_PIN(48, "EMMC_DATA_1"),
 715 +       MT7988_TYPE0_PIN(49, "EMMC_DATA_0"),
 716 +       MT7988_TYPE0_PIN(50, "PCM_FS_I2S_LRCK"),
 717 +       MT7988_TYPE0_PIN(51, "PCM_CLK_I2S_BCLK"),
 718 +       MT7988_TYPE0_PIN(52, "PCM_DRX_I2S_DIN"),
 719 +       MT7988_TYPE0_PIN(53, "PCM_DTX_I2S_DOUT"),
 720 +       MT7988_TYPE0_PIN(54, "PCM_MCK_I2S_MCLK"),
 721 +       MT7988_TYPE0_PIN(55, "UART0_RXD"),
 722 +       MT7988_TYPE0_PIN(56, "UART0_TXD"),
 723 +       MT7988_TYPE0_PIN(57, "PWMD0"),
 724 +       MT7988_TYPE0_PIN(58, "JTAG_JTDI"),
 725 +       MT7988_TYPE0_PIN(59, "JTAG_JTDO"),
 726 +       MT7988_TYPE0_PIN(60, "JTAG_JTMS"),
 727 +       MT7988_TYPE0_PIN(61, "JTAG_JTCLK"),
 728 +       MT7988_TYPE0_PIN(62, "JTAG_JTRST_N"),
 729 +       MT7988_TYPE1_PIN(63, "USB_DRV_VBUS_P1"),
 730 +       MT7988_TYPE0_PIN(64, "LED_A"),
 731 +       MT7988_TYPE0_PIN(65, "LED_B"),
 732 +       MT7988_TYPE0_PIN(66, "LED_C"),
 733 +       MT7988_TYPE0_PIN(67, "LED_D"),
 734 +       MT7988_TYPE0_PIN(68, "LED_E"),
 735 +       MT7988_TYPE0_PIN(69, "GPIO_B"),
 736 +       MT7988_TYPE0_PIN(70, "GPIO_C"),
 737 +       MT7988_TYPE2_PIN(71, "I2C_2_SCL"),
 738 +       MT7988_TYPE2_PIN(72, "I2C_2_SDA"),
 739 +       MT7988_TYPE0_PIN(73, "PCIE30_2L_1_PRESET_N"),
 740 +       MT7988_TYPE0_PIN(74, "PCIE30_1L_0_PRESET_N"),
 741 +       MT7988_TYPE1_PIN(75, "PCIE30_2L_1_WAKE_N"),
 742 +       MT7988_TYPE1_PIN(76, "PCIE30_2L_1_CLKREQ_N"),
 743 +       MT7988_TYPE1_PIN(77, "PCIE30_1L_0_WAKE_N"),
 744 +       MT7988_TYPE1_PIN(78, "PCIE30_1L_0_CLKREQ_N"),
 745 +       MT7988_TYPE1_PIN(79, "USB_DRV_VBUS_P0"),
 746 +       MT7988_TYPE0_PIN(80, "UART1_RXD"),
 747 +       MT7988_TYPE0_PIN(81, "UART1_TXD"),
 748 +       MT7988_TYPE0_PIN(82, "UART1_CTS"),
 749 +       MT7988_TYPE0_PIN(83, "UART1_RTS"),
 750 +};
 751 +
 752 +/* jtag */
 753 +static const int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 };
 754 +static const int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 };
 755 +
 756 +static const int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 };
 757 +static const int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 };
 758 +
 759 +static const int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 };
 760 +static const int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 };
 761 +
 762 +static const int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 };
 763 +static const int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 };
 764 +
 765 +static const int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 };
 766 +static const int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 };
 767 +
 768 +static const int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 };
 769 +static const int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 };
 770 +
 771 +/* int_usxgmii */
 772 +static const int mt7988_int_usxgmii_pins[] = { 2, 3 };
 773 +static const int mt7988_int_usxgmii_funcs[] = { 3, 3 };
 774 +
 775 +/* pwm */
 776 +static const int mt7988_pwm0_pins[] = { 57 };
 777 +static const int mt7988_pwm0_funcs[] = { 1 };
 778 +
 779 +static const int mt7988_pwm1_pins[] = { 21 };
 780 +static const int mt7988_pwm1_funcs[] = { 1 };
 781 +
 782 +static const int mt7988_pwm2_pins[] = { 80 };
 783 +static const int mt7988_pwm2_funcs[] = { 2 };
 784 +
 785 +static const int mt7988_pwm3_pins[] = { 81 };
 786 +static const int mt7988_pwm3_funcs[] = { 2 };
 787 +
 788 +static const int mt7988_pwm4_pins[] = { 82 };
 789 +static const int mt7988_pwm4_funcs[] = { 2 };
 790 +
 791 +static const int mt7988_pwm5_pins[] = { 83 };
 792 +static const int mt7988_pwm5_funcs[] = { 2 };
 793 +
 794 +static const int mt7988_pwm6_pins[] = { 69 };
 795 +static const int mt7988_pwm6_funcs[] = { 3 };
 796 +
 797 +static const int mt7988_pwm7_pins[] = { 70 };
 798 +static const int mt7988_pwm7_funcs[] = { 3 };
 799 +
 800 +/* dfd */
 801 +static const int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 };
 802 +static const int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 };
 803 +
 804 +/* i2c */
 805 +static const int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 };
 806 +static const int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 };
 807 +
 808 +static const int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 };
 809 +static const int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 };
 810 +
 811 +static const int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 };
 812 +static const int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 };
 813 +
 814 +static const int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 };
 815 +static const int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 };
 816 +
 817 +static const int mt7988_i2c0_0_pins[] = { 5, 6 };
 818 +static const int mt7988_i2c0_0_funcs[] = { 2, 2 };
 819 +
 820 +static const int mt7988_i2c1_sfp_pins[] = { 5, 6 };
 821 +static const int mt7988_i2c1_sfp_funcs[] = { 4, 4 };
 822 +
 823 +static const int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 };
 824 +static const int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 };
 825 +
 826 +static const int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 };
 827 +static const int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 };
 828 +
 829 +static const int mt7988_i2c0_1_pins[] = { 15, 16 };
 830 +static const int mt7988_i2c0_1_funcs[] = { 1, 1 };
 831 +
 832 +static const int mt7988_u30_phy_i2c0_pins[] = { 15, 16 };
 833 +static const int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 };
 834 +
 835 +static const int mt7988_u32_phy_i2c0_pins[] = { 15, 16 };
 836 +static const int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 };
 837 +
 838 +static const int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 };
 839 +static const int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 };
 840 +
 841 +static const int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 };
 842 +static const int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 };
 843 +
 844 +static const int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 };
 845 +static const int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 };
 846 +
 847 +static const int mt7988_i2c1_0_pins[] = { 17, 18 };
 848 +static const int mt7988_i2c1_0_funcs[] = { 1, 1 };
 849 +
 850 +static const int mt7988_u30_phy_i2c1_pins[] = { 17, 18 };
 851 +static const int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 };
 852 +
 853 +static const int mt7988_u32_phy_i2c1_pins[] = { 17, 18 };
 854 +static const int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 };
 855 +
 856 +static const int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 };
 857 +static const int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 };
 858 +
 859 +static const int mt7988_sgmii0_i2c_pins[] = { 17, 18 };
 860 +static const int mt7988_sgmii0_i2c_funcs[] = { 5, 5 };
 861 +
 862 +static const int mt7988_sgmii1_i2c_pins[] = { 17, 18 };
 863 +static const int mt7988_sgmii1_i2c_funcs[] = { 6, 6 };
 864 +
 865 +static const int mt7988_i2c1_2_pins[] = { 69, 70 };
 866 +static const int mt7988_i2c1_2_funcs[] = { 2, 2 };
 867 +
 868 +static const int mt7988_i2c2_0_pins[] = { 69, 70 };
 869 +static const int mt7988_i2c2_0_funcs[] = { 4, 4 };
 870 +
 871 +static const int mt7988_i2c2_1_pins[] = { 71, 72 };
 872 +static const int mt7988_i2c2_1_funcs[] = { 1, 1 };
 873 +
 874 +/* eth */
 875 +static const int mt7988_mdc_mdio0_pins[] = { 5, 6 };
 876 +static const int mt7988_mdc_mdio0_funcs[] = { 1, 1 };
 877 +
 878 +static const int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 };
 879 +static const int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 };
 880 +
 881 +static const int mt7988_gbe_ext_mdio_pins[] = { 30, 31 };
 882 +static const int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 };
 883 +
 884 +static const int mt7988_mdc_mdio1_pins[] = { 69, 70 };
 885 +static const int mt7988_mdc_mdio1_funcs[] = { 1, 1 };
 886 +
 887 +/* pcie */
 888 +static const int mt7988_pcie_wake_n0_0_pins[] = { 7 };
 889 +static const int mt7988_pcie_wake_n0_0_funcs[] = { 1 };
 890 +
 891 +static const int mt7988_pcie_clk_req_n0_0_pins[] = { 8 };
 892 +static const int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 };
 893 +
 894 +static const int mt7988_pcie_wake_n3_0_pins[] = { 9 };
 895 +static const int mt7988_pcie_wake_n3_0_funcs[] = { 1 };
 896 +
 897 +static const int mt7988_pcie_clk_req_n3_pins[] = { 10 };
 898 +static const int mt7988_pcie_clk_req_n3_funcs[] = { 1 };
 899 +
 900 +static const int mt7988_pcie_clk_req_n0_1_pins[] = { 10 };
 901 +static const int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 };
 902 +
 903 +static const int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 };
 904 +static const int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 };
 905 +
 906 +static const int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 };
 907 +static const int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 };
 908 +
 909 +static const int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 };
 910 +static const int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 };
 911 +
 912 +static const int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 };
 913 +static const int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 };
 914 +
 915 +static const int mt7988_ckm_phy_i2c_pins[] = { 9, 10 };
 916 +static const int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 };
 917 +
 918 +static const int mt7988_pcie_wake_n0_1_pins[] = { 13 };
 919 +static const int mt7988_pcie_wake_n0_1_funcs[] = { 2 };
 920 +
 921 +static const int mt7988_pcie_wake_n3_1_pins[] = { 14 };
 922 +static const int mt7988_pcie_wake_n3_1_funcs[] = { 2 };
 923 +
 924 +static const int mt7988_pcie_2l_0_pereset_pins[] = { 19 };
 925 +static const int mt7988_pcie_2l_0_pereset_funcs[] = { 1 };
 926 +
 927 +static const int mt7988_pcie_1l_1_pereset_pins[] = { 20 };
 928 +static const int mt7988_pcie_1l_1_pereset_funcs[] = { 1 };
 929 +
 930 +static const int mt7988_pcie_clk_req_n2_1_pins[] = { 63 };
 931 +static const int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 };
 932 +
 933 +static const int mt7988_pcie_2l_1_pereset_pins[] = { 73 };
 934 +static const int mt7988_pcie_2l_1_pereset_funcs[] = { 1 };
 935 +
 936 +static const int mt7988_pcie_1l_0_pereset_pins[] = { 74 };
 937 +static const int mt7988_pcie_1l_0_pereset_funcs[] = { 1 };
 938 +
 939 +static const int mt7988_pcie_wake_n1_0_pins[] = { 75 };
 940 +static const int mt7988_pcie_wake_n1_0_funcs[] = { 1 };
 941 +
 942 +static const int mt7988_pcie_clk_req_n1_pins[] = { 76 };
 943 +static const int mt7988_pcie_clk_req_n1_funcs[] = { 1 };
 944 +
 945 +static const int mt7988_pcie_wake_n2_0_pins[] = { 77 };
 946 +static const int mt7988_pcie_wake_n2_0_funcs[] = { 1 };
 947 +
 948 +static const int mt7988_pcie_clk_req_n2_0_pins[] = { 78 };
 949 +static const int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 };
 950 +
 951 +static const int mt7988_pcie_wake_n2_1_pins[] = { 79 };
 952 +static const int mt7988_pcie_wake_n2_1_funcs[] = { 2 };
 953 +
 954 +/* pmic */
 955 +static const int mt7988_pmic_pins[] = { 11 };
 956 +static const int mt7988_pmic_funcs[] = { 1 };
 957 +
 958 +/* watchdog */
 959 +static const int mt7988_watchdog_pins[] = { 12 };
 960 +static const int mt7988_watchdog_funcs[] = { 1 };
 961 +
 962 +/* spi */
 963 +static const int mt7988_spi0_wp_hold_pins[] = { 22, 23 };
 964 +static const int mt7988_spi0_wp_hold_funcs[] = { 1, 1 };
 965 +
 966 +static const int mt7988_spi0_pins[] = { 24, 25, 26, 27 };
 967 +static const int mt7988_spi0_funcs[] = { 1, 1, 1, 1 };
 968 +
 969 +static const int mt7988_spi1_pins[] = { 28, 29, 30, 31 };
 970 +static const int mt7988_spi1_funcs[] = { 1, 1, 1, 1 };
 971 +
 972 +static const int mt7988_spi2_pins[] = { 32, 33, 34, 35 };
 973 +static const int mt7988_spi2_funcs[] = { 1, 1, 1, 1 };
 974 +
 975 +static const int mt7988_spi2_wp_hold_pins[] = { 36, 37 };
 976 +static const int mt7988_spi2_wp_hold_funcs[] = { 1, 1 };
 977 +
 978 +/* flash */
 979 +static const int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 };
 980 +static const int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
 981 +
 982 +static const int mt7988_emmc_45_pins[] = {
 983 +       21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 };
 984 +static const int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 };
 985 +
 986 +static const int mt7988_emmc_51_pins[] = {
 987 +       38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49 };
 988 +static const int mt7988_emmc_51_funcs[] = {
 989 +       1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
 990 +
 991 +/* uart */
 992 +static const int mt7988_uart2_pins[] = { 0, 1, 2, 3 };
 993 +static const int mt7988_uart2_funcs[] = { 1, 1, 1, 1 };
 994 +
 995 +static const int mt7988_tops_uart0_0_pins[] = { 22, 23 };
 996 +static const int mt7988_tops_uart0_0_funcs[] = { 3, 3 };
 997 +
 998 +static const int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 };
 999 +static const int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 };
1000 +
1001 +static const int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 };
1002 +static const int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 };
1003 +
1004 +static const int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 };
1005 +static const int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 };
1006 +
1007 +static const int mt7988_net_wo0_uart_txd_0_pins[] = { 28 };
1008 +static const int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 };
1009 +
1010 +static const int mt7988_net_wo1_uart_txd_0_pins[] = { 29 };
1011 +static const int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 };
1012 +
1013 +static const int mt7988_net_wo2_uart_txd_0_pins[] = { 30 };
1014 +static const int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 };
1015 +
1016 +static const int mt7988_tops_uart1_0_pins[] = { 28, 29 };
1017 +static const int mt7988_tops_uart1_0_funcs[] = { 4, 4 };
1018 +
1019 +static const int mt7988_tops_uart0_1_pins[] = { 30, 31 };
1020 +static const int mt7988_tops_uart0_1_funcs[] = { 4, 4 };
1021 +
1022 +static const int mt7988_tops_uart1_1_pins[] = { 36, 37 };
1023 +static const int mt7988_tops_uart1_1_funcs[] = { 3, 3 };
1024 +
1025 +static const int mt7988_uart0_pins[] = { 55, 56 };
1026 +static const int mt7988_uart0_funcs[] = { 1, 1 };
1027 +
1028 +static const int mt7988_tops_uart0_2_pins[] = { 55, 56 };
1029 +static const int mt7988_tops_uart0_2_funcs[] = { 2, 2 };
1030 +
1031 +static const int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 };
1032 +static const int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 };
1033 +
1034 +static const int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 };
1035 +static const int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 };
1036 +
1037 +static const int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 };
1038 +static const int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 };
1039 +
1040 +static const int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 };
1041 +static const int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 };
1042 +
1043 +static const int mt7988_tops_uart1_2_pins[] = { 80, 81 };
1044 +static const int mt7988_tops_uart1_2_funcs[] = { 4, 4, };
1045 +
1046 +static const int mt7988_net_wo0_uart_txd_1_pins[] = { 80 };
1047 +static const int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 };
1048 +
1049 +static const int mt7988_net_wo1_uart_txd_1_pins[] = { 81 };
1050 +static const int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 };
1051 +
1052 +static const int mt7988_net_wo2_uart_txd_1_pins[] = { 82 };
1053 +static const int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 };
1054 +
1055 +/* udi */
1056 +static const int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 };
1057 +static const int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 };
1058 +
1059 +/* pcm */
1060 +static const int mt7988_pcm_pins[] = { 50, 51, 52, 53, 54 };
1061 +static const int mt7988_pcm_funcs[] = { 1, 1, 1, 1, 1 };
1062 +
1063 +/* led */
1064 +static const int mt7988_gbe_led1_pins[] = { 58, 59, 60, 61 };
1065 +static const int mt7988_gbe_led1_funcs[] = { 6, 6, 6, 6 };
1066 +
1067 +static const int mt7988_2p5gbe_led1_pins[] = { 62 };
1068 +static const int mt7988_2p5gbe_led1_funcs[] = { 6 };
1069 +
1070 +static const int mt7988_gbe_led0_pins[] = { 64, 65, 66, 67 };
1071 +static const int mt7988_gbe_led0_funcs[] = { 1, 1, 1, 1 };
1072 +
1073 +static const int mt7988_2p5gbe_led0_pins[] = { 68 };
1074 +static const int mt7988_2p5gbe_led0_funcs[] = { 1 };
1075 +
1076 +/* usb */
1077 +static const int mt7988_drv_vbus_p1_pins[] = { 63 };
1078 +static const int mt7988_drv_vbus_p1_funcs[] = { 1 };
1079 +
1080 +static const int mt7988_drv_vbus_pins[] = { 79 };
1081 +static const int mt7988_drv_vbus_funcs[] = { 1 };
1082 +
1083 +static const struct mtk_group_desc mt7988_groups[] = {
1084 +       PINCTRL_PIN_GROUP("uart2", mt7988_uart2),
1085 +       PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0),
1086 +       PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii),
1087 +       PINCTRL_PIN_GROUP("dfd", mt7988_dfd),
1088 +       PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0),
1089 +       PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0),
1090 +       PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0),
1091 +       PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1),
1092 +       PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0),
1093 +       PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp),
1094 +       PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c),
1095 +       PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c),
1096 +       PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0),
1097 +       PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0),
1098 +       PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0),
1099 +       PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0),
1100 +       PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3),
1101 +       PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1),
1102 +       PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c),
1103 +       PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c),
1104 +       PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c),
1105 +       PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c),
1106 +       PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c),
1107 +       PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic),
1108 +       PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog),
1109 +       PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1),
1110 +       PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1),
1111 +       PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1),
1112 +       PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0),
1113 +       PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0),
1114 +       PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1),
1115 +       PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1),
1116 +       PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2),
1117 +       PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0),
1118 +       PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1),
1119 +       PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1),
1120 +       PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3),
1121 +       PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c),
1122 +       PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c),
1123 +       PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset),
1124 +       PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset),
1125 +       PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1),
1126 +       PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold),
1127 +       PINCTRL_PIN_GROUP("spi0", mt7988_spi0),
1128 +       PINCTRL_PIN_GROUP("spi1", mt7988_spi1),
1129 +       PINCTRL_PIN_GROUP("spi2", mt7988_spi2),
1130 +       PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold),
1131 +       PINCTRL_PIN_GROUP("snfi", mt7988_snfi),
1132 +       PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0),
1133 +       PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0),
1134 +       PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0),
1135 +       PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1),
1136 +       PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
1137 +       PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
1138 +       PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
1139 +       PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0),
1140 +       PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1),
1141 +       PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1),
1142 +       PINCTRL_PIN_GROUP("udi", mt7988_udi),
1143 +       PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45),
1144 +       PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51),
1145 +       PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio),
1146 +       PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio),
1147 +       PINCTRL_PIN_GROUP("pcm", mt7988_pcm),
1148 +       PINCTRL_PIN_GROUP("uart0", mt7988_uart0),
1149 +       PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2),
1150 +       PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2),
1151 +       PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag),
1152 +       PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag),
1153 +       PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag),
1154 +       PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0),
1155 +       PINCTRL_PIN_GROUP("jtag", mt7988_jtag),
1156 +       PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1),
1157 +       PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3),
1158 +       PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1),
1159 +       PINCTRL_PIN_GROUP("gbe_led1", mt7988_gbe_led1),
1160 +       PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1),
1161 +       PINCTRL_PIN_GROUP("gbe_led0", mt7988_gbe_led0),
1162 +       PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0),
1163 +       PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1),
1164 +       PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1),
1165 +       PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1),
1166 +       PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2),
1167 +       PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6),
1168 +       PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7),
1169 +       PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0),
1170 +       PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1),
1171 +       PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset),
1172 +       PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset),
1173 +       PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0),
1174 +       PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1),
1175 +       PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0),
1176 +       PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0),
1177 +       PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus),
1178 +       PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1),
1179 +       PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2),
1180 +       PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2),
1181 +       PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3),
1182 +       PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4),
1183 +       PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5),
1184 +       PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0),
1185 +       PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0),
1186 +       PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0),
1187 +       PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2),
1188 +       PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1),
1189 +       PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1),
1190 +       PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1),
1191 +};
1192 +
1193 +static const struct mtk_io_type_desc mt7988_io_type_desc[] = {
1194 +       [IO_TYPE_GRP0] = {
1195 +               .name = "18OD33",
1196 +               .bias_set = mtk_pinconf_bias_set_pupd_r1_r0,
1197 +               .drive_set = mtk_pinconf_drive_set_v1,
1198 +               .input_enable = mtk_pinconf_input_enable_v1,
1199 +       },
1200 +       [IO_TYPE_GRP1] = {
1201 +               .name = "18A01",
1202 +               .bias_set = mtk_pinconf_bias_set_pu_pd,
1203 +               .drive_set = mtk_pinconf_drive_set_v1,
1204 +               .input_enable = mtk_pinconf_input_enable_v1,
1205 +       },
1206 +       [IO_TYPE_GRP2] = {
1207 +               .name = "I2C",
1208 +               .input_enable = mtk_pinconf_input_enable_v1,
1209 +       },
1210 +};
1211 +
1212 +/* Joint those groups owning the same capability in user point of view which
1213 + * allows that people tend to use through the device tree.
1214 + */
1215 +static const char *const mt7988_jtag_groups[] = { "tops_jtag0_0", "wo0_jtag",
1216 +       "wo1_jtag", "wo2_jtag", "jtag", "tops_jtag0_1", };
1217 +static const char *const mt7988_int_usxgmii_groups[] = { "int_usxgmii", };
1218 +static const char *const mt7988_pwm_groups[] = { "pwm0", "pwm1", "pwm2", "pwm3",
1219 +       "pwm4", "pwm5", "pwm6", "pwm7" };
1220 +static const char *const mt7988_dfd_groups[] = { "dfd", };
1221 +static const char *const mt7988_i2c_groups[] = { "xfi_phy0_i2c0",
1222 +       "xfi_phy1_i2c0", "xfi_phy_pll_i2c0", "xfi_phy_pll_i2c1", "i2c0_0",
1223 +       "i2c1_sfp", "xfi_pextp_phy0_i2c", "xfi_pextp_phy1_i2c", "i2c0_1",
1224 +       "u30_phy_i2c0", "u32_phy_i2c0", "xfi_phy0_i2c1", "xfi_phy1_i2c1",
1225 +       "xfi_phy_pll_i2c2", "i2c1_0", "u30_phy_i2c1", "u32_phy_i2c1",
1226 +       "xfi_phy_pll_i2c3", "sgmii0_i2c", "sgmii1_i2c", "i2c1_2", "i2c2_0",
1227 +       "i2c2_1", };
1228 +static const char *const mt7988_ethernet_groups[] = { "mdc_mdio0",
1229 +       "2p5g_ext_mdio", "gbe_ext_mdio", "mdc_mdio1", };
1230 +static const char *const mt7988_pcie_groups[] = { "pcie_wake_n0_0",
1231 +       "pcie_clk_req_n0_0", "pcie_wake_n3_0", "pcie_clk_req_n3",
1232 +       "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", "pcie_p3_phy_i2",
1233 +       "pcie_p2_phy_i2c", "ckm_phy_i2c", "pcie_wake_n0_1", "pcie_wake_n3_1",
1234 +       "pcie_2l_0_pereset", "pcie_1l_1_pereset", "pcie_clk_req_n2_1",
1235 +       "pcie_2l_1_perese", "pcie_1l_0_pereset", "pcie_wake_n1_0",
1236 +       "cie_clk_req_n1", "pcie_wake_n2_0", "pcie_wake_n2_1", };
1237 +static const char *const mt7988_pmic_groups[] = { "pmic", };
1238 +static const char *const mt7988_wdt_groups[] = { "watchdog", };
1239 +static const char *const mt7988_spi_groups[] = { "spi0", "spi0_wp_hold",
1240 +       "spi1", "spi2", "spi2_wp_hold", };
1241 +static const char *const mt7988_flash_groups[] = { "emmc_45", "snfi",
1242 +       "emmc_51" };
1243 +static const char *const mt7988_uart_groups[] = { "uart2", "tops_uart0_0",
1244 +       "uart2_0", "uart1_0", "uart2_1",
1245 +       "net_wo0_uart_txd_0", "net_wo1_uart_txd_0", "net_wo2_uart_txd_0",
1246 +       "tops_uart1_0", "ops_uart0_1", "ops_uart1_1",
1247 +       "uart0", "tops_uart0_2", "uart1_1",
1248 +       "uart2_3", "uart1_2", "tops_uart1_2",
1249 +       "net_wo0_uart_txd_1", "net_wo1_uart_txd_1", "net_wo2_uart_txd_1", };
1250 +static const char *const mt7988_udi_groups[] = { "udi", };
1251 +static const char *const mt7988_pcm_groups[] = { "pcm", };
1252 +static const char *const mt7988_led_groups[] = { "gbe_led1", "2p5gbe_led1",
1253 +       "gbe_led0", "2p5gbe_led0", "wf5g_led0", "wf5g_led1", };
1254 +static const char *const mt7988_usb_groups[] = { "drv_vbus", "drv_vbus_p1", };
1255 +
1256 +static const struct mtk_function_desc mt7988_functions[] = {
1257 +       {"jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups)},
1258 +       {"int_usxgmii", mt7988_int_usxgmii_groups,
1259 +                       ARRAY_SIZE(mt7988_int_usxgmii_groups)},
1260 +       {"pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups)},
1261 +       {"dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups)},
1262 +       {"i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups)},
1263 +       {"eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups)},
1264 +       {"pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups)},
1265 +       {"pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups)},
1266 +       {"watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups)},
1267 +       {"spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups)},
1268 +       {"flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups)},
1269 +       {"uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups)},
1270 +       {"udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups)},
1271 +       {"pcm", mt7988_pcm_groups, ARRAY_SIZE(mt7988_pcm_groups)},
1272 +       {"usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups)},
1273 +       {"led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups)},
1274 +};
1275 +
1276 +static const char *const mt7988_pinctrl_register_base_names[] = {
1277 +       "gpio_base", "iocfg_tr_base", "iocfg_br_base", "iocfg_rb_base",
1278 +       "iocfg_lb_base", "iocfg_tl_base",
1279 +};
1280 +
1281 +static const struct mtk_pinctrl_soc mt7988_data = {
1282 +       .name = "mt7988_pinctrl",
1283 +       .reg_cal = mt7988_reg_cals,
1284 +       .pins = mt7988_pins,
1285 +       .npins = ARRAY_SIZE(mt7988_pins),
1286 +       .grps = mt7988_groups,
1287 +       .ngrps = ARRAY_SIZE(mt7988_groups),
1288 +       .funcs = mt7988_functions,
1289 +       .nfuncs = ARRAY_SIZE(mt7988_functions),
1290 +       .io_type = mt7988_io_type_desc,
1291 +       .ntype = ARRAY_SIZE(mt7988_io_type_desc),
1292 +       .gpio_mode = 0,
1293 +       .base_names = mt7988_pinctrl_register_base_names,
1294 +       .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names),
1295 +       .base_calc = 1,
1296 +};
1297 +
1298 +static int mtk_pinctrl_mt7988_probe(struct udevice *dev)
1299 +{
1300 +       return mtk_pinctrl_common_probe(dev, &mt7988_data);
1301 +}
1302 +
1303 +static const struct udevice_id mt7988_pctrl_match[] = {
1304 +       {.compatible = "mediatek,mt7988-pinctrl"},
1305 +       { /* sentinel */ }
1306 +};
1307 +
1308 +U_BOOT_DRIVER(mt7988_pinctrl) = {
1309 +       .name = "mt7988_pinctrl",
1310 +       .id = UCLASS_PINCTRL,
1311 +       .of_match = mt7988_pctrl_match,
1312 +       .ops = &mtk_pinctrl_ops,
1313 +       .probe = mtk_pinctrl_mt7988_probe,
1314 +       .priv_auto = sizeof(struct mtk_pinctrl_priv),
1315 +};