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12eda828fa9b9eace0fe96aec338fe1bbd198b42
[openwrt/staging/jow.git] / package / boot / uboot-mediatek / patches / 101-10-clk-mediatek-add-clock-driver-support-for-MediaTek-M.patch
1 From 94306126baa215c39e9fd5328550586dedf00230 Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Wed, 19 Jul 2023 17:16:28 +0800
4 Subject: [PATCH 10/29] clk: mediatek: add clock driver support for MediaTek
5 MT7988 SoC
6
7 This patch adds clock driver support for MediaTek MT7988 SoC
8
9 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
10 ---
11 drivers/clk/mediatek/Makefile | 1 +
12 drivers/clk/mediatek/clk-mt7988.c | 1123 ++++++++++++++++++++++++
13 include/dt-bindings/clock/mt7988-clk.h | 349 ++++++++
14 3 files changed, 1473 insertions(+)
15 create mode 100644 drivers/clk/mediatek/clk-mt7988.c
16 create mode 100644 include/dt-bindings/clock/mt7988-clk.h
17
18 --- a/drivers/clk/mediatek/Makefile
19 +++ b/drivers/clk/mediatek/Makefile
20 @@ -9,6 +9,7 @@ obj-$(CONFIG_TARGET_MT7622) += clk-mt762
21 obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
22 obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o
23 obj-$(CONFIG_TARGET_MT7981) += clk-mt7981.o
24 +obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o
25 obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
26 obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
27 obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
28 --- /dev/null
29 +++ b/drivers/clk/mediatek/clk-mt7988.c
30 @@ -0,0 +1,1123 @@
31 +// SPDX-License-Identifier: GPL-2.0
32 +/*
33 + * MediaTek clock driver for MT7988 SoC
34 + *
35 + * Copyright (C) 2022 MediaTek Inc.
36 + * Author: Sam Shih <sam.shih@mediatek.com>
37 + */
38 +
39 +#include <dm.h>
40 +#include <log.h>
41 +#include <asm/arch-mediatek/reset.h>
42 +#include <asm/io.h>
43 +#include <dt-bindings/clock/mt7988-clk.h>
44 +#include <linux/bitops.h>
45 +
46 +#include "clk-mtk.h"
47 +
48 +#define MT7988_CLK_PDN 0x250
49 +#define MT7988_CLK_PDN_EN_WRITE BIT(31)
50 +
51 +#define MT7988_ETHDMA_RST_CTRL_OFS 0x34
52 +#define MT7988_ETHWARP_RST_CTRL_OFS 0x8
53 +
54 +#define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \
55 + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL)
56 +
57 +#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \
58 + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
59 +
60 +#define TOP_FACTOR(_id, _name, _parent, _mult, _div) \
61 + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
62 +
63 +#define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \
64 + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS)
65 +
66 +/* FIXED PLLS */
67 +static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
68 + FIXED_CLK(CK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000),
69 + FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
70 + FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000),
71 + FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
72 + FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
73 + FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
74 + FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
75 + FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
76 + FIXED_CLK(CK_APMIXED_ARM_B, CLK_XTAL, 1500000000),
77 + FIXED_CLK(CK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000),
78 + FIXED_CLK(CK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000),
79 + FIXED_CLK(CK_APMIXED_MSDCPLL, CLK_XTAL, 400000000),
80 +};
81 +
82 +/* TOPCKGEN FIXED DIV */
83 +static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = {
84 + XTAL_FACTOR(CK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1),
85 + PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
86 + PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
87 + PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
88 + PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
89 + PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
90 + PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
91 + PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1),
92 + PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
93 + PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15),
94 + PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
95 + PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12),
96 + PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
97 + PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
98 + 1),
99 + PLL_FACTOR(CK_TOP_CB_APLL2_D4, "cb_apll2_d4", CK_APMIXED_APLL2, 1, 4),
100 + PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
101 + PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
102 + PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
103 + PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
104 + PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8),
105 + PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
106 + PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
107 + PLL_FACTOR(CK_TOP_NET1_D8_D8, "net1_d8_d8", CK_APMIXED_NET1PLL, 1, 64),
108 + PLL_FACTOR(CK_TOP_NET1_D8_D16, "net1_d8_d16", CK_APMIXED_NET1PLL, 1,
109 + 128),
110 + PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
111 + 1),
112 + PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2),
113 + PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
114 + PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
115 + PLL_FACTOR(CK_TOP_NET2_D4_D8, "net2_d4_d8", CK_APMIXED_NET2PLL, 1, 32),
116 + PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6),
117 + PLL_FACTOR(CK_TOP_CB_NET2_D8, "cb_net2_d8", CK_APMIXED_NET2PLL, 1, 8),
118 + PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m",
119 + CK_APMIXED_WEDMCUPLL, 1, 1),
120 + PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
121 + PLL_FACTOR(CK_TOP_CB_NETSYS_850M, "cb_netsys_850m",
122 + CK_APMIXED_NETSYSPLL, 1, 1),
123 + PLL_FACTOR(CK_TOP_CB_MSDC_400M, "cb_msdc_400m", CK_APMIXED_MSDCPLL, 1,
124 + 1),
125 + TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2),
126 + TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
127 + 1250),
128 + TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
129 + 1220),
130 + TOP_FACTOR(CK_TOP_INFRA_F32K, "csw_infra_f32k", CK_TOP_CB_RTC_32P7K, 1,
131 + 1),
132 + XTAL_FACTOR(CK_TOP_CKSQ_SRC, "cksq_src", CLK_XTAL, 1, 1),
133 + TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
134 + TOP_FACTOR(CK_TOP_NETSYS_GSW, "netsys_gsw", CK_TOP_NETSYS_GSW_SEL, 1,
135 + 1),
136 + TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
137 + CK_TOP_NETSYS_MCU_SEL, 1, 1),
138 + TOP_FACTOR(CK_TOP_EIP197, "eip197", CK_TOP_EIP197_SEL, 1, 1),
139 + TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1),
140 + TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1),
141 + TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1),
142 + TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1),
143 + TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
144 + TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
145 + TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
146 + TOP_FACTOR(CK_TOP_USB_SYS, "usb_sys", CK_TOP_USB_SYS_SEL, 1, 1),
147 + TOP_FACTOR(CK_TOP_USB_SYS_P1, "usb_sys_p1", CK_TOP_USB_SYS_P1_SEL, 1,
148 + 1),
149 + TOP_FACTOR(CK_TOP_USB_XHCI, "usb_xhci", CK_TOP_USB_XHCI_SEL, 1, 1),
150 + TOP_FACTOR(CK_TOP_USB_XHCI_P1, "usb_xhci_p1", CK_TOP_USB_XHCI_P1_SEL, 1,
151 + 1),
152 + TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1,
153 + 1),
154 + TOP_FACTOR(CK_TOP_USB_FRMCNT_P1, "usb_frmcnt_p1",
155 + CK_TOP_USB_FRMCNT_P1_SEL, 1, 1),
156 + TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_AUD_SEL, 1, 1),
157 + TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
158 + TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
159 + TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1),
160 + TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
161 + TOP_FACTOR(CK_TOP_INFRA_F26M, "csw_infra_f26m", CK_TOP_INFRA_F26M_SEL,
162 + 1, 1),
163 + TOP_FACTOR(CK_TOP_USB_REF, "usb_ref", CK_TOP_CKSQ_SRC, 1, 1),
164 + TOP_FACTOR(CK_TOP_USB_CK_P1, "usb_ck_p1", CK_TOP_CKSQ_SRC, 1, 1),
165 +};
166 +
167 +/* TOPCKGEN MUX PARENTS */
168 +static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2,
169 + CK_TOP_CB_MM_D2 };
170 +
171 +static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
172 + CK_TOP_CB_NET1_D5,
173 + CK_TOP_NET1_D5_D2 };
174 +
175 +static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
176 + CK_TOP_CB_NET2_800M,
177 + CK_TOP_CB_MM_720M };
178 +
179 +static const int netsys_gsw_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D4,
180 + CK_TOP_CB_NET1_D5 };
181 +
182 +static const int eth_gmii_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
183 +
184 +static const int netsys_mcu_parents[] = {
185 + CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M, CK_TOP_CB_MM_720M,
186 + CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5, CK_TOP_CB_M_416M
187 +};
188 +
189 +static const int eip197_parents[] = {
190 + CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NETSYS_850M, CK_TOP_CB_NET2_800M,
191 + CK_TOP_CB_MM_720M, CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5
192 +};
193 +
194 +static const int axi_infra_parents[] = { CK_TOP_CB_CKSQ_40M,
195 + CK_TOP_NET1_D8_D2 };
196 +
197 +static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
198 + CK_TOP_M_D8_D2 };
199 +
200 +static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D2,
201 + CK_TOP_CB_MM_D4 };
202 +
203 +static const int emmc_400m_parents[] = {
204 + CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MSDC_400M, CK_TOP_CB_MM_D2,
205 + CK_TOP_CB_M_D2, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2
206 +};
207 +
208 +static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
209 + CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2,
210 + CK_TOP_CB_NET2_D6, CK_TOP_NET1_D5_D4,
211 + CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
212 +
213 +static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4,
214 + CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6,
215 + CK_TOP_CB_M_D4, CK_TOP_CB_MM_D8,
216 + CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 };
217 +
218 +static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M,
219 + CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
220 + CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4,
221 + CK_TOP_MM_D6_D2, CK_TOP_CB_M_D8 };
222 +
223 +static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
224 + CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
225 + CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
226 +
227 +static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
228 + CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
229 +
230 +static const int pcie_mbist_250m_parents[] = { CK_TOP_CB_CKSQ_40M,
231 + CK_TOP_NET1_D5_D2 };
232 +
233 +static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
234 + CK_TOP_CB_NET2_D6, CK_TOP_CB_MM_D8,
235 + CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
236 +
237 +static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M,
238 + CK_TOP_CB_MM_D3_D5 };
239 +
240 +static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M };
241 +
242 +static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_D4 };
243 +
244 +static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
245 + CK_TOP_M_D8_D2 };
246 +
247 +static const int sspxtp_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 };
248 +
249 +static const int usxgmii_sbus_0_parents[] = { CK_TOP_CB_CKSQ_40M,
250 + CK_TOP_NET1_D8_D4 };
251 +
252 +static const int sgm_0_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M };
253 +
254 +static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 };
255 +
256 +static const int eth_refck_50m_parents[] = { CK_TOP_CB_CKSQ_40M,
257 + CK_TOP_NET2_D4_D4 };
258 +
259 +static const int eth_sys_200m_parents[] = { CK_TOP_CB_CKSQ_40M,
260 + CK_TOP_CB_NET2_D4 };
261 +
262 +static const int eth_xgmii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET1_D8_D8,
263 + CK_TOP_NET1_D8_D16 };
264 +
265 +static const int bus_tops_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5,
266 + CK_TOP_CB_NET2_D2 };
267 +
268 +static const int npu_tops_parents[] = { CK_TOP_CB_CKSQ_40M,
269 + CK_TOP_CB_NET2_800M };
270 +
271 +static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
272 + CK_TOP_CB_WEDMCU_208M };
273 +
274 +static const int da_xtp_glb_p0_parents[] = { CK_TOP_CB_CKSQ_40M,
275 + CK_TOP_CB_NET2_D8 };
276 +
277 +static const int mcusys_backup_625m_parents[] = { CK_TOP_CB_CKSQ_40M,
278 + CK_TOP_CB_NET1_D4 };
279 +
280 +static const int macsec_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M,
281 + CK_TOP_CB_NET1_D8 };
282 +
283 +static const int netsys_tops_400m_parents[] = { CK_TOP_CB_CKSQ_40M,
284 + CK_TOP_CB_NET2_D2 };
285 +
286 +static const int eth_mii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET2_D4_D8 };
287 +
288 +#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
289 + _shift, _width, _gate, _upd_ofs, _upd) \
290 + { \
291 + .id = _id, .mux_reg = _mux_ofs, .mux_set_reg = _mux_set_ofs, \
292 + .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \
293 + .upd_shift = _upd, .mux_shift = _shift, \
294 + .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \
295 + .gate_shift = _gate, .parent = _parents, \
296 + .num_parents = ARRAY_SIZE(_parents), \
297 + .flags = CLK_MUX_SETCLR_UPD, \
298 + }
299 +
300 +/* TOPCKGEN MUX_GATE */
301 +static const struct mtk_composite topckgen_mtk_muxes[] = {
302 + TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x0, 0x4, 0x8,
303 + 0, 2, 7, 0x1c0, 0),
304 + TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
305 + 0x0, 0x4, 0x8, 8, 2, 15, 0x1c0, 1),
306 + TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x0,
307 + 0x4, 0x8, 16, 2, 23, 0x1c0, 2),
308 + TOP_MUX(CK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents,
309 + 0x0, 0x4, 0x8, 24, 2, 31, 0x1c0, 3),
310 + TOP_MUX(CK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x10,
311 + 0x14, 0x18, 0, 1, 7, 0x1c0, 4),
312 + TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
313 + 0x10, 0x14, 0x18, 8, 3, 15, 0x1c0, 5),
314 + TOP_MUX(CK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
315 + netsys_mcu_parents, 0x10, 0x14, 0x18, 16, 3, 23, 0x1c0, 6),
316 + TOP_MUX(CK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x10, 0x14,
317 + 0x18, 24, 3, 31, 0x1c0, 7),
318 + TOP_MUX(CK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x20,
319 + 0x24, 0x28, 0, 1, 7, 0x1c0, 8),
320 + TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x20, 0x24, 0x28, 8,
321 + 2, 15, 0x1c0, 9),
322 + TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x20,
323 + 0x24, 0x28, 16, 2, 23, 0x1c0, 10),
324 + TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
325 + 0x24, 0x28, 24, 3, 31, 0x1c0, 11),
326 + TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x30, 0x34, 0x38, 0, 3,
327 + 7, 0x1c0, 12),
328 + TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x30, 0x34,
329 + 0x38, 8, 3, 15, 0x1c0, 13),
330 + TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x30, 0x34, 0x38,
331 + 16, 3, 23, 0x1c0, 14),
332 + TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x30, 0x34,
333 + 0x38, 24, 3, 31, 0x1c0, 15),
334 + TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x40, 0x44, 0x48, 0, 3,
335 + 7, 0x1c0, 16),
336 + TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x40, 0x44, 0x48, 8, 2,
337 + 15, 0x1c0, 17),
338 + TOP_MUX(CK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel",
339 + pcie_mbist_250m_parents, 0x40, 0x44, 0x48, 16, 1, 23, 0x1c0,
340 + 18),
341 + TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
342 + 0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19),
343 + TOP_MUX(CK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel",
344 + pextp_tl_ck_parents, 0x50, 0x54, 0x58, 0, 3, 7, 0x1c0, 20),
345 + TOP_MUX(CK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel",
346 + pextp_tl_ck_parents, 0x50, 0x54, 0x58, 8, 3, 15, 0x1c0, 21),
347 + TOP_MUX(CK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel",
348 + pextp_tl_ck_parents, 0x50, 0x54, 0x58, 16, 3, 23, 0x1c0, 22),
349 + TOP_MUX(CK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x50, 0x54,
350 + 0x58, 24, 1, 31, 0x1c0, 23),
351 + TOP_MUX(CK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x60,
352 + 0x64, 0x68, 0, 1, 7, 0x1c0, 24),
353 + TOP_MUX(CK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x60,
354 + 0x64, 0x68, 8, 1, 15, 0x1c0, 25),
355 + TOP_MUX(CK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents,
356 + 0x60, 0x64, 0x68, 16, 1, 23, 0x1c0, 26),
357 + TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
358 + 0x60, 0x64, 0x68, 24, 1, 31, 0x1c0, 27),
359 + TOP_MUX(CK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
360 + usb_frmcnt_parents, 0x70, 0x74, 0x78, 0, 1, 7, 0x1c0, 28),
361 + TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x70, 0x74, 0x78, 8, 1,
362 + 15, 0x1c0, 29),
363 + TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x70, 0x74, 0x78,
364 + 16, 1, 23, 0x1c0, 30),
365 + TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x70, 0x74, 0x78,
366 + 24, 2, 31, 0x1c4, 0),
367 + TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x80, 0x84,
368 + 0x88, 0, 1, 7, 0x1c4, 1),
369 + TOP_MUX(CK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x80, 0x84,
370 + 0x88, 8, 1, 15, 0x1c4, 2),
371 + TOP_MUX(CK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x80, 0x84,
372 + 0x88, 16, 1, 23, 0x1c4, 3),
373 + TOP_MUX(CK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
374 + usxgmii_sbus_0_parents, 0x80, 0x84, 0x88, 24, 1, 31, 0x1c4, 4),
375 + TOP_MUX(CK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
376 + usxgmii_sbus_0_parents, 0x90, 0x94, 0x98, 0, 1, 7, 0x1c4, 5),
377 + TOP_MUX(CK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x90, 0x94, 0x98,
378 + 8, 1, 15, 0x1c4, 6),
379 + TOP_MUX(CK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents,
380 + 0x90, 0x94, 0x98, 16, 1, 23, 0x1c4, 7),
381 + TOP_MUX(CK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x90, 0x94, 0x98,
382 + 24, 1, 31, 0x1c4, 8),
383 + TOP_MUX(CK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents,
384 + 0xa0, 0xa4, 0xa8, 0, 1, 7, 0x1c4, 9),
385 + TOP_MUX(CK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents,
386 + 0xa0, 0xa4, 0xa8, 8, 1, 15, 0x1c4, 10),
387 + TOP_MUX(CK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents,
388 + 0xa0, 0xa4, 0xa8, 16, 1, 23, 0x1c4, 11),
389 + TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0xa0, 0xa4,
390 + 0xa8, 24, 1, 31, 0x1c4, 12),
391 + TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0xb0, 0xb4,
392 + 0xb8, 0, 1, 7, 0x1c4, 13),
393 + TOP_MUX(CK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
394 + eth_refck_50m_parents, 0xb0, 0xb4, 0xb8, 8, 1, 15, 0x1c4, 14),
395 + TOP_MUX(CK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
396 + eth_sys_200m_parents, 0xb0, 0xb4, 0xb8, 16, 1, 23, 0x1c4, 15),
397 + TOP_MUX(CK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents,
398 + 0xb0, 0xb4, 0xb8, 24, 1, 31, 0x1c4, 16),
399 + TOP_MUX(CK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0xc0,
400 + 0xc4, 0xc8, 0, 2, 7, 0x1c4, 17),
401 + TOP_MUX(CK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0xc0,
402 + 0xc4, 0xc8, 8, 2, 15, 0x1c4, 18),
403 + TOP_MUX(CK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0xc0,
404 + 0xc4, 0xc8, 16, 1, 23, 0x1c4, 19),
405 + TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0xc0, 0xc4, 0xc8,
406 + 24, 1, 31, 0x1c4, 20),
407 + TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
408 + 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x1c4, 21),
409 + TOP_MUX(CK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
410 + 0xd0, 0xd4, 0xd8, 8, 1, 15, 0x1c4, 22),
411 + TOP_MUX(CK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0xd0, 0xd4,
412 + 0xd8, 16, 1, 23, 0x1c4, 23),
413 + TOP_MUX(CK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0xd0, 0xd4,
414 + 0xd8, 24, 1, 31, 0x1c4, 24),
415 + TOP_MUX(CK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0xe0, 0xe4,
416 + 0xe8, 0, 1, 7, 0x1c4, 25),
417 + TOP_MUX(CK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0xe0, 0xe4,
418 + 0xe8, 8, 1, 15, 0x1c4, 26),
419 + TOP_MUX(CK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
420 + da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 16, 1, 23, 0x1c4, 27),
421 + TOP_MUX(CK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
422 + da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 24, 1, 31, 0x1c4, 28),
423 + TOP_MUX(CK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
424 + da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x1c4, 29),
425 + TOP_MUX(CK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
426 + da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 8, 1, 15, 0x1c4, 30),
427 + TOP_MUX(CK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16,
428 + 1, 23, 0x1c8, 0),
429 + TOP_MUX(CK_TOP_DA_SELM_XTAL_SEL, "da_selm_xtal_sel", sspxtp_parents,
430 + 0xf0, 0xf4, 0xf8, 24, 1, 31, 0x1c8, 1),
431 + TOP_MUX(CK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104,
432 + 0x108, 0, 1, 7, 0x1c8, 2),
433 + TOP_MUX(CK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents,
434 + 0x100, 0x104, 0x108, 8, 1, 15, 0x1c8, 3),
435 + TOP_MUX(CK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel",
436 + mcusys_backup_625m_parents, 0x100, 0x104, 0x108, 16, 1, 23,
437 + 0x1c8, 4),
438 + TOP_MUX(CK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel",
439 + pcie_mbist_250m_parents, 0x100, 0x104, 0x108, 24, 1, 31, 0x1c8,
440 + 5),
441 + TOP_MUX(CK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x110, 0x114,
442 + 0x118, 0, 2, 7, 0x1c8, 6),
443 + TOP_MUX(CK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel",
444 + netsys_tops_400m_parents, 0x110, 0x114, 0x118, 8, 1, 15, 0x1c8,
445 + 7),
446 + TOP_MUX(CK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel",
447 + pcie_mbist_250m_parents, 0x110, 0x114, 0x118, 16, 1, 23, 0x1c8,
448 + 8),
449 + TOP_MUX(CK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents,
450 + 0x110, 0x114, 0x118, 24, 2, 31, 0x1c8, 9),
451 + TOP_MUX(CK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120,
452 + 0x124, 0x128, 0, 1, 7, 0x1c8, 10),
453 + TOP_MUX(CK_TOP_CK_NPU_SEL_CM_TOPS_SEL, "ck_npu_sel_cm_tops_sel",
454 + netsys_2x_parents, 0x120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
455 +};
456 +
457 +/* INFRA FIXED DIV */
458 +static const struct mtk_fixed_factor infracfg_mtk_fixed_factor[] = {
459 + TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_INFRA_F26M_SEL, 1,
460 + 1),
461 + TOP_FACTOR(CK_INFRA_PWM_O, "infra_pwm_o", CK_TOP_PWM_SEL, 1, 1),
462 + TOP_FACTOR(CK_INFRA_PCIE_OCC_P0, "infra_pcie_ck_occ_p0",
463 + CK_TOP_PEXTP_TL_SEL, 1, 1),
464 + TOP_FACTOR(CK_INFRA_PCIE_OCC_P1, "infra_pcie_ck_occ_p1",
465 + CK_TOP_PEXTP_TL_P1_SEL, 1, 1),
466 + TOP_FACTOR(CK_INFRA_PCIE_OCC_P2, "infra_pcie_ck_occ_p2",
467 + CK_TOP_PEXTP_TL_P2_SEL, 1, 1),
468 + TOP_FACTOR(CK_INFRA_PCIE_OCC_P3, "infra_pcie_ck_occ_p3",
469 + CK_TOP_PEXTP_TL_P3_SEL, 1, 1),
470 + TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1),
471 + INFRA_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_INFRA_133M_HCK,
472 + 1, 1),
473 + INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1,
474 + 1),
475 + TOP_FACTOR(CK_INFRA_FAUD_L_O, "infra_faud_l_o", CK_TOP_AUD_L, 1, 1),
476 + TOP_FACTOR(CK_INFRA_FAUD_AUD_O, "infra_faud_aud_o", CK_TOP_A1SYS, 1, 1),
477 + TOP_FACTOR(CK_INFRA_FAUD_EG2_O, "infra_faud_eg2_o", CK_TOP_A_TUNER, 1,
478 + 1),
479 + TOP_FACTOR(CK_INFRA_I2C_O, "infra_i2c_o", CK_TOP_I2C_BCK, 1, 1),
480 + TOP_FACTOR(CK_INFRA_UART_O0, "infra_uart_o0", CK_TOP_UART_SEL, 1, 1),
481 + TOP_FACTOR(CK_INFRA_UART_O1, "infra_uart_o1", CK_TOP_UART_SEL, 1, 1),
482 + TOP_FACTOR(CK_INFRA_UART_O2, "infra_uart_o2", CK_TOP_UART_SEL, 1, 1),
483 + TOP_FACTOR(CK_INFRA_NFI_O, "infra_nfi_o", CK_TOP_NFI1X, 1, 1),
484 + TOP_FACTOR(CK_INFRA_SPINFI_O, "infra_spinfi_o", CK_TOP_SPINFI_BCK, 1,
485 + 1),
486 + TOP_FACTOR(CK_INFRA_SPI0_O, "infra_spi0_o", CK_TOP_SPI, 1, 1),
487 + TOP_FACTOR(CK_INFRA_SPI1_O, "infra_spi1_o", CK_TOP_SPIM_MST, 1, 1),
488 + INFRA_FACTOR(CK_INFRA_LB_MUX_FRTC, "infra_lb_mux_frtc", CK_INFRA_FRTC,
489 + 1, 1),
490 + TOP_FACTOR(CK_INFRA_FRTC, "infra_frtc", CK_TOP_CB_RTC_32K, 1, 1),
491 + TOP_FACTOR(CK_INFRA_FMSDC400_O, "infra_fmsdc400_o", CK_TOP_EMMC_400M, 1,
492 + 1),
493 + TOP_FACTOR(CK_INFRA_FMSDC2_HCK_OCC, "infra_fmsdc2_hck_occ",
494 + CK_TOP_EMMC_250M, 1, 1),
495 + TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1),
496 + TOP_FACTOR(CK_INFRA_USB_O, "infra_usb_o", CK_TOP_USB_REF, 1, 1),
497 + TOP_FACTOR(CK_INFRA_USB_O_P1, "infra_usb_o_p1", CK_TOP_USB_CK_P1, 1, 1),
498 + TOP_FACTOR(CK_INFRA_USB_FRMCNT_O, "infra_usb_frmcnt_o",
499 + CK_TOP_USB_FRMCNT, 1, 1),
500 + TOP_FACTOR(CK_INFRA_USB_FRMCNT_O_P1, "infra_usb_frmcnt_o_p1",
501 + CK_TOP_USB_FRMCNT_P1, 1, 1),
502 + TOP_FACTOR(CK_INFRA_USB_XHCI_O, "infra_usb_xhci_o", CK_TOP_USB_XHCI, 1,
503 + 1),
504 + TOP_FACTOR(CK_INFRA_USB_XHCI_O_P1, "infra_usb_xhci_o_p1",
505 + CK_TOP_USB_XHCI_P1, 1, 1),
506 + XTAL_FACTOR(CK_INFRA_USB_PIPE_O, "infra_usb_pipe_o", CLK_XTAL, 1, 1),
507 + XTAL_FACTOR(CK_INFRA_USB_PIPE_O_P1, "infra_usb_pipe_o_p1", CLK_XTAL, 1,
508 + 1),
509 + XTAL_FACTOR(CK_INFRA_USB_UTMI_O, "infra_usb_utmi_o", CLK_XTAL, 1, 1),
510 + XTAL_FACTOR(CK_INFRA_USB_UTMI_O_P1, "infra_usb_utmi_o_p1", CLK_XTAL, 1,
511 + 1),
512 + XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P0, "infra_pcie_pipe_ck_occ_p0",
513 + CLK_XTAL, 1, 1),
514 + XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P1, "infra_pcie_pipe_ck_occ_p1",
515 + CLK_XTAL, 1, 1),
516 + XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P2, "infra_pcie_pipe_ck_occ_p2",
517 + CLK_XTAL, 1, 1),
518 + XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P3, "infra_pcie_pipe_ck_occ_p3",
519 + CLK_XTAL, 1, 1),
520 + TOP_FACTOR(CK_INFRA_F26M_O0, "infra_f26m_o0", CK_TOP_INFRA_F26M, 1, 1),
521 + TOP_FACTOR(CK_INFRA_F26M_O1, "infra_f26m_o1", CK_TOP_INFRA_F26M, 1, 1),
522 + TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1),
523 + TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI, 1, 1),
524 + TOP_FACTOR(CK_INFRA_PERI_66M_O, "infra_peri_66m_o", CK_TOP_SYSAXI, 1,
525 + 1),
526 + TOP_FACTOR(CK_INFRA_USB_SYS_O, "infra_usb_sys_o", CK_TOP_USB_SYS, 1, 1),
527 + TOP_FACTOR(CK_INFRA_USB_SYS_O_P1, "infra_usb_sys_o_p1",
528 + CK_TOP_USB_SYS_P1, 1, 1),
529 +};
530 +
531 +/* INFRASYS MUX PARENTS */
532 +static const int infra_mux_uart0_parents[] = { CK_INFRA_CK_F26M,
533 + CK_INFRA_UART_O0 };
534 +
535 +static const int infra_mux_uart1_parents[] = { CK_INFRA_CK_F26M,
536 + CK_INFRA_UART_O1 };
537 +
538 +static const int infra_mux_uart2_parents[] = { CK_INFRA_CK_F26M,
539 + CK_INFRA_UART_O2 };
540 +
541 +static const int infra_mux_spi0_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI0_O };
542 +
543 +static const int infra_mux_spi1_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI1_O };
544 +
545 +static const int infra_pwm_bck_parents[] = { CK_TOP_INFRA_F32K,
546 + CK_INFRA_CK_F26M, CK_INFRA_66M_MCK,
547 + CK_INFRA_PWM_O };
548 +
549 +static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = {
550 + CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
551 + CK_INFRA_PCIE_OCC_P0
552 +};
553 +
554 +static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = {
555 + CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
556 + CK_INFRA_PCIE_OCC_P1
557 +};
558 +
559 +static const int infra_pcie_gfmux_tl_ck_o_p2_parents[] = {
560 + CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
561 + CK_INFRA_PCIE_OCC_P2
562 +};
563 +
564 +static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = {
565 + CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M,
566 + CK_INFRA_PCIE_OCC_P3
567 +};
568 +
569 +#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \
570 + { \
571 + .id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0, \
572 + .mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \
573 + .mux_mask = BIT(_width) - 1, .parent = _parents, \
574 + .num_parents = ARRAY_SIZE(_parents), \
575 + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \
576 + }
577 +
578 +/* INFRA MUX */
579 +static const struct mtk_composite infracfg_mtk_mux[] = {
580 + INFRA_MUX(CK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
581 + infra_mux_uart0_parents, 0x10, 0, 1),
582 + INFRA_MUX(CK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
583 + infra_mux_uart1_parents, 0x10, 1, 1),
584 + INFRA_MUX(CK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
585 + infra_mux_uart2_parents, 0x10, 2, 1),
586 + INFRA_MUX(CK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
587 + infra_mux_spi0_parents, 0x10, 4, 1),
588 + INFRA_MUX(CK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
589 + infra_mux_spi1_parents, 0x10, 5, 1),
590 + INFRA_MUX(CK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
591 + infra_mux_spi0_parents, 0x10, 6, 1),
592 + INFRA_MUX(CK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents,
593 + 0x10, 14, 2),
594 + INFRA_MUX(CK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
595 + infra_pwm_bck_parents, 0x10, 16, 2),
596 + INFRA_MUX(CK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
597 + infra_pwm_bck_parents, 0x10, 18, 2),
598 + INFRA_MUX(CK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
599 + infra_pwm_bck_parents, 0x10, 20, 2),
600 + INFRA_MUX(CK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
601 + infra_pwm_bck_parents, 0x10, 22, 2),
602 + INFRA_MUX(CK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
603 + infra_pwm_bck_parents, 0x10, 24, 2),
604 + INFRA_MUX(CK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
605 + infra_pwm_bck_parents, 0x10, 26, 2),
606 + INFRA_MUX(CK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
607 + infra_pwm_bck_parents, 0x10, 28, 2),
608 + INFRA_MUX(CK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
609 + infra_pwm_bck_parents, 0x10, 30, 2),
610 + INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
611 + "infra_pcie_gfmux_tl_o_p0_sel",
612 + infra_pcie_gfmux_tl_ck_o_p0_parents, 0x20, 0, 2),
613 + INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
614 + "infra_pcie_gfmux_tl_o_p1_sel",
615 + infra_pcie_gfmux_tl_ck_o_p1_parents, 0x20, 2, 2),
616 + INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
617 + "infra_pcie_gfmux_tl_o_p2_sel",
618 + infra_pcie_gfmux_tl_ck_o_p2_parents, 0x20, 4, 2),
619 + INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
620 + "infra_pcie_gfmux_tl_o_p3_sel",
621 + infra_pcie_gfmux_tl_ck_o_p3_parents, 0x20, 6, 2),
622 +};
623 +
624 +static const struct mtk_gate_regs infra_0_cg_regs = {
625 + .set_ofs = 0x10,
626 + .clr_ofs = 0x14,
627 + .sta_ofs = 0x18,
628 +};
629 +
630 +static const struct mtk_gate_regs infra_1_cg_regs = {
631 + .set_ofs = 0x40,
632 + .clr_ofs = 0x44,
633 + .sta_ofs = 0x48,
634 +};
635 +
636 +static const struct mtk_gate_regs infra_2_cg_regs = {
637 + .set_ofs = 0x50,
638 + .clr_ofs = 0x54,
639 + .sta_ofs = 0x58,
640 +};
641 +
642 +static const struct mtk_gate_regs infra_3_cg_regs = {
643 + .set_ofs = 0x60,
644 + .clr_ofs = 0x64,
645 + .sta_ofs = 0x68,
646 +};
647 +
648 +#define GATE_INFRA0(_id, _name, _parent, _shift) \
649 + { \
650 + .id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \
651 + .shift = _shift, \
652 + .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
653 + }
654 +
655 +#define GATE_INFRA1(_id, _name, _parent, _shift) \
656 + { \
657 + .id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \
658 + .shift = _shift, \
659 + .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
660 + }
661 +
662 +#define GATE_INFRA2(_id, _name, _parent, _shift) \
663 + { \
664 + .id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \
665 + .shift = _shift, \
666 + .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
667 + }
668 +
669 +#define GATE_INFRA3(_id, _name, _parent, _shift) \
670 + { \
671 + .id = _id, .parent = _parent, .regs = &infra_3_cg_regs, \
672 + .shift = _shift, \
673 + .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
674 + }
675 +
676 +/* INFRA GATE */
677 +static const struct mtk_gate infracfg_mtk_gates[] = {
678 + GATE_INFRA1(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
679 + CK_INFRA_66M_MCK, 0),
680 + GATE_INFRA1(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
681 + CK_INFRA_66M_MCK, 1),
682 + GATE_INFRA1(CK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
683 + CK_INFRA_PWM_SEL, 2),
684 + GATE_INFRA1(CK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
685 + CK_INFRA_PWM_CK1_SEL, 3),
686 + GATE_INFRA1(CK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
687 + CK_INFRA_PWM_CK2_SEL, 4),
688 + GATE_INFRA1(CK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
689 + CK_INFRA_PWM_CK3_SEL, 5),
690 + GATE_INFRA1(CK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
691 + CK_INFRA_PWM_CK4_SEL, 6),
692 + GATE_INFRA1(CK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
693 + CK_INFRA_PWM_CK5_SEL, 7),
694 + GATE_INFRA1(CK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
695 + CK_INFRA_PWM_CK6_SEL, 8),
696 + GATE_INFRA1(CK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
697 + CK_INFRA_PWM_CK7_SEL, 9),
698 + GATE_INFRA1(CK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
699 + CK_INFRA_PWM_CK8_SEL, 10),
700 + GATE_INFRA1(CK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
701 + CK_INFRA_133M_MCK, 12),
702 + GATE_INFRA1(CK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
703 + CK_INFRA_66M_PHCK, 13),
704 + GATE_INFRA1(CK_INFRA_AUD_26M, "infra_f_faud_26m", CK_INFRA_CK_F26M, 14),
705 + GATE_INFRA1(CK_INFRA_AUD_L, "infra_f_faud_l", CK_INFRA_FAUD_L_O, 15),
706 + GATE_INFRA1(CK_INFRA_AUD_AUD, "infra_f_aud_aud", CK_INFRA_FAUD_AUD_O,
707 + 16),
708 + GATE_INFRA1(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", CK_INFRA_FAUD_EG2_O,
709 + 18),
710 + GATE_INFRA1(CK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CK_INFRA_CK_F26M,
711 + 19),
712 + GATE_INFRA1(CK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
713 + CK_INFRA_133M_MCK, 20),
714 + GATE_INFRA1(CK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
715 + CK_INFRA_66M_MCK, 21),
716 + GATE_INFRA1(CK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
717 + CK_INFRA_66M_MCK, 29),
718 + GATE_INFRA1(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
719 + CK_INFRA_CK_F26M, 30),
720 + GATE_INFRA1(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", CK_INFRA_PERI_66M_O,
721 + 31),
722 + GATE_INFRA2(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
723 + CK_INFRA_CK_F26M, 0),
724 + GATE_INFRA2(CK_INFRA_I2C_BCK, "infra_i2c_bck", CK_INFRA_I2C_O, 1),
725 + GATE_INFRA2(CK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck",
726 + CK_INFRA_66M_MCK, 3),
727 + GATE_INFRA2(CK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck",
728 + CK_INFRA_66M_MCK, 4),
729 + GATE_INFRA2(CK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck",
730 + CK_INFRA_66M_MCK, 5),
731 + GATE_INFRA2(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
732 + CK_INFRA_MUX_UART0_SEL, 3),
733 + GATE_INFRA2(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
734 + CK_INFRA_MUX_UART1_SEL, 4),
735 + GATE_INFRA2(CK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
736 + CK_INFRA_MUX_UART2_SEL, 5),
737 + GATE_INFRA2(CK_INFRA_NFI, "infra_f_fnfi", CK_INFRA_NFI_O, 9),
738 + GATE_INFRA2(CK_INFRA_SPINFI, "infra_f_fspinfi", CK_INFRA_SPINFI_O, 10),
739 + GATE_INFRA2(CK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
740 + CK_INFRA_66M_MCK, 11),
741 + GATE_INFRA2(CK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
742 + CK_INFRA_MUX_SPI0_SEL, 12),
743 + GATE_INFRA2(CK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
744 + CK_INFRA_MUX_SPI1_SEL, 13),
745 + GATE_INFRA2(CK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
746 + CK_INFRA_MUX_SPI2_SEL, 14),
747 + GATE_INFRA2(CK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
748 + CK_INFRA_66M_MCK, 15),
749 + GATE_INFRA2(CK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
750 + CK_INFRA_66M_MCK, 16),
751 + GATE_INFRA2(CK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
752 + CK_INFRA_66M_MCK, 17),
753 + GATE_INFRA2(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
754 + CK_INFRA_66M_MCK, 18),
755 + GATE_INFRA2(CK_INFRA_RTC, "infra_f_frtc", CK_INFRA_LB_MUX_FRTC, 19),
756 + GATE_INFRA2(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
757 + CK_INFRA_F26M_O1, 20),
758 + GATE_INFRA2(CK_INFRA_RC_ADC, "infra_f_frc_adc", CK_INFRA_26M_ADC_BCK,
759 + 21),
760 + GATE_INFRA2(CK_INFRA_MSDC400, "infra_f_fmsdc400", CK_INFRA_FMSDC400_O,
761 + 22),
762 + GATE_INFRA2(CK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck",
763 + CK_INFRA_FMSDC2_HCK_OCC, 23),
764 + GATE_INFRA2(CK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
765 + CK_INFRA_PERI_133M, 24),
766 + GATE_INFRA2(CK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
767 + CK_INFRA_66M_PHCK, 25),
768 + GATE_INFRA2(CK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
769 + CK_INFRA_133M_MCK, 26),
770 + GATE_INFRA2(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CK_INFRA_NFI_O,
771 + 27),
772 + GATE_INFRA2(CK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1",
773 + CK_INFRA_133M_MCK, 29),
774 + GATE_INFRA2(CK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1",
775 + CK_INFRA_66M_PHCK, 31),
776 + GATE_INFRA3(CK_INFRA_133M_USB_HCK, "infra_133m_usb_hck",
777 + CK_INFRA_133M_PHCK, 0),
778 + GATE_INFRA3(CK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
779 + CK_INFRA_133M_PHCK, 1),
780 + GATE_INFRA3(CK_INFRA_66M_USB_HCK, "infra_66m_usb_hck",
781 + CK_INFRA_66M_PHCK, 2),
782 + GATE_INFRA3(CK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
783 + CK_INFRA_66M_PHCK, 3),
784 + GATE_INFRA3(CK_INFRA_USB_SYS, "infra_usb_sys", CK_INFRA_USB_SYS_O, 4),
785 + GATE_INFRA3(CK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
786 + CK_INFRA_USB_SYS_O_P1, 5),
787 + GATE_INFRA3(CK_INFRA_USB_REF, "infra_usb_ref", CK_INFRA_USB_O, 6),
788 + GATE_INFRA3(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CK_INFRA_USB_O_P1,
789 + 7),
790 + GATE_INFRA3(CK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
791 + CK_INFRA_USB_FRMCNT_O, 8),
792 + GATE_INFRA3(CK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
793 + CK_INFRA_USB_FRMCNT_O_P1, 9),
794 + GATE_INFRA3(CK_INFRA_USB_PIPE, "infra_usb_pipe", CK_INFRA_USB_PIPE_O,
795 + 10),
796 + GATE_INFRA3(CK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
797 + CK_INFRA_USB_PIPE_O_P1, 11),
798 + GATE_INFRA3(CK_INFRA_USB_UTMI, "infra_usb_utmi", CK_INFRA_USB_UTMI_O,
799 + 12),
800 + GATE_INFRA3(CK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
801 + CK_INFRA_USB_UTMI_O_P1, 13),
802 + GATE_INFRA3(CK_INFRA_USB_XHCI, "infra_usb_xhci", CK_INFRA_USB_XHCI_O,
803 + 14),
804 + GATE_INFRA3(CK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
805 + CK_INFRA_USB_XHCI_O_P1, 15),
806 + GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
807 + CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20),
808 + GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
809 + CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21),
810 + GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
811 + CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22),
812 + GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
813 + CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23),
814 + GATE_INFRA3(CK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
815 + CK_INFRA_PCIE_PIPE_OCC_P0, 24),
816 + GATE_INFRA3(CK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
817 + CK_INFRA_PCIE_PIPE_OCC_P1, 25),
818 + GATE_INFRA3(CK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
819 + CK_INFRA_PCIE_PIPE_OCC_P2, 26),
820 + GATE_INFRA3(CK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
821 + CK_INFRA_PCIE_PIPE_OCC_P3, 27),
822 + GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
823 + CK_INFRA_133M_PHCK, 28),
824 + GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
825 + CK_INFRA_133M_PHCK, 29),
826 + GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
827 + CK_INFRA_133M_PHCK, 30),
828 + GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
829 + CK_INFRA_133M_PHCK, 31),
830 + GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P0,
831 + "infra_pcie_peri_ck_26m_ck_p0", CK_INFRA_F26M_O0, 7),
832 + GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P1,
833 + "infra_pcie_peri_ck_26m_ck_p1", CK_INFRA_F26M_O0, 8),
834 + GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P2,
835 + "infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_F26M_O0, 9),
836 + GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P3,
837 + "infra_pcie_peri_ck_26m_ck_p3", CK_INFRA_F26M_O0, 10),
838 +};
839 +
840 +static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {
841 + .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls),
842 + .fclks = apmixedsys_mtk_plls,
843 + .xtal_rate = 40 * MHZ,
844 +};
845 +
846 +static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
847 + .fdivs_offs = CK_TOP_CB_CKSQ_40M,
848 + .muxes_offs = CK_TOP_NETSYS_SEL,
849 + .fdivs = topckgen_mtk_fixed_factors,
850 + .muxes = topckgen_mtk_muxes,
851 + .flags = CLK_BYPASS_XTAL,
852 + .xtal_rate = 40 * MHZ,
853 +};
854 +
855 +static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
856 + .fdivs_offs = CK_INFRA_CK_F26M,
857 + .muxes_offs = CK_INFRA_MUX_UART0_SEL,
858 + .fdivs = infracfg_mtk_fixed_factor,
859 + .muxes = infracfg_mtk_mux,
860 + .flags = CLK_BYPASS_XTAL,
861 + .xtal_rate = 40 * MHZ,
862 +};
863 +
864 +static const struct udevice_id mt7988_fixed_pll_compat[] = {
865 + { .compatible = "mediatek,mt7988-fixed-plls" },
866 + {}
867 +};
868 +
869 +static const struct udevice_id mt7988_topckgen_compat[] = {
870 + { .compatible = "mediatek,mt7988-topckgen" },
871 + {}
872 +};
873 +
874 +static int mt7988_fixed_pll_probe(struct udevice *dev)
875 +{
876 + return mtk_common_clk_init(dev, &mt7988_fixed_pll_clk_tree);
877 +}
878 +
879 +static int mt7988_topckgen_probe(struct udevice *dev)
880 +{
881 + struct mtk_clk_priv *priv = dev_get_priv(dev);
882 +
883 + priv->base = dev_read_addr_ptr(dev);
884 + if (!priv->base)
885 + return -ENOENT;
886 +
887 + writel(MT7988_CLK_PDN_EN_WRITE, priv->base + MT7988_CLK_PDN);
888 + return mtk_common_clk_init(dev, &mt7988_topckgen_clk_tree);
889 +}
890 +
891 +U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
892 + .name = "mt7988-clock-fixed-pll",
893 + .id = UCLASS_CLK,
894 + .of_match = mt7988_fixed_pll_compat,
895 + .probe = mt7988_fixed_pll_probe,
896 + .priv_auto = sizeof(struct mtk_clk_priv),
897 + .ops = &mtk_clk_topckgen_ops,
898 + .flags = DM_FLAG_PRE_RELOC,
899 +};
900 +
901 +U_BOOT_DRIVER(mtk_clk_topckgen) = {
902 + .name = "mt7988-clock-topckgen",
903 + .id = UCLASS_CLK,
904 + .of_match = mt7988_topckgen_compat,
905 + .probe = mt7988_topckgen_probe,
906 + .priv_auto = sizeof(struct mtk_clk_priv),
907 + .ops = &mtk_clk_topckgen_ops,
908 + .flags = DM_FLAG_PRE_RELOC,
909 +};
910 +
911 +static const struct udevice_id mt7988_infracfg_compat[] = {
912 + { .compatible = "mediatek,mt7988-infracfg" },
913 + {}
914 +};
915 +
916 +static const struct udevice_id mt7988_infracfg_ao_cgs_compat[] = {
917 + { .compatible = "mediatek,mt7988-infracfg_ao_cgs" },
918 + {}
919 +};
920 +
921 +static int mt7988_infracfg_probe(struct udevice *dev)
922 +{
923 + return mtk_common_clk_init(dev, &mt7988_infracfg_clk_tree);
924 +}
925 +
926 +static int mt7988_infracfg_ao_cgs_probe(struct udevice *dev)
927 +{
928 + return mtk_common_clk_gate_init(dev, &mt7988_infracfg_clk_tree,
929 + infracfg_mtk_gates);
930 +}
931 +
932 +U_BOOT_DRIVER(mtk_clk_infracfg) = {
933 + .name = "mt7988-clock-infracfg",
934 + .id = UCLASS_CLK,
935 + .of_match = mt7988_infracfg_compat,
936 + .probe = mt7988_infracfg_probe,
937 + .priv_auto = sizeof(struct mtk_clk_priv),
938 + .ops = &mtk_clk_infrasys_ops,
939 + .flags = DM_FLAG_PRE_RELOC,
940 +};
941 +
942 +U_BOOT_DRIVER(mtk_clk_infracfg_ao_cgs) = {
943 + .name = "mt7988-clock-infracfg_ao_cgs",
944 + .id = UCLASS_CLK,
945 + .of_match = mt7988_infracfg_ao_cgs_compat,
946 + .probe = mt7988_infracfg_ao_cgs_probe,
947 + .priv_auto = sizeof(struct mtk_cg_priv),
948 + .ops = &mtk_clk_gate_ops,
949 + .flags = DM_FLAG_PRE_RELOC,
950 +};
951 +
952 +/* ETHDMA */
953 +
954 +static const struct mtk_gate_regs ethdma_cg_regs = {
955 + .set_ofs = 0x30,
956 + .clr_ofs = 0x30,
957 + .sta_ofs = 0x30,
958 +};
959 +
960 +#define GATE_ETHDMA(_id, _name, _parent, _shift) \
961 + { \
962 + .id = _id, .parent = _parent, .regs = &ethdma_cg_regs, \
963 + .shift = _shift, \
964 + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
965 + }
966 +
967 +static const struct mtk_gate ethdma_mtk_gate[] = {
968 + GATE_ETHDMA(CK_ETHDMA_FE_EN, "ethdma_fe_en", CK_TOP_NETSYS_2X, 6),
969 +};
970 +
971 +static int mt7988_ethdma_probe(struct udevice *dev)
972 +{
973 + return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
974 + ethdma_mtk_gate);
975 +}
976 +
977 +static int mt7988_ethdma_bind(struct udevice *dev)
978 +{
979 + int ret = 0;
980 +
981 + if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) {
982 + ret = mediatek_reset_bind(dev, MT7988_ETHDMA_RST_CTRL_OFS, 1);
983 + if (ret)
984 + debug("Warning: failed to bind reset controller\n");
985 + }
986 +
987 + return ret;
988 +}
989 +
990 +static const struct udevice_id mt7988_ethdma_compat[] = {
991 + {
992 + .compatible = "mediatek,mt7988-ethdma",
993 + },
994 + {}
995 +};
996 +
997 +U_BOOT_DRIVER(mtk_clk_ethdma) = {
998 + .name = "mt7988-clock-ethdma",
999 + .id = UCLASS_CLK,
1000 + .of_match = mt7988_ethdma_compat,
1001 + .probe = mt7988_ethdma_probe,
1002 + .bind = mt7988_ethdma_bind,
1003 + .priv_auto = sizeof(struct mtk_cg_priv),
1004 + .ops = &mtk_clk_gate_ops,
1005 +};
1006 +
1007 +/* SGMIISYS_0 */
1008 +
1009 +static const struct mtk_gate_regs sgmii0_cg_regs = {
1010 + .set_ofs = 0xE4,
1011 + .clr_ofs = 0xE4,
1012 + .sta_ofs = 0xE4,
1013 +};
1014 +
1015 +#define GATE_SGMII0(_id, _name, _parent, _shift) \
1016 + { \
1017 + .id = _id, .parent = _parent, .regs = &sgmii0_cg_regs, \
1018 + .shift = _shift, \
1019 + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
1020 + }
1021 +
1022 +static const struct mtk_gate sgmiisys_0_mtk_gate[] = {
1023 + /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
1024 + GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", CK_TOP_CB_CKSQ_40M, 2),
1025 + /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
1026 + GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", CK_TOP_CB_CKSQ_40M, 3),
1027 +};
1028 +
1029 +static int mt7988_sgmiisys_0_probe(struct udevice *dev)
1030 +{
1031 + return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
1032 + sgmiisys_0_mtk_gate);
1033 +}
1034 +
1035 +static const struct udevice_id mt7988_sgmiisys_0_compat[] = {
1036 + {
1037 + .compatible = "mediatek,mt7988-sgmiisys_0",
1038 + },
1039 + {}
1040 +};
1041 +
1042 +U_BOOT_DRIVER(mtk_clk_sgmiisys_0) = {
1043 + .name = "mt7988-clock-sgmiisys_0",
1044 + .id = UCLASS_CLK,
1045 + .of_match = mt7988_sgmiisys_0_compat,
1046 + .probe = mt7988_sgmiisys_0_probe,
1047 + .priv_auto = sizeof(struct mtk_cg_priv),
1048 + .ops = &mtk_clk_gate_ops,
1049 +};
1050 +
1051 +/* SGMIISYS_1 */
1052 +
1053 +static const struct mtk_gate_regs sgmii1_cg_regs = {
1054 + .set_ofs = 0xE4,
1055 + .clr_ofs = 0xE4,
1056 + .sta_ofs = 0xE4,
1057 +};
1058 +
1059 +#define GATE_SGMII1(_id, _name, _parent, _shift) \
1060 + { \
1061 + .id = _id, .parent = _parent, .regs = &sgmii1_cg_regs, \
1062 + .shift = _shift, \
1063 + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
1064 + }
1065 +
1066 +static const struct mtk_gate sgmiisys_1_mtk_gate[] = {
1067 + /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
1068 + GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", CK_TOP_CB_CKSQ_40M, 2),
1069 + /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */
1070 + GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", CK_TOP_CB_CKSQ_40M, 3),
1071 +};
1072 +
1073 +static int mt7988_sgmiisys_1_probe(struct udevice *dev)
1074 +{
1075 + return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
1076 + sgmiisys_1_mtk_gate);
1077 +}
1078 +
1079 +static const struct udevice_id mt7988_sgmiisys_1_compat[] = {
1080 + {
1081 + .compatible = "mediatek,mt7988-sgmiisys_1",
1082 + },
1083 + {}
1084 +};
1085 +
1086 +U_BOOT_DRIVER(mtk_clk_sgmiisys_1) = {
1087 + .name = "mt7988-clock-sgmiisys_1",
1088 + .id = UCLASS_CLK,
1089 + .of_match = mt7988_sgmiisys_1_compat,
1090 + .probe = mt7988_sgmiisys_1_probe,
1091 + .priv_auto = sizeof(struct mtk_cg_priv),
1092 + .ops = &mtk_clk_gate_ops,
1093 +};
1094 +
1095 +/* ETHWARP */
1096 +
1097 +static const struct mtk_gate_regs ethwarp_cg_regs = {
1098 + .set_ofs = 0x14,
1099 + .clr_ofs = 0x14,
1100 + .sta_ofs = 0x14,
1101 +};
1102 +
1103 +#define GATE_ETHWARP(_id, _name, _parent, _shift) \
1104 + { \
1105 + .id = _id, .parent = _parent, .regs = &ethwarp_cg_regs, \
1106 + .shift = _shift, \
1107 + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
1108 + }
1109 +
1110 +static const struct mtk_gate ethwarp_mtk_gate[] = {
1111 + GATE_ETHWARP(CK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
1112 + CK_TOP_NETSYS_WED_MCU, 13),
1113 + GATE_ETHWARP(CK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
1114 + CK_TOP_NETSYS_WED_MCU, 14),
1115 + GATE_ETHWARP(CK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
1116 + CK_TOP_NETSYS_WED_MCU, 15),
1117 +};
1118 +
1119 +static int mt7988_ethwarp_probe(struct udevice *dev)
1120 +{
1121 + return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
1122 + ethwarp_mtk_gate);
1123 +}
1124 +
1125 +static int mt7988_ethwarp_bind(struct udevice *dev)
1126 +{
1127 + int ret = 0;
1128 +
1129 + if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) {
1130 + ret = mediatek_reset_bind(dev, MT7988_ETHWARP_RST_CTRL_OFS, 2);
1131 + if (ret)
1132 + debug("Warning: failed to bind reset controller\n");
1133 + }
1134 +
1135 + return ret;
1136 +}
1137 +
1138 +static const struct udevice_id mt7988_ethwarp_compat[] = {
1139 + {
1140 + .compatible = "mediatek,mt7988-ethwarp",
1141 + },
1142 + {}
1143 +};
1144 +
1145 +U_BOOT_DRIVER(mtk_clk_ethwarp) = {
1146 + .name = "mt7988-clock-ethwarp",
1147 + .id = UCLASS_CLK,
1148 + .of_match = mt7988_ethwarp_compat,
1149 + .probe = mt7988_ethwarp_probe,
1150 + .bind = mt7988_ethwarp_bind,
1151 + .priv_auto = sizeof(struct mtk_cg_priv),
1152 + .ops = &mtk_clk_gate_ops,
1153 +};
1154 --- /dev/null
1155 +++ b/include/dt-bindings/clock/mt7988-clk.h
1156 @@ -0,0 +1,349 @@
1157 +/* SPDX-License-Identifier: GPL-2.0 */
1158 +/*
1159 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
1160 + *
1161 + * Author: Sam Shih <sam.shih@mediatek.com>
1162 + */
1163 +
1164 +#ifndef _DT_BINDINGS_CLK_MT7988_H
1165 +#define _DT_BINDINGS_CLK_MT7988_H
1166 +
1167 +/* INFRACFG */
1168 +/* mtk_fixed_factor */
1169 +#define CK_INFRA_CK_F26M 0
1170 +#define CK_INFRA_PWM_O 1
1171 +#define CK_INFRA_PCIE_OCC_P0 2
1172 +#define CK_INFRA_PCIE_OCC_P1 3
1173 +#define CK_INFRA_PCIE_OCC_P2 4
1174 +#define CK_INFRA_PCIE_OCC_P3 5
1175 +#define CK_INFRA_133M_HCK 6
1176 +#define CK_INFRA_133M_PHCK 7
1177 +#define CK_INFRA_66M_PHCK 8
1178 +#define CK_INFRA_FAUD_L_O 9
1179 +#define CK_INFRA_FAUD_AUD_O 10
1180 +#define CK_INFRA_FAUD_EG2_O 11
1181 +#define CK_INFRA_I2C_O 12
1182 +#define CK_INFRA_UART_O0 13
1183 +#define CK_INFRA_UART_O1 14
1184 +#define CK_INFRA_UART_O2 15
1185 +#define CK_INFRA_NFI_O 16
1186 +#define CK_INFRA_SPINFI_O 17
1187 +#define CK_INFRA_SPI0_O 18
1188 +#define CK_INFRA_SPI1_O 19
1189 +#define CK_INFRA_LB_MUX_FRTC 20
1190 +#define CK_INFRA_FRTC 21
1191 +#define CK_INFRA_FMSDC400_O 22
1192 +#define CK_INFRA_FMSDC2_HCK_OCC 23
1193 +#define CK_INFRA_PERI_133M 24
1194 +#define CK_INFRA_USB_O 25
1195 +#define CK_INFRA_USB_O_P1 26
1196 +#define CK_INFRA_USB_FRMCNT_O 27
1197 +#define CK_INFRA_USB_FRMCNT_O_P1 28
1198 +#define CK_INFRA_USB_XHCI_O 29
1199 +#define CK_INFRA_USB_XHCI_O_P1 30
1200 +#define CK_INFRA_USB_PIPE_O 31
1201 +#define CK_INFRA_USB_PIPE_O_P1 32
1202 +#define CK_INFRA_USB_UTMI_O 33
1203 +#define CK_INFRA_USB_UTMI_O_P1 34
1204 +#define CK_INFRA_PCIE_PIPE_OCC_P0 35
1205 +#define CK_INFRA_PCIE_PIPE_OCC_P1 36
1206 +#define CK_INFRA_PCIE_PIPE_OCC_P2 37
1207 +#define CK_INFRA_PCIE_PIPE_OCC_P3 38
1208 +#define CK_INFRA_F26M_O0 39
1209 +#define CK_INFRA_F26M_O1 40
1210 +#define CK_INFRA_133M_MCK 41
1211 +#define CK_INFRA_66M_MCK 42
1212 +#define CK_INFRA_PERI_66M_O 43
1213 +#define CK_INFRA_USB_SYS_O 44
1214 +#define CK_INFRA_USB_SYS_O_P1 45
1215 +
1216 +/* INFRACFG_AO */
1217 +#define GATE_OFFSET 65
1218 +/* mtk_mux */
1219 +#define CK_INFRA_MUX_UART0_SEL 46 /* Linux CLK ID (0) */
1220 +#define CK_INFRA_MUX_UART1_SEL 47 /* Linux CLK ID (1) */
1221 +#define CK_INFRA_MUX_UART2_SEL 48 /* Linux CLK ID (2) */
1222 +#define CK_INFRA_MUX_SPI0_SEL 49 /* Linux CLK ID (3) */
1223 +#define CK_INFRA_MUX_SPI1_SEL 50 /* Linux CLK ID (4) */
1224 +#define CK_INFRA_MUX_SPI2_SEL 51 /* Linux CLK ID (5) */
1225 +#define CK_INFRA_PWM_SEL 52 /* Linux CLK ID (6) */
1226 +#define CK_INFRA_PWM_CK1_SEL 53 /* Linux CLK ID (7) */
1227 +#define CK_INFRA_PWM_CK2_SEL 54 /* Linux CLK ID (8) */
1228 +#define CK_INFRA_PWM_CK3_SEL 55 /* Linux CLK ID (9) */
1229 +#define CK_INFRA_PWM_CK4_SEL 56 /* Linux CLK ID (10) */
1230 +#define CK_INFRA_PWM_CK5_SEL 57 /* Linux CLK ID (11) */
1231 +#define CK_INFRA_PWM_CK6_SEL 58 /* Linux CLK ID (12) */
1232 +#define CK_INFRA_PWM_CK7_SEL 59 /* Linux CLK ID (13) */
1233 +#define CK_INFRA_PWM_CK8_SEL 60 /* Linux CLK ID (14) */
1234 +#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 61 /* Linux CLK ID (15) */
1235 +#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 62 /* Linux CLK ID (16) */
1236 +#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 63 /* Linux CLK ID (17) */
1237 +#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 64 /* Linux CLK ID (18) */
1238 +/* mtk_gate */
1239 +#define CK_INFRA_66M_GPT_BCK (65 - GATE_OFFSET) /* Linux CLK ID (19) */
1240 +#define CK_INFRA_66M_PWM_HCK (66 - GATE_OFFSET) /* Linux CLK ID (20) */
1241 +#define CK_INFRA_66M_PWM_BCK (67 - GATE_OFFSET) /* Linux CLK ID (21) */
1242 +#define CK_INFRA_66M_PWM_CK1 (68 - GATE_OFFSET) /* Linux CLK ID (22) */
1243 +#define CK_INFRA_66M_PWM_CK2 (69 - GATE_OFFSET) /* Linux CLK ID (23) */
1244 +#define CK_INFRA_66M_PWM_CK3 (70 - GATE_OFFSET) /* Linux CLK ID (24) */
1245 +#define CK_INFRA_66M_PWM_CK4 (71 - GATE_OFFSET) /* Linux CLK ID (25) */
1246 +#define CK_INFRA_66M_PWM_CK5 (72 - GATE_OFFSET) /* Linux CLK ID (26) */
1247 +#define CK_INFRA_66M_PWM_CK6 (73 - GATE_OFFSET) /* Linux CLK ID (27) */
1248 +#define CK_INFRA_66M_PWM_CK7 (74 - GATE_OFFSET) /* Linux CLK ID (28) */
1249 +#define CK_INFRA_66M_PWM_CK8 (75 - GATE_OFFSET) /* Linux CLK ID (29) */
1250 +#define CK_INFRA_133M_CQDMA_BCK (76 - GATE_OFFSET) /* Linux CLK ID (30) */
1251 +#define CK_INFRA_66M_AUD_SLV_BCK (77 - GATE_OFFSET) /* Linux CLK ID (31) */
1252 +#define CK_INFRA_AUD_26M (78 - GATE_OFFSET) /* Linux CLK ID (32) */
1253 +#define CK_INFRA_AUD_L (79 - GATE_OFFSET) /* Linux CLK ID (33) */
1254 +#define CK_INFRA_AUD_AUD (80 - GATE_OFFSET) /* Linux CLK ID (34) */
1255 +#define CK_INFRA_AUD_EG2 (81 - GATE_OFFSET) /* Linux CLK ID (35) */
1256 +#define CK_INFRA_DRAMC_F26M (82 - GATE_OFFSET) /* Linux CLK ID (36) */
1257 +#define CK_INFRA_133M_DBG_ACKM (83 - GATE_OFFSET) /* Linux CLK ID (37) */
1258 +#define CK_INFRA_66M_AP_DMA_BCK (84 - GATE_OFFSET) /* Linux CLK ID (38) */
1259 +#define CK_INFRA_66M_SEJ_BCK (85 - GATE_OFFSET) /* Linux CLK ID (39) */
1260 +#define CK_INFRA_PRE_CK_SEJ_F13M (86 - GATE_OFFSET) /* Linux CLK ID (40) */
1261 +#define CK_INFRA_66M_TRNG (87 - GATE_OFFSET) /* Linux CLK ID (41) */
1262 +#define CK_INFRA_26M_THERM_SYSTEM (88 - GATE_OFFSET) /* Linux CLK ID (42) */
1263 +#define CK_INFRA_I2C_BCK (89 - GATE_OFFSET) /* Linux CLK ID (43) */
1264 +#define CK_INFRA_66M_UART0_PCK (90 - GATE_OFFSET) /* Linux CLK ID (44) */
1265 +#define CK_INFRA_66M_UART1_PCK (91 - GATE_OFFSET) /* Linux CLK ID (45) */
1266 +#define CK_INFRA_66M_UART2_PCK (92 - GATE_OFFSET) /* Linux CLK ID (46) */
1267 +#define CK_INFRA_52M_UART0_CK (93 - GATE_OFFSET) /* Linux CLK ID (47) */
1268 +#define CK_INFRA_52M_UART1_CK (94 - GATE_OFFSET) /* Linux CLK ID (48) */
1269 +#define CK_INFRA_52M_UART2_CK (95 - GATE_OFFSET) /* Linux CLK ID (49) */
1270 +#define CK_INFRA_NFI (96 - GATE_OFFSET) /* Linux CLK ID (50) */
1271 +#define CK_INFRA_SPINFI (97 - GATE_OFFSET) /* Linux CLK ID (51) */
1272 +#define CK_INFRA_66M_NFI_HCK (98 - GATE_OFFSET) /* Linux CLK ID (52) */
1273 +#define CK_INFRA_104M_SPI0 (99 - GATE_OFFSET) /* Linux CLK ID (53) */
1274 +#define CK_INFRA_104M_SPI1 (100 - GATE_OFFSET) /* Linux CLK ID (54) */
1275 +#define CK_INFRA_104M_SPI2_BCK (101 - GATE_OFFSET) /* Linux CLK ID (55) */
1276 +#define CK_INFRA_66M_SPI0_HCK (102 - GATE_OFFSET) /* Linux CLK ID (56) */
1277 +#define CK_INFRA_66M_SPI1_HCK (103 - GATE_OFFSET) /* Linux CLK ID (57) */
1278 +#define CK_INFRA_66M_SPI2_HCK (104 - GATE_OFFSET) /* Linux CLK ID (58) */
1279 +#define CK_INFRA_66M_FLASHIF_AXI (105 - GATE_OFFSET) /* Linux CLK ID (59) */
1280 +#define CK_INFRA_RTC (106 - GATE_OFFSET) /* Linux CLK ID (60) */
1281 +#define CK_INFRA_26M_ADC_BCK (107 - GATE_OFFSET) /* Linux CLK ID (61) */
1282 +#define CK_INFRA_RC_ADC (108 - GATE_OFFSET) /* Linux CLK ID (62) */
1283 +#define CK_INFRA_MSDC400 (109 - GATE_OFFSET) /* Linux CLK ID (63) */
1284 +#define CK_INFRA_MSDC2_HCK (110 - GATE_OFFSET) /* Linux CLK ID (64) */
1285 +#define CK_INFRA_133M_MSDC_0_HCK (111 - GATE_OFFSET) /* Linux CLK ID (65) */
1286 +#define CK_INFRA_66M_MSDC_0_HCK (112 - GATE_OFFSET) /* Linux CLK ID (66) */
1287 +#define CK_INFRA_133M_CPUM_BCK (113 - GATE_OFFSET) /* Linux CLK ID (67) */
1288 +#define CK_INFRA_BIST2FPC (114 - GATE_OFFSET) /* Linux CLK ID (68) */
1289 +#define CK_INFRA_I2C_X16W_MCK_CK_P1 (115 - GATE_OFFSET) /* Linux CLK ID (69) */
1290 +#define CK_INFRA_I2C_X16W_PCK_CK_P1 (116 - GATE_OFFSET) /* Linux CLK ID (70) */
1291 +#define CK_INFRA_133M_USB_HCK (117 - GATE_OFFSET) /* Linux CLK ID (71) */
1292 +#define CK_INFRA_133M_USB_HCK_CK_P1 (118 - GATE_OFFSET) /* Linux CLK ID (72) */
1293 +#define CK_INFRA_66M_USB_HCK (119 - GATE_OFFSET) /* Linux CLK ID (73) */
1294 +#define CK_INFRA_66M_USB_HCK_CK_P1 (120 - GATE_OFFSET) /* Linux CLK ID (74) */
1295 +#define CK_INFRA_USB_SYS (121 - GATE_OFFSET) /* Linux CLK ID (75) */
1296 +#define CK_INFRA_USB_SYS_CK_P1 (122 - GATE_OFFSET) /* Linux CLK ID (76) */
1297 +#define CK_INFRA_USB_REF (123 - GATE_OFFSET) /* Linux CLK ID (77) */
1298 +#define CK_INFRA_USB_CK_P1 (124 - GATE_OFFSET) /* Linux CLK ID (78) */
1299 +#define CK_INFRA_USB_FRMCNT (125 - GATE_OFFSET) /* Linux CLK ID (79) */
1300 +#define CK_INFRA_USB_FRMCNT_CK_P1 (126 - GATE_OFFSET) /* Linux CLK ID (80) */
1301 +#define CK_INFRA_USB_PIPE (127 - GATE_OFFSET) /* Linux CLK ID (81) */
1302 +#define CK_INFRA_USB_PIPE_CK_P1 (128 - GATE_OFFSET) /* Linux CLK ID (82) */
1303 +#define CK_INFRA_USB_UTMI (129 - GATE_OFFSET) /* Linux CLK ID (83) */
1304 +#define CK_INFRA_USB_UTMI_CK_P1 (130 - GATE_OFFSET) /* Linux CLK ID (84) */
1305 +#define CK_INFRA_USB_XHCI (131 - GATE_OFFSET) /* Linux CLK ID (85) */
1306 +#define CK_INFRA_USB_XHCI_CK_P1 (132 - GATE_OFFSET) /* Linux CLK ID (86) */
1307 +#define CK_INFRA_PCIE_GFMUX_TL_P0 (133 - GATE_OFFSET) /* Linux CLK ID (87) */
1308 +#define CK_INFRA_PCIE_GFMUX_TL_P1 (134 - GATE_OFFSET) /* Linux CLK ID (88) */
1309 +#define CK_INFRA_PCIE_GFMUX_TL_P2 (135 - GATE_OFFSET) /* Linux CLK ID (89) */
1310 +#define CK_INFRA_PCIE_GFMUX_TL_P3 (136 - GATE_OFFSET) /* Linux CLK ID (90) */
1311 +#define CK_INFRA_PCIE_PIPE_P0 (137 - GATE_OFFSET) /* Linux CLK ID (91) */
1312 +#define CK_INFRA_PCIE_PIPE_P1 (138 - GATE_OFFSET) /* Linux CLK ID (92) */
1313 +#define CK_INFRA_PCIE_PIPE_P2 (139 - GATE_OFFSET) /* Linux CLK ID (93) */
1314 +#define CK_INFRA_PCIE_PIPE_P3 (140 - GATE_OFFSET) /* Linux CLK ID (94) */
1315 +#define CK_INFRA_133M_PCIE_CK_P0 (141 - GATE_OFFSET) /* Linux CLK ID (95) */
1316 +#define CK_INFRA_133M_PCIE_CK_P1 (142 - GATE_OFFSET) /* Linux CLK ID (96) */
1317 +#define CK_INFRA_133M_PCIE_CK_P2 (143 - GATE_OFFSET) /* Linux CLK ID (97) */
1318 +#define CK_INFRA_133M_PCIE_CK_P3 (144 - GATE_OFFSET) /* Linux CLK ID (98) */
1319 +#define CK_INFRA_PCIE_PERI_26M_CK_P0 (145 - GATE_OFFSET) /* Linux CLK ID (99) */
1320 +#define CK_INFRA_PCIE_PERI_26M_CK_P1 \
1321 + (146 - GATE_OFFSET) /* Linux CLK ID (100) */
1322 +#define CK_INFRA_PCIE_PERI_26M_CK_P2 \
1323 + (147 - GATE_OFFSET) /* Linux CLK ID (101) */
1324 +#define CK_INFRA_PCIE_PERI_26M_CK_P3 \
1325 + (148 - GATE_OFFSET) /* Linux CLK ID (102) */
1326 +
1327 +/* TOPCKGEN */
1328 +/* mtk_fixed_factor */
1329 +#define CK_TOP_CB_CKSQ_40M 0 /* Linux CLK ID (74) */
1330 +#define CK_TOP_CB_M_416M 1 /* Linux CLK ID (75) */
1331 +#define CK_TOP_CB_M_D2 2 /* Linux CLK ID (76) */
1332 +#define CK_TOP_M_D3_D2 3 /* Linux CLK ID (77) */
1333 +#define CK_TOP_CB_M_D4 4 /* Linux CLK ID (78) */
1334 +#define CK_TOP_CB_M_D8 5 /* Linux CLK ID (79) */
1335 +#define CK_TOP_M_D8_D2 6 /* Linux CLK ID (80) */
1336 +#define CK_TOP_CB_MM_720M 7 /* Linux CLK ID (81) */
1337 +#define CK_TOP_CB_MM_D2 8 /* Linux CLK ID (82) */
1338 +#define CK_TOP_CB_MM_D3_D5 9 /* Linux CLK ID (83) */
1339 +#define CK_TOP_CB_MM_D4 10 /* Linux CLK ID (84) */
1340 +#define CK_TOP_MM_D6_D2 11 /* Linux CLK ID (85) */
1341 +#define CK_TOP_CB_MM_D8 12 /* Linux CLK ID (86) */
1342 +#define CK_TOP_CB_APLL2_196M 13 /* Linux CLK ID (87) */
1343 +#define CK_TOP_CB_APLL2_D4 14 /* Linux CLK ID (88) */
1344 +#define CK_TOP_CB_NET1_D4 15 /* Linux CLK ID (89) */
1345 +#define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */
1346 +#define CK_TOP_NET1_D5_D2 17 /* Linux CLK ID (91) */
1347 +#define CK_TOP_NET1_D5_D4 18 /* Linux CLK ID (92) */
1348 +#define CK_TOP_CB_NET1_D8 19 /* Linux CLK ID (93) */
1349 +#define CK_TOP_NET1_D8_D2 20 /* Linux CLK ID (94) */
1350 +#define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */
1351 +#define CK_TOP_NET1_D8_D8 22 /* Linux CLK ID (96) */
1352 +#define CK_TOP_NET1_D8_D16 23 /* Linux CLK ID (97) */
1353 +#define CK_TOP_CB_NET2_800M 24 /* Linux CLK ID (98) */
1354 +#define CK_TOP_CB_NET2_D2 25 /* Linux CLK ID (99) */
1355 +#define CK_TOP_CB_NET2_D4 26 /* Linux CLK ID (100) */
1356 +#define CK_TOP_NET2_D4_D4 27 /* Linux CLK ID (101) */
1357 +#define CK_TOP_NET2_D4_D8 28 /* Linux CLK ID (102) */
1358 +#define CK_TOP_CB_NET2_D6 29 /* Linux CLK ID (103) */
1359 +#define CK_TOP_CB_NET2_D8 30 /* Linux CLK ID (104) */
1360 +#define CK_TOP_CB_WEDMCU_208M 31 /* Linux CLK ID (105) */
1361 +#define CK_TOP_CB_SGM_325M 32 /* Linux CLK ID (106) */
1362 +#define CK_TOP_CB_NETSYS_850M 33 /* Linux CLK ID (107) */
1363 +#define CK_TOP_CB_MSDC_400M 34 /* Linux CLK ID (108) */
1364 +#define CK_TOP_CKSQ_40M_D2 35 /* Linux CLK ID (109) */
1365 +#define CK_TOP_CB_RTC_32K 36 /* Linux CLK ID (110) */
1366 +#define CK_TOP_CB_RTC_32P7K 37 /* Linux CLK ID (111) */
1367 +#define CK_TOP_INFRA_F32K 38 /* Linux CLK ID (112) */
1368 +#define CK_TOP_CKSQ_SRC 39 /* Linux CLK ID (113) */
1369 +#define CK_TOP_NETSYS_2X 40 /* Linux CLK ID (114) */
1370 +#define CK_TOP_NETSYS_GSW 41 /* Linux CLK ID (115) */
1371 +#define CK_TOP_NETSYS_WED_MCU 42 /* Linux CLK ID (116) */
1372 +#define CK_TOP_EIP197 43 /* Linux CLK ID (117) */
1373 +#define CK_TOP_EMMC_250M 44 /* Linux CLK ID (118) */
1374 +#define CK_TOP_EMMC_400M 45 /* Linux CLK ID (119) */
1375 +#define CK_TOP_SPI 46 /* Linux CLK ID (120) */
1376 +#define CK_TOP_SPIM_MST 47 /* Linux CLK ID (121) */
1377 +#define CK_TOP_NFI1X 48 /* Linux CLK ID (122) */
1378 +#define CK_TOP_SPINFI_BCK 49 /* Linux CLK ID (123) */
1379 +#define CK_TOP_I2C_BCK 50 /* Linux CLK ID (124) */
1380 +#define CK_TOP_USB_SYS 51 /* Linux CLK ID (125) */
1381 +#define CK_TOP_USB_SYS_P1 52 /* Linux CLK ID (126) */
1382 +#define CK_TOP_USB_XHCI 53 /* Linux CLK ID (127) */
1383 +#define CK_TOP_USB_XHCI_P1 54 /* Linux CLK ID (128) */
1384 +#define CK_TOP_USB_FRMCNT 55 /* Linux CLK ID (129) */
1385 +#define CK_TOP_USB_FRMCNT_P1 56 /* Linux CLK ID (130) */
1386 +#define CK_TOP_AUD 57 /* Linux CLK ID (131) */
1387 +#define CK_TOP_A1SYS 58 /* Linux CLK ID (132) */
1388 +#define CK_TOP_AUD_L 59 /* Linux CLK ID (133) */
1389 +#define CK_TOP_A_TUNER 60 /* Linux CLK ID (134) */
1390 +#define CK_TOP_SYSAXI 61 /* Linux CLK ID (135) */
1391 +#define CK_TOP_INFRA_F26M 62 /* Linux CLK ID (136) */
1392 +#define CK_TOP_USB_REF 63 /* Linux CLK ID (137) */
1393 +#define CK_TOP_USB_CK_P1 64 /* Linux CLK ID (138) */
1394 +/* mtk_mux */
1395 +#define CK_TOP_NETSYS_SEL 65 /* Linux CLK ID (0) */
1396 +#define CK_TOP_NETSYS_500M_SEL 66 /* Linux CLK ID (1) */
1397 +#define CK_TOP_NETSYS_2X_SEL 67 /* Linux CLK ID (2) */
1398 +#define CK_TOP_NETSYS_GSW_SEL 68 /* Linux CLK ID (3) */
1399 +#define CK_TOP_ETH_GMII_SEL 69 /* Linux CLK ID (4) */
1400 +#define CK_TOP_NETSYS_MCU_SEL 70 /* Linux CLK ID (5) */
1401 +#define CK_TOP_NETSYS_PAO_2X_SEL 71 /* Linux CLK ID (6) */
1402 +#define CK_TOP_EIP197_SEL 72 /* Linux CLK ID (7) */
1403 +#define CK_TOP_AXI_INFRA_SEL 73 /* Linux CLK ID (8) */
1404 +#define CK_TOP_UART_SEL 74 /* Linux CLK ID (9) */
1405 +#define CK_TOP_EMMC_250M_SEL 75 /* Linux CLK ID (10) */
1406 +#define CK_TOP_EMMC_400M_SEL 76 /* Linux CLK ID (11) */
1407 +#define CK_TOP_SPI_SEL 77 /* Linux CLK ID (12) */
1408 +#define CK_TOP_SPIM_MST_SEL 78 /* Linux CLK ID (13) */
1409 +#define CK_TOP_NFI1X_SEL 79 /* Linux CLK ID (14) */
1410 +#define CK_TOP_SPINFI_SEL 80 /* Linux CLK ID (15) */
1411 +#define CK_TOP_PWM_SEL 81 /* Linux CLK ID (16) */
1412 +#define CK_TOP_I2C_SEL 82 /* Linux CLK ID (17) */
1413 +#define CK_TOP_PCIE_MBIST_250M_SEL 83 /* Linux CLK ID (18) */
1414 +#define CK_TOP_PEXTP_TL_SEL 84 /* Linux CLK ID (19) */
1415 +#define CK_TOP_PEXTP_TL_P1_SEL 85 /* Linux CLK ID (20) */
1416 +#define CK_TOP_PEXTP_TL_P2_SEL 86 /* Linux CLK ID (21) */
1417 +#define CK_TOP_PEXTP_TL_P3_SEL 87 /* Linux CLK ID (22) */
1418 +#define CK_TOP_USB_SYS_SEL 88 /* Linux CLK ID (23) */
1419 +#define CK_TOP_USB_SYS_P1_SEL 89 /* Linux CLK ID (24) */
1420 +#define CK_TOP_USB_XHCI_SEL 90 /* Linux CLK ID (25) */
1421 +#define CK_TOP_USB_XHCI_P1_SEL 91 /* Linux CLK ID (26) */
1422 +#define CK_TOP_USB_FRMCNT_SEL 92 /* Linux CLK ID (27) */
1423 +#define CK_TOP_USB_FRMCNT_P1_SEL 93 /* Linux CLK ID (28) */
1424 +#define CK_TOP_AUD_SEL 94 /* Linux CLK ID (29) */
1425 +#define CK_TOP_A1SYS_SEL 95 /* Linux CLK ID (30) */
1426 +#define CK_TOP_AUD_L_SEL 96 /* Linux CLK ID (31) */
1427 +#define CK_TOP_A_TUNER_SEL 97 /* Linux CLK ID (32) */
1428 +#define CK_TOP_SSPXTP_SEL 98 /* Linux CLK ID (33) */
1429 +#define CK_TOP_USB_PHY_SEL 99 /* Linux CLK ID (34) */
1430 +#define CK_TOP_USXGMII_SBUS_0_SEL 100 /* Linux CLK ID (35) */
1431 +#define CK_TOP_USXGMII_SBUS_1_SEL 101 /* Linux CLK ID (36) */
1432 +#define CK_TOP_SGM_0_SEL 102 /* Linux CLK ID (37) */
1433 +#define CK_TOP_SGM_SBUS_0_SEL 103 /* Linux CLK ID (38) */
1434 +#define CK_TOP_SGM_1_SEL 104 /* Linux CLK ID (39) */
1435 +#define CK_TOP_SGM_SBUS_1_SEL 105 /* Linux CLK ID (40) */
1436 +#define CK_TOP_XFI_PHY_0_XTAL_SEL 106 /* Linux CLK ID (41) */
1437 +#define CK_TOP_XFI_PHY_1_XTAL_SEL 107 /* Linux CLK ID (42) */
1438 +#define CK_TOP_SYSAXI_SEL 108 /* Linux CLK ID (43) */
1439 +#define CK_TOP_SYSAPB_SEL 109 /* Linux CLK ID (44) */
1440 +#define CK_TOP_ETH_REFCK_50M_SEL 110 /* Linux CLK ID (45) */
1441 +#define CK_TOP_ETH_SYS_200M_SEL 111 /* Linux CLK ID (46) */
1442 +#define CK_TOP_ETH_SYS_SEL 112 /* Linux CLK ID (47) */
1443 +#define CK_TOP_ETH_XGMII_SEL 113 /* Linux CLK ID (48) */
1444 +#define CK_TOP_BUS_TOPS_SEL 114 /* Linux CLK ID (49) */
1445 +#define CK_TOP_NPU_TOPS_SEL 115 /* Linux CLK ID (50) */
1446 +#define CK_TOP_DRAMC_SEL 116 /* Linux CLK ID (51) */
1447 +#define CK_TOP_DRAMC_MD32_SEL 117 /* Linux CLK ID (52) */
1448 +#define CK_TOP_INFRA_F26M_SEL 118 /* Linux CLK ID (53) */
1449 +#define CK_TOP_PEXTP_P0_SEL 119 /* Linux CLK ID (54) */
1450 +#define CK_TOP_PEXTP_P1_SEL 120 /* Linux CLK ID (55) */
1451 +#define CK_TOP_PEXTP_P2_SEL 121 /* Linux CLK ID (56) */
1452 +#define CK_TOP_PEXTP_P3_SEL 122 /* Linux CLK ID (57) */
1453 +#define CK_TOP_DA_XTP_GLB_P0_SEL 123 /* Linux CLK ID (58) */
1454 +#define CK_TOP_DA_XTP_GLB_P1_SEL 124 /* Linux CLK ID (59) */
1455 +#define CK_TOP_DA_XTP_GLB_P2_SEL 125 /* Linux CLK ID (60) */
1456 +#define CK_TOP_DA_XTP_GLB_P3_SEL 126 /* Linux CLK ID (61) */
1457 +#define CK_TOP_CKM_SEL 127 /* Linux CLK ID (62) */
1458 +#define CK_TOP_DA_SELM_XTAL_SEL 128 /* Linux CLK ID (63) */
1459 +#define CK_TOP_PEXTP_SEL 129 /* Linux CLK ID (64) */
1460 +#define CK_TOP_TOPS_P2_26M_SEL 130 /* Linux CLK ID (65) */
1461 +#define CK_TOP_MCUSYS_BACKUP_625M_SEL 131 /* Linux CLK ID (66) */
1462 +#define CK_TOP_NETSYS_SYNC_250M_SEL 132 /* Linux CLK ID (67) */
1463 +#define CK_TOP_MACSEC_SEL 133 /* Linux CLK ID (68) */
1464 +#define CK_TOP_NETSYS_TOPS_400M_SEL 134 /* Linux CLK ID (69) */
1465 +#define CK_TOP_NETSYS_PPEFB_250M_SEL 135 /* Linux CLK ID (70) */
1466 +#define CK_TOP_NETSYS_WARP_SEL 136 /* Linux CLK ID (71) */
1467 +#define CK_TOP_ETH_MII_SEL 137 /* Linux CLK ID (72) */
1468 +#define CK_TOP_CK_NPU_SEL_CM_TOPS_SEL 138 /* Linux CLK ID (73) */
1469 +
1470 +/* APMIXEDSYS */
1471 +/* mtk_pll_data */
1472 +#define CK_APMIXED_NETSYSPLL 0
1473 +#define CK_APMIXED_MPLL 1
1474 +#define CK_APMIXED_MMPLL 2
1475 +#define CK_APMIXED_APLL2 3
1476 +#define CK_APMIXED_NET1PLL 4
1477 +#define CK_APMIXED_NET2PLL 5
1478 +#define CK_APMIXED_WEDMCUPLL 6
1479 +#define CK_APMIXED_SGMPLL 7
1480 +#define CK_APMIXED_ARM_B 8
1481 +#define CK_APMIXED_CCIPLL2_B 9
1482 +#define CK_APMIXED_USXGMIIPLL 10
1483 +#define CK_APMIXED_MSDCPLL 11
1484 +
1485 +/* ETHSYS ETH DMA */
1486 +/* mtk_gate */
1487 +#define CK_ETHDMA_FE_EN 0
1488 +
1489 +/* SGMIISYS_0 */
1490 +/* mtk_gate */
1491 +#define CK_SGM0_TX_EN 0
1492 +#define CK_SGM0_RX_EN 1
1493 +
1494 +/* SGMIISYS_1 */
1495 +/* mtk_gate */
1496 +#define CK_SGM1_TX_EN 0
1497 +#define CK_SGM1_RX_EN 1
1498 +
1499 +/* ETHWARP */
1500 +/* mtk_gate */
1501 +#define CK_ETHWARP_WOCPU2_EN 0
1502 +#define CK_ETHWARP_WOCPU1_EN 1
1503 +#define CK_ETHWARP_WOCPU0_EN 2
1504 +
1505 +#endif /* _DT_BINDINGS_CLK_MT7988_H */
Staging tree of Jo-Philipp Wich