package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch

   1 From a2df2df6fd1aec32572c7b30ccf5a184ec1763fd Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Wed, 27 Jul 2022 16:32:17 +0800
   4 Subject: [PATCH 56/71] mtd: spi-nor: add more flash ids
   5
   6 Add more spi-nor flash ids
   7
   8 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
   9 ---
  10  drivers/mtd/spi/spi-nor-core.c |  1 +
  11  drivers/mtd/spi/spi-nor-ids.c  | 23 ++++++++++++++++++++++-
  12  2 files changed, 23 insertions(+), 1 deletion(-)
  13
  14 --- a/drivers/mtd/spi/spi-nor-core.c
  15 +++ b/drivers/mtd/spi/spi-nor-core.c
  16 @@ -673,6 +673,7 @@ static int set_4byte(struct spi_nor *nor
  17         case SNOR_MFR_ISSI:
  18         case SNOR_MFR_MACRONIX:
  19         case SNOR_MFR_WINBOND:
  20 +       case SNOR_MFR_EON:
  21                 if (need_wren)
  22                         write_enable(nor);
  23
  24 --- a/drivers/mtd/spi/spi-nor-ids.c
  25 +++ b/drivers/mtd/spi/spi-nor-ids.c
  26 @@ -83,7 +83,8 @@ const struct flash_info spi_nor_ids[] =
  27         { INFO("en25q32b",   0x1c3016, 0, 64 * 1024,   64, 0) },
  28         { INFO("en25q64",    0x1c3017, 0, 64 * 1024,  128, SECT_4K) },
  29         { INFO("en25q128b",  0x1c3018, 0, 64 * 1024,  256, 0) },
  30 -       { INFO("en25qh128",  0x1c7018, 0, 64 * 1024,  256, 0) },
  31 +       { INFO("en25qh128",  0x1c7018, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  32 +       { INFO("en25qh256",  0x1c7019, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  33         { INFO("en25s64",    0x1c3817, 0, 64 * 1024,  128, SECT_4K) },
  34  #endif
  35  #ifdef CONFIG_SPI_FLASH_GIGADEVICE     /* GIGADEVICE */
  36 @@ -149,6 +150,11 @@ const struct flash_info spi_nor_ids[] =
  37         {INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K |
  38         SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
  39         {
  40 +               INFO("gd25q256", 0xc84019, 0, 64 * 1024, 512,
  41 +                       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  42 +                       SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  43 +       },
  44 +       {
  45                 INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
  46                         SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  47                         SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  48 @@ -468,6 +474,16 @@ const struct flash_info spi_nor_ids[] =
  49                         SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  50         },
  51         {
  52 +               INFO("w25q256jv", 0xef7019, 0, 64 * 1024, 512,
  53 +                       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  54 +                       SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  55 +       },
  56 +       {
  57 +               INFO("w25q512jv", 0xef7020, 0, 64 * 1024, 1024,
  58 +                       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  59 +                       SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  60 +       },
  61 +       {
  62                 INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256,
  63                         SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  64                         SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  65 @@ -517,6 +533,11 @@ const struct flash_info spi_nor_ids[] =
  66                         SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  67         },
  68         { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  69 +       {
  70 +               INFO("w25q512", 0xef4020, 0, 64 * 1024, 1024,
  71 +                       SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  72 +                       SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  73 +       },
  74         { INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  75         { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  76         { INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },