SUBTARGETS:=generic mips74k legacy
KERNEL_PATCHVER:=5.10
+KERNEL_TESTING_PATCHVER:=5.15
define Target/Description
Build firmware images for Broadcom based BCM47xx/53xx routers with MIPS CPU, *not* ARM.
CONFIG_ADM6996_PHY=y
-CONFIG_ARCH_BINFMT_ELF_STATE=y
-CONFIG_ARCH_CLOCKSOURCE_DATA=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
-CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
+CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MMAP_RND_BITS_MAX=15
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USE_BUILTIN_BSWAP=y
-CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
-CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_BCM47XX=y
CONFIG_BCM47XX_BCMA=y
CONFIG_BCM47XX_NVRAM=y
CONFIG_CPU_MIPSR2_IRQ_VI=y
CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CRYPTO_BLAKE2S=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_CSRC_R4K=y
-CONFIG_DMA_DIRECT_OPS=y
CONFIG_DMA_NONCOHERENT=y
-CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y
-CONFIG_DMA_NONCOHERENT_MMAP=y
-CONFIG_DMA_NONCOHERENT_OPS=y
# CONFIG_EARLY_PRINTK is not set
CONFIG_FIXED_PHY=y
+CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IOMAP=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
CONFIG_GPIO_WDT=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_ARCH_COMPILER_H=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
-CONFIG_HAVE_ARCH_TRACEHOOK=y
-CONFIG_HAVE_CBPF_JIT=y
-CONFIG_HAVE_CONTEXT_TRACKING=y
-CONFIG_HAVE_COPY_THREAD_TLS=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
-CONFIG_HAVE_DMA_CONTIGUOUS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
-CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
-CONFIG_HAVE_RSEQ=y
-CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
-CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
-CONFIG_HW_HAS_PCI=y
CONFIG_HW_RANDOM=y
CONFIG_HZ_PERIODIC=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
CONFIG_MEMFD_CREATE=y
CONFIG_MIGRATION=y
CONFIG_MIPS=y
CONFIG_MIPS_CLOCK_VSYSCALL=y
# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_MIPS_EBPF_JIT=y
CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_MIPS_LD_CAN_LINK_VDSO=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MTD_BCM47XXSFLASH=y
CONFIG_MTD_BCM47XX_PARTS=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_NAND_BCM47XXNFLASH=y
CONFIG_MTD_NAND_BRCMNAND=y
CONFIG_MTD_NAND_BRCMNAND_BCMA=y
+CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_PARSER_TRX=y
CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_RAW_NAND=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_SELFTESTS=y
CONFIG_NO_EXCEPT_FILL=y
CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
# CONFIG_OF is not set
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SRCU=y
CONFIG_SSB=y
CONFIG_SSB_B43_PCI_BRIDGE=y
CONFIG_SSB_SPROM=y
CONFIG_SWCONFIG=y
CONFIG_SWCONFIG_B53=y
-# CONFIG_SWCONFIG_B53_MMAP_DRIVER is not set
CONFIG_SWCONFIG_B53_PHY_DRIVER=y
CONFIG_SWCONFIG_B53_PHY_FIXUP=y
-# CONFIG_SWCONFIG_B53_SRAB_DRIVER is not set
CONFIG_SWPHY=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_SYS_HAS_CPU_BMIPS=y
CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
CONFIG_SYS_SUPPORTS_MIPS16=y
CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_TARGET_ISA_REV=1
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TINY_SRCU=y
CONFIG_USB_SUPPORT=y
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -2949,6 +2949,7 @@ int brcmnand_probe(struct platform_devic
+@@ -2998,6 +2998,7 @@ int brcmnand_probe(struct platform_devic
dev_set_drvdata(dev, ctrl);
ctrl->dev = dev;
init_completion(&ctrl->done);
init_completion(&ctrl->dma_done);
-@@ -3089,8 +3090,6 @@ int brcmnand_probe(struct platform_devic
+@@ -3138,8 +3139,6 @@ int brcmnand_probe(struct platform_devic
* interesting ways
*/
if (soc) {
struct brcmnand_controller {
struct device *dev;
struct nand_controller controller;
-@@ -589,15 +592,25 @@ enum {
+@@ -592,15 +595,25 @@ enum {
INTFC_CTLR_READY = BIT(31),
};
}
static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
-@@ -763,13 +776,18 @@ static inline void brcmnand_rmw_reg(stru
+@@ -766,13 +779,18 @@ static inline void brcmnand_rmw_reg(stru
static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
{
}
static inline void edu_writel(struct brcmnand_controller *ctrl,
-@@ -2951,6 +2969,12 @@ int brcmnand_probe(struct platform_devic
+@@ -3000,6 +3018,12 @@ int brcmnand_probe(struct platform_devic
ctrl->dev = dev;
ctrl->soc = soc;
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -2722,7 +2722,7 @@ static const struct nand_controller_ops
+@@ -2771,7 +2771,7 @@ static const struct nand_controller_ops
static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
{
struct brcmnand_controller *ctrl = host->ctrl;
struct mtd_info *mtd;
struct nand_chip *chip;
int ret;
-@@ -2730,7 +2730,7 @@ static int brcmnand_init_cs(struct brcmn
+@@ -2779,7 +2779,7 @@ static int brcmnand_init_cs(struct brcmn
ret = of_property_read_u32(dn, "reg", &host->cs);
if (ret) {
return -ENXIO;
}
-@@ -2739,13 +2739,13 @@ static int brcmnand_init_cs(struct brcmn
+@@ -2788,13 +2788,13 @@ static int brcmnand_init_cs(struct brcmn
nand_set_flash_node(chip, dn);
nand_set_controller_data(chip, host);
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -2719,7 +2719,7 @@ static const struct nand_controller_ops
+@@ -2768,7 +2768,7 @@ static const struct nand_controller_ops
.attach_chip = brcmnand_attach_chip,
};
{
struct brcmnand_controller *ctrl = host->ctrl;
struct device *dev = ctrl->dev;
-@@ -2728,16 +2728,9 @@ static int brcmnand_init_cs(struct brcmn
+@@ -2777,16 +2777,9 @@ static int brcmnand_init_cs(struct brcmn
int ret;
u16 cfg_offs;
nand_set_controller_data(chip, host);
mtd->name = devm_kasprintf(dev, GFP_KERNEL, "brcmnand.%d",
host->cs);
-@@ -3144,7 +3137,16 @@ int brcmnand_probe(struct platform_devic
+@@ -3193,7 +3186,16 @@ int brcmnand_probe(struct platform_devic
host->pdev = pdev;
host->ctrl = ctrl;
unsigned int dma_irq;
int nand_version;
-@@ -1590,7 +1590,7 @@ static bool brcmstb_nand_wait_for_comple
+@@ -1610,7 +1610,7 @@ static bool brcmstb_nand_wait_for_comple
bool err = false;
int sts;
/* switch to interrupt polling and PIO mode */
disable_ctrl_irqs(ctrl);
sts = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY,
-@@ -3095,33 +3095,29 @@ int brcmnand_probe(struct platform_devic
+@@ -3144,33 +3144,29 @@ int brcmnand_probe(struct platform_devic
}
/* IRQ */
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -3712,6 +3712,7 @@ L: linux-mtd@lists.infradead.org
+@@ -3900,6 +3900,7 @@ L: linux-mtd@lists.infradead.org
L: bcm-kernel-feedback-list@broadcom.com
S: Maintained
F: drivers/mtd/nand/raw/brcmnand/
+F: include/linux/platform_data/brcmnand.h
- BROADCOM SYSTEMPORT ETHERNET DRIVER
- M: Florian Fainelli <f.fainelli@gmail.com>
+ BROADCOM STB PCIE DRIVER
+ M: Jim Quinlan <jim2101024@gmail.com>
--- a/drivers/bcma/driver_chipcommon_nflash.c
+++ b/drivers/bcma/driver_chipcommon_nflash.c
@@ -7,18 +7,28 @@
#include <linux/err.h>
#include <linux/completion.h>
#include <linux/interrupt.h>
-@@ -2719,7 +2720,8 @@ static const struct nand_controller_ops
+@@ -2768,7 +2769,8 @@ static const struct nand_controller_ops
.attach_chip = brcmnand_attach_chip,
};
{
struct brcmnand_controller *ctrl = host->ctrl;
struct device *dev = ctrl->dev;
-@@ -2772,7 +2774,7 @@ static int brcmnand_init_cs(struct brcmn
+@@ -2821,7 +2823,7 @@ static int brcmnand_init_cs(struct brcmn
if (ret)
return ret;
if (ret)
nand_cleanup(chip);
-@@ -2941,17 +2943,15 @@ static int brcmnand_edu_setup(struct pla
+@@ -2990,17 +2992,15 @@ static int brcmnand_edu_setup(struct pla
int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
{
return -ENODEV;
ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
-@@ -2978,7 +2978,7 @@ int brcmnand_probe(struct platform_devic
+@@ -3027,7 +3027,7 @@ int brcmnand_probe(struct platform_devic
/* NAND register range */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ctrl->nand_base = devm_ioremap_resource(dev, res);
return PTR_ERR(ctrl->nand_base);
/* Enable clock before using NAND registers */
-@@ -3122,7 +3122,6 @@ int brcmnand_probe(struct platform_devic
+@@ -3171,7 +3171,6 @@ int brcmnand_probe(struct platform_devic
for_each_available_child_of_node(dn, child) {
if (of_device_is_compatible(child, "brcm,nandcs")) {
host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
if (!host) {
-@@ -3142,7 +3141,7 @@ int brcmnand_probe(struct platform_devic
+@@ -3191,7 +3190,7 @@ int brcmnand_probe(struct platform_devic
nand_set_flash_node(&host->chip, child);
if (ret) {
devm_kfree(dev, host);
continue; /* Try all chip-selects */
-@@ -3152,6 +3151,32 @@ int brcmnand_probe(struct platform_devic
+@@ -3201,6 +3200,32 @@ int brcmnand_probe(struct platform_devic
}
}
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -913,6 +913,12 @@ static void brcmnand_wr_corr_thresh(stru
+@@ -916,6 +916,12 @@ static void brcmnand_wr_corr_thresh(stru
static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
{
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
-@@ -236,6 +236,19 @@ config MTD_NAND_BRCMNAND
+@@ -208,6 +208,19 @@ config MTD_NAND_BRCMNAND
originally designed for Set-Top Box but is used on various BCM7xxx,
BCM3xxx, BCM63xxx, iProc/Cygnus and more.
+MODULE_DESCRIPTION("NAND controller driver glue for BCMA chips");
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -595,7 +595,11 @@ enum {
+@@ -598,7 +598,11 @@ enum {
static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl)
{
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
-@@ -28,6 +28,38 @@
+@@ -27,6 +27,38 @@
extern void (*r4k_blast_dcache)(void);
extern void (*r4k_blast_icache)(void);
/*
* This macro return a properly sign-extended address suitable as base address
* for indexed cache operations. Two issues here:
-@@ -61,6 +93,7 @@ static inline void flush_icache_line_ind
+@@ -60,6 +92,7 @@ static inline void flush_icache_line_ind
static inline void flush_dcache_line_indexed(unsigned long addr)
{
cache_op(Index_Writeback_Inv_D, addr);
}
-@@ -84,11 +117,13 @@ static inline void flush_icache_line(uns
+@@ -83,11 +116,13 @@ static inline void flush_icache_line(uns
static inline void flush_dcache_line(unsigned long addr)
{
cache_op(Hit_Invalidate_D, addr);
}
-@@ -161,6 +196,7 @@ static inline int protected_flush_icache
- #ifdef CONFIG_EVA
- return protected_cachee_op(Hit_Invalidate_I, addr);
- #else
+@@ -160,6 +195,7 @@ static inline int protected_flush_icache
+ return protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
+
+ default:
+ BCM4710_DUMMY_RREG();
return protected_cache_op(Hit_Invalidate_I, addr);
- #endif
}
-@@ -174,6 +210,7 @@ static inline int protected_flush_icache
+ }
+@@ -172,6 +208,7 @@ static inline int protected_flush_icache
*/
static inline int protected_writeback_dcache_line(unsigned long addr)
{
+ BCM4710_DUMMY_RREG();
- #ifdef CONFIG_EVA
- return protected_cachee_op(Hit_Writeback_Inv_D, addr);
- #else
-@@ -203,8 +240,51 @@ static inline void invalidate_tcache_pag
+ return protected_cache_op(Hit_Writeback_Inv_D, addr);
+ }
+
+@@ -193,8 +230,51 @@ static inline void invalidate_tcache_pag
unroll(times, _cache_op, insn, op, (addr) + (i++ * (lsize))); \
} while (0)
static inline void extra##blast_##pfx##cache##lsize(void) \
{ \
unsigned long start = INDEX_BASE; \
-@@ -214,6 +294,7 @@ static inline void extra##blast_##pfx##c
+@@ -204,6 +284,7 @@ static inline void extra##blast_##pfx##c
current_cpu_data.desc.waybit; \
unsigned long ws, addr; \
\
for (ws = 0; ws < ws_end; ws += ws_inc) \
for (addr = start; addr < end; addr += lsize * 32) \
cache_unroll(32, kernel_cache, indexop, \
-@@ -225,6 +306,7 @@ static inline void extra##blast_##pfx##c
+@@ -215,6 +296,7 @@ static inline void extra##blast_##pfx##c
unsigned long start = page; \
unsigned long end = page + PAGE_SIZE; \
\
do { \
cache_unroll(32, kernel_cache, hitop, start, lsize); \
start += lsize * 32; \
-@@ -241,32 +323,33 @@ static inline void extra##blast_##pfx##c
+@@ -231,32 +313,33 @@ static inline void extra##blast_##pfx##c
current_cpu_data.desc.waybit; \
unsigned long ws, addr; \
\
#define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
-@@ -291,58 +374,29 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
+@@ -281,65 +364,36 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
/* build blast_xxx_range, protected_blast_xxx_range */
- addr += lsize_8; \
- lines -= 8; \
- } \
-- \
++ unsigned long aend = (end - 1) & ~(lsize - 1); \
+ \
- if (lines & 0x4) { \
- prot##cache_op(hitop, addr); \
- prot##cache_op(hitop, addr + lsize); \
- prot##cache_op(hitop, addr + lsize_3); \
- addr += lsize_4; \
- } \
-+ unsigned long aend = (end - 1) & ~(lsize - 1); \
- \
+- \
- if (lines & 0x2) { \
- prot##cache_op(hitop, addr); \
- prot##cache_op(hitop, addr + lsize); \
} \
}
- #ifndef CONFIG_EVA
-
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
+-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, , BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, , , )
-
- #else
-
-@@ -376,15 +430,15 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache
- __BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
-
- #endif
--__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, , , )
__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
- protected_, loongson2_)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -38,6 +38,9 @@
- #include <asm/dma-coherence.h>
+ #include <asm/traps.h>
#include <asm/mips-cps.h>
+/* For enabling BCM4710 cache workarounds */
if (dc_lsize == 0)
r4k_blast_dcache = (void *)cache_noop;
else if (dc_lsize == 16)
-@@ -1818,6 +1830,17 @@ static void coherency_setup(void)
+@@ -1817,6 +1829,17 @@ static void coherency_setup(void)
* silly idea of putting something else there ...
*/
switch (current_cpu_type()) {
case CPU_R4000PC:
case CPU_R4000SC:
case CPU_R4000MC:
-@@ -1864,6 +1887,15 @@ void r4k_cache_init(void)
+@@ -1863,6 +1886,15 @@ void r4k_cache_init(void)
extern void build_copy_page(void);
struct cpuinfo_mips *c = ¤t_cpu_data;
probe_pcache();
probe_vcache();
setup_scache();
-@@ -1940,7 +1972,15 @@ void r4k_cache_init(void)
+@@ -1935,7 +1967,15 @@ void r4k_cache_init(void)
*/
local_r4k___flush_cache_all(NULL);
/*
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
-@@ -984,6 +984,9 @@ void build_get_pgde32(u32 **p, unsigned
+@@ -985,6 +985,9 @@ void build_get_pgde32(u32 **p, unsigned
uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
uasm_i_addu(p, ptr, tmp, ptr);
#else
UASM_i_LA_mostly(p, ptr, pgdc);
#endif
uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
-@@ -1345,6 +1348,9 @@ static void build_r4000_tlb_refill_handl
+@@ -1347,6 +1350,9 @@ static void build_r4000_tlb_refill_handl
#ifdef CONFIG_64BIT
build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
#else
build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
#endif
-@@ -1356,6 +1362,9 @@ static void build_r4000_tlb_refill_handl
+@@ -1358,6 +1364,9 @@ static void build_r4000_tlb_refill_handl
build_update_entries(&p, K0, K1);
build_tlb_write_entry(&p, &l, &r, tlb_random);
uasm_l_leave(&l, p);
uasm_i_eret(&p); /* return from trap */
}
#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
-@@ -2056,6 +2065,9 @@ build_r4000_tlbchange_handler_head(u32 *
+@@ -2059,6 +2068,9 @@ build_r4000_tlbchange_handler_head(u32 *
#ifdef CONFIG_64BIT
build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
#else
build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
#endif
-@@ -2102,6 +2114,9 @@ build_r4000_tlbchange_handler_tail(u32 *
+@@ -2105,6 +2117,9 @@ build_r4000_tlbchange_handler_tail(u32 *
build_tlb_write_entry(p, l, r, tlb_indexed);
uasm_l_leave(l, *p);
build_restore_work_registers(p);
---
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
-@@ -242,6 +242,9 @@
+@@ -240,6 +240,9 @@
#ifndef cpu_has_pindexed_dcache
#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
#endif
kunmap_atomic(vaddr);
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
-@@ -173,7 +173,7 @@ void copy_user_highpage(struct page *to,
+@@ -172,7 +172,7 @@ void copy_user_highpage(struct page *to,
void *vfrom, *vto;
vto = kmap_atomic(to);
page_mapcount(from) && !Page_dcache_dirty(from)) {
vfrom = kmap_coherent(from, vaddr);
copy_page(vto, vfrom);
-@@ -195,7 +195,7 @@ void copy_to_user_page(struct vm_area_st
+@@ -194,7 +194,7 @@ void copy_to_user_page(struct vm_area_st
struct page *page, unsigned long vaddr, void *dst, const void *src,
unsigned long len)
{
page_mapcount(page) && !Page_dcache_dirty(page)) {
void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
memcpy(vto, src, len);
-@@ -213,7 +213,7 @@ void copy_from_user_page(struct vm_area_
+@@ -212,7 +212,7 @@ void copy_from_user_page(struct vm_area_
struct page *page, unsigned long vaddr, void *dst, const void *src,
unsigned long len)
{
* These are used to make use of C type-checking..
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
-@@ -167,30 +167,6 @@ void kunmap_coherent(void)
+@@ -166,30 +166,6 @@ void kunmap_coherent(void)
preempt_enable();
}
+++ /dev/null
-From: b.sander
-Subject: [PATCH] pci: IDE fix
-
-These are standard probing messages when using pdc202xx_old:
-pdc202xx_old 0000:00:01.0: IDE controller (0x105a:0x0d30 rev 0x02)
-PCI: Enabling device 0000:00:01.0 (0004 -> 0007)
-PCI: Fixing up device 0000:00:01.0
-0000:00:01.0: (U)DMA Burst Bit DISABLED Primary PCI Mode Secondary PCI Mode.
-0000:00:01.0: FORCING BURST BIT 0x00->0x01 ACTIVE
-pdc202xx_old 0000:00:01.0: 100% native mode on irq 6
-
-With the default MAX_HWIFS value after above we get:
- ide2: BM-DMA at 0x0400-0x0407
- ide3: BM-DMA at 0x0408-0x040f
-Probing IDE interface ide2...
-hde: CF500, CFA DISK drive
-
-As you can see it's ide2 + ide3 and hde.
-
-With this patch applied we get:
- ide0: BM-DMA at 0x0400-0x0407
- ide1: BM-DMA at 0x0408-0x040f
-Probing IDE interface ide0...
-hda: CF500, CFA DISK drive
-
-This fixes OpenWrt ticket #7061: https://dev.openwrt.org/ticket/7061
----
---- a/include/linux/ide.h
-+++ b/include/linux/ide.h
-@@ -236,7 +236,11 @@ static inline void ide_std_init_ports(st
- hw->io_ports.ctl_addr = ctl_addr;
- }
-
-+#if defined CONFIG_BCM47XX
-+# define MAX_HWIFS 2
-+#else
- #define MAX_HWIFS 10
-+#endif
-
- /*
- * Now for the data we need to maintain per-drive: ide_drive_t
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
-@@ -4273,7 +4273,8 @@ static int tg3_power_down_prepare(struct
+@@ -4267,7 +4267,8 @@ static int tg3_power_down_prepare(struct
static void tg3_power_down(struct tg3 *tp)
{
pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
-@@ -1698,6 +1698,15 @@ config WDT_MTX1
+@@ -1664,6 +1664,15 @@ config WDT_MTX1
Hardware driver for the MTX-1 boards. This is a watchdog timer that
will reboot the machine after a 100 seconds timer expired.
+ 100 second timer expired and no process has written to
+ /dev/watchdog during that time.
+
- config PNX833X_WDT
- tristate "PNX833x Hardware Watchdog"
- depends on SOC_PNX8335
+ config SIBYTE_WDOG
+ tristate "Sibyte SoC hardware watchdog"
+ depends on CPU_SB1
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
-@@ -161,6 +161,7 @@ obj-$(CONFIG_RC32434_WDT) += rc32434_wdt
+@@ -159,6 +159,7 @@ obj-$(CONFIG_RC32434_WDT) += rc32434_wdt
obj-$(CONFIG_INDYDOG) += indydog.o
obj-$(CONFIG_JZ4740_WDT) += jz4740_wdt.o
obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o
+obj-$(CONFIG_GPIO_WDT) += old_gpio_wdt.o
- obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o
obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
+ obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
--- /dev/null
+++ b/drivers/watchdog/old_gpio_wdt.c
@@ -0,0 +1,301 @@
--- a/drivers/ssb/driver_pcicore.c
+++ b/drivers/ssb/driver_pcicore.c
-@@ -164,6 +164,10 @@ static int ssb_extpci_write_config(struc
+@@ -165,6 +165,10 @@ static int ssb_extpci_write_config(struc
WARN_ON(!pc->hostmode);
if (unlikely(len != 1 && len != 2 && len != 4))
goto out;
--- a/drivers/ssb/driver_pcicore.c
+++ b/drivers/ssb/driver_pcicore.c
-@@ -390,7 +390,7 @@ static void ssb_pcicore_init_hostmode(st
- set_io_port_base(ssb_pcicore_controller.io_map_base);
+@@ -394,7 +394,7 @@ static void ssb_pcicore_init_hostmode(st
/* Give some time to the PCI controller to configure itself with the new
- * values. Not waiting at this point causes crashes of the machine. */
+ * values. Not waiting at this point causes crashes of the machine.
+ */
- mdelay(10);
+ mdelay(300);
register_pci_controller(&ssb_pcicore_controller);
static int cfe_env;
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
-@@ -61,6 +61,9 @@ void (*_dma_cache_wback_inv)(unsigned lo
+@@ -63,6 +63,9 @@ void (*_dma_cache_wback_inv)(unsigned lo
void (*_dma_cache_wback)(unsigned long start, unsigned long size);
void (*_dma_cache_inv)(unsigned long start, unsigned long size);
projects / openwrt / staging / hauke.git / commitdiff