target/linux/rtl838x/files-5.4/arch/mips/include/asm/mach-rtl838x/mach-rtl838x.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
   4  * Copyright (C) 2020 B. Koblitz
   5  */
   6 #ifndef _MACH_RTL838X_H_
   7 #define _MACH_RTL838X_H_
   8
   9 /*
  10  * Register access macros
  11  */
  12
  13 #define RTL838X_SW_BASE         ((volatile void *) 0xBB000000)
  14
  15 #define rtl838x_r32(reg)        __raw_readl(reg)
  16 #define rtl838x_w32(val, reg)   __raw_writel(val, reg)
  17 #define rtl838x_w32_mask(clear, set, reg) rtl838x_w32((rtl838x_r32(reg) & ~(clear)) | (set), reg)
  18
  19 #define rtl838x_r8(reg)         __raw_readb(reg)
  20 #define rtl838x_w8(val, reg)    __raw_writeb(val, reg)
  21
  22 #define sw_r32(reg)             __raw_readl(RTL838X_SW_BASE + reg)
  23 #define sw_w32(val, reg)        __raw_writel(val, RTL838X_SW_BASE + reg)
  24 #define sw_w32_mask(clear, set, reg)    \
  25                                 sw_w32((sw_r32(reg) & ~(clear)) | (set), reg)
  26 #define sw_r64(reg)             ((((u64)__raw_readl(RTL838X_SW_BASE + reg)) << 32) | \
  27                                 __raw_readl(RTL838X_SW_BASE + reg + 4))
  28
  29 #define sw_w64(val, reg)        do { \
  30                                         __raw_writel((u32)((val) >> 32), RTL838X_SW_BASE + reg); \
  31                                         __raw_writel((u32)((val) & 0xffffffff), \
  32                                                         RTL838X_SW_BASE + reg + 4); \
  33                                 } while (0)
  34
  35 /*
  36  * SPRAM
  37  */
  38 #define RTL838X_ISPRAM_BASE     0x0
  39 #define RTL838X_DSPRAM_BASE     0x0
  40
  41 /*
  42  * IRQ Controller
  43  */
  44 #define RTL838X_IRQ_CPU_BASE    0
  45 #define RTL838X_IRQ_CPU_NUM     8
  46 #define RTL838X_IRQ_ICTL_BASE   (RTL838X_IRQ_CPU_BASE + RTL838X_IRQ_CPU_NUM)
  47 #define RTL838X_IRQ_ICTL_NUM    32
  48
  49 /*
  50  * MIPS32R2 counter
  51  */
  52 #define RTL838X_COMPARE_IRQ     (RTL838X_IRQ_CPU_BASE + 7)
  53
  54 /*
  55  *  ICTL
  56  *  Base address 0xb8003000UL
  57  */
  58 #define RTL838X_ICTL1_IRQ       (RTL838X_IRQ_CPU_BASE + 2)
  59 #define RTL838X_ICTL2_IRQ       (RTL838X_IRQ_CPU_BASE + 3)
  60 #define RTL838X_ICTL3_IRQ       (RTL838X_IRQ_CPU_BASE + 4)
  61 #define RTL838X_ICTL4_IRQ       (RTL838X_IRQ_CPU_BASE + 5)
  62 #define RTL838X_ICTL5_IRQ       (RTL838X_IRQ_CPU_BASE + 6)
  63
  64 #define GIMR                    (0x00)
  65 #define UART0_IE                (1 << 31)
  66 #define UART1_IE                (1 << 30)
  67 #define TC0_IE                  (1 << 29)
  68 #define TC1_IE                  (1 << 28)
  69 #define OCPTO_IE                (1 << 27)
  70 #define HLXTO_IE                (1 << 26)
  71 #define SLXTO_IE                (1 << 25)
  72 #define NIC_IE                  (1 << 24)
  73 #define GPIO_ABCD_IE            (1 << 23)
  74 #define GPIO_EFGH_IE            (1 << 22)
  75 #define RTC_IE                  (1 << 21)
  76 #define WDT_IP1_IE              (1 << 19)
  77 #define WDT_IP2_IE              (1 << 18)
  78
  79 #define GISR                    (0x04)
  80 #define UART0_IP                (1 << 31)
  81 #define UART1_IP                (1 << 30)
  82 #define TC0_IP                  (1 << 29)
  83 #define TC1_IP                  (1 << 28)
  84 #define OCPTO_IP                (1 << 27)
  85 #define HLXTO_IP                (1 << 26)
  86 #define SLXTO_IP                (1 << 25)
  87 #define NIC_IP                  (1 << 24)
  88 #define GPIO_ABCD_IP            (1 << 23)
  89 #define GPIO_EFGH_IP            (1 << 22)
  90 #define RTC_IP                  (1 << 21)
  91 #define WDT_IP1_IP              (1 << 19)
  92 #define WDT_IP2_IP              (1 << 18)
  93
  94 #define IRR0                    (0x08)
  95 #define IRR0_SETTING            ((UART0_RS  << 28) | \
  96                                  (UART1_RS  << 24) | \
  97                                  (TC0_RS    << 20) | \
  98                                  (TC1_RS    << 16) | \
  99                                  (OCPTO_RS  << 12) | \
 100                                  (HLXTO_RS  << 8)  | \
 101                                  (SLXTO_RS  << 4)  | \
 102                                  (NIC_RS    << 0)    \
 103                                 )
 104
 105 #define IRR1                    (0x0c)
 106
 107 #define IRR1_SETTING_RTL838X    ((GPIO_ABCD_RS << 28) | \
 108                                  (GPIO_EFGH_RS << 24) | \
 109                                  (RTC_RS       << 20) | \
 110                                  (SWCORE_RS    << 16)   \
 111                                 )
 112 #define IRR1_SETTING_RTL839X    ((GPIO_ABCD_RS << 28) | \
 113                                  (SWCORE_RS    << 16)   \
 114                                 )
 115
 116
 117 #define IRR2                    (0x10)
 118 #define IRR2_SETTING            0
 119
 120 #define IRR3                    (0x14)
 121 #define IRR3_SETTING            0
 122
 123 /* Interrupt Routing Selection */
 124 #define UART0_RS                2
 125 #define UART1_RS                1
 126 #define TC0_RS                  5
 127 #define TC1_RS                  1
 128 #define OCPTO_RS                1
 129 #define HLXTO_RS                1
 130 #define SLXTO_RS                1
 131 #define NIC_RS                  4
 132 #define GPIO_ABCD_RS            4
 133 #define GPIO_EFGH_RS            4
 134 #define RTC_RS                  4
 135 #define SWCORE_RS               3
 136 #define WDT_IP1_RS              4
 137 #define WDT_IP2_RS              5
 138
 139 /* Interrupt IRQ Assignments */
 140 #define UART0_IRQ               31
 141 #define UART1_IRQ               30
 142 #define TC0_IRQ                 29
 143 #define TC1_IRQ                 28
 144 #define OCPTO_IRQ               27
 145 #define HLXTO_IRQ               26
 146 #define SLXTO_IRQ               25
 147 #define NIC_IRQ                 24
 148 #define GPIO_ABCD_IRQ           23
 149 #define GPIO_EFGH_IRQ           22
 150 #define RTC_IRQ                 21
 151 #define SWCORE_IRQ              20
 152 #define WDT_IP1_IRQ             19
 153 #define WDT_IP2_IRQ             18
 154
 155 #define SYSTEM_FREQ             200000000
 156 #define RTL838X_UART0_BASE      ((volatile void *)(0xb8002000UL))
 157 #define RTL838X_UART0_BAUD      38400  /* ex. 19200 or 38400 or 57600 or 115200 */
 158 #define RTL838X_UART0_FREQ      (SYSTEM_FREQ - RTL838X_UART0_BAUD * 24)
 159 #define RTL838X_UART0_MAPBASE   0x18002000UL
 160 #define RTL838X_UART0_MAPSIZE   0x100
 161 #define RTL838X_UART0_IRQ       UART0_IRQ
 162
 163 #define RTL838X_UART1_BASE      ((volatile void *)(0xb8002100UL))
 164 #define RTL838X_UART1_BAUD      38400  /* ex. 19200 or 38400 or 57600 or 115200 */
 165 #define RTL838X_UART1_FREQ      (SYSTEM_FREQ - RTL838X_UART1_BAUD * 24)
 166 #define RTL838X_UART1_MAPBASE   0x18002100UL
 167 #define RTL838X_UART1_MAPSIZE   0x100
 168 #define RTL838X_UART1_IRQ       UART1_IRQ
 169
 170 #define UART0_RBR               (RTL838X_UART0_BASE + 0x000)
 171 #define UART0_THR               (RTL838X_UART0_BASE + 0x000)
 172 #define UART0_DLL               (RTL838X_UART0_BASE + 0x000)
 173 #define UART0_IER               (RTL838X_UART0_BASE + 0x004)
 174 #define UART0_DLM               (RTL838X_UART0_BASE + 0x004)
 175 #define UART0_IIR               (RTL838X_UART0_BASE + 0x008)
 176 #define UART0_FCR               (RTL838X_UART0_BASE + 0x008)
 177 #define UART0_LCR               (RTL838X_UART0_BASE + 0x00C)
 178 #define UART0_MCR               (RTL838X_UART0_BASE + 0x010)
 179 #define UART0_LSR               (RTL838X_UART0_BASE + 0x014)
 180
 181 #define UART1_RBR               (RTL838X_UART1_BASE + 0x000)
 182 #define UART1_THR               (RTL838X_UART1_BASE + 0x000)
 183 #define UART1_DLL               (RTL838X_UART1_BASE + 0x000)
 184 #define UART1_IER               (RTL838X_UART1_BASE + 0x004)
 185 #define UART1_DLM               (RTL838X_UART1_BASE + 0x004)
 186 #define UART1_IIR               (RTL838X_UART1_BASE + 0x008)
 187 #define UART1_FCR               (RTL838X_UART1_BASE + 0x008)
 188    #define FCR_EN               0x01
 189    #define FCR_RXRST            0x02
 190    #define XRST                 0x02
 191    #define FCR_TXRST            0x04
 192    #define TXRST                0x04
 193    #define FCR_DMA              0x08
 194    #define FCR_RTRG             0xC0
 195    #define CHAR_TRIGGER_01      0x00
 196    #define CHAR_TRIGGER_04      0x40
 197    #define CHAR_TRIGGER_08      0x80
 198    #define CHAR_TRIGGER_14      0xC0
 199 #define UART1_LCR               (RTL838X_UART1_BASE + 0x00C)
 200    #define LCR_WLN              0x03
 201    #define CHAR_LEN_5           0x00
 202    #define CHAR_LEN_6           0x01
 203    #define CHAR_LEN_7           0x02
 204    #define CHAR_LEN_8           0x03
 205    #define LCR_STB              0x04
 206    #define ONE_STOP             0x00
 207    #define TWO_STOP             0x04
 208    #define LCR_PEN              0x08
 209    #define PARITY_ENABLE        0x01
 210    #define PARITY_DISABLE       0x00
 211    #define LCR_EPS              0x30
 212    #define PARITY_ODD           0x00
 213    #define PARITY_EVEN          0x10
 214    #define PARITY_MARK          0x20
 215    #define PARITY_SPACE         0x30
 216    #define LCR_BRK              0x40
 217    #define LCR_DLAB             0x80
 218    #define DLAB                 0x80
 219 #define UART1_MCR               (RTL838X_UART1_BASE + 0x010)
 220 #define UART1_LSR               (RTL838X_UART1_BASE + 0x014)
 221    #define LSR_DR               0x01
 222    #define RxCHAR_AVAIL         0x01
 223    #define LSR_OE               0x02
 224    #define LSR_PE               0x04
 225    #define LSR_FE               0x08
 226    #define LSR_BI               0x10
 227    #define LSR_THRE             0x20
 228    #define TxCHAR_AVAIL         0x00
 229    #define TxCHAR_EMPTY         0x20
 230    #define LSR_TEMT             0x40
 231    #define LSR_RFE              0x80
 232
 233 /*
 234  *  Timer/counter for 8390/80/28 TC & MP chip
 235  */
 236 #define RTL838X_TIMER0_BASE     ((volatile void *)(0xb8003100UL))
 237 #define RTL838X_TIMER0_IRQ      RTL838X_TC0_EXT_IRQ
 238
 239 #define RTL8390TC_TC1DATA       (RTL838X_TIMER0_BASE + 0x04)
 240 #define RTL8390TC_TCD_OFFSET    8
 241 #define RTL8390TC_TC0CNT        (RTL838X_TIMER0_BASE + 0x08)
 242 #define RTL8390TC_TC1CNT        (RTL838X_TIMER0_BASE + 0x0C)
 243 #define RTL8390TC_TCCNR         (RTL838X_TIMER0_BASE + 0x10)
 244 #define RTL8390TC_TC0EN         (1 << 31)
 245 #define RTL8390TC_TC0MODE_TIMER (1 << 30)
 246 #define RTL8390TC_TC1EN         (1 << 29)
 247 #define RTL8390TC_TC1MODE_TIMER (1 << 28)
 248 #define RTL8390TC_TCIR          (RTL838X_TIMER0_BASE + 0x14)
 249 #define RTL8390TC_TC0IE         (1 << 31)
 250 #define RTL8390TC_TC1IE         (1 << 30)
 251 #define RTL8390TC_TC0IP         (1 << 29)
 252 #define RTL8390TC_TC1IP         (1 << 28)
 253 #define RTL8390TC_CDBR          (RTL838X_TIMER0_BASE + 0x18)
 254 #define RTL8390TC_DIVF_OFFSET   16
 255 #define RTL8390TC_WDTCNR        (RTL838X_TIMER0_BASE + 0x1C)
 256
 257 #define RTL8390MP_TC1DATA       (RTL838X_TIMER0_BASE + 0x10)
 258 #define RTL8390MP_TC0CNT        (RTL838X_TIMER0_BASE + 0x04)
 259 #define RTL8390MP_TC1CNT        (RTL838X_TIMER0_BASE + 0x14)
 260 #define RTL8390MP_TC0CTL        (RTL838X_TIMER0_BASE + 0x08)
 261 #define RTL8390MP_TC1CTL        (RTL838X_TIMER0_BASE + 0x18)
 262 #define RTL8390MP_TCEN          (1 << 28)
 263 #define RTL8390MP_TCMODE_TIMER  (1 << 24)
 264 #define RTL8390MP_TCDIV_FACTOR  (0xFFFF << 0)
 265 #define RTL8390MP_TC0INT        (RTL838X_TIMER0_BASE + 0xC)
 266 #define RTL8390MP_TC1INT        (RTL838X_TIMER0_BASE + 0x1C)
 267 #define RTL8390MP_TCIE          (1 << 20)
 268 #define RTL8390MP_TCIP          (1 << 16)
 269 #define RTL8390MP_WDTCNR        (RTL838X_TIMER0_BASE + 0x50)
 270
 271 #define RTL8380MP_TC0DATA       (RTL838X_TIMER0_BASE + 0x00)
 272 #define RTL8380MP_TC1DATA       (RTL838X_TIMER0_BASE + 0x10)
 273 #define RTL8380MP_TC0CNT        (RTL838X_TIMER0_BASE + 0x04)
 274 #define RTL8380MP_TC1CNT        (RTL838X_TIMER0_BASE + 0x14)
 275 #define RTL8380MP_TC0CTL        (RTL838X_TIMER0_BASE + 0x08)
 276 #define RTL8380MP_TC1CTL        (RTL838X_TIMER0_BASE + 0x18)
 277 #define RTL8380MP_TCEN          (1 << 28)
 278 #define RTL8380MP_TCMODE_TIMER  (1 << 24)
 279 #define RTL8380MP_TCDIV_FACTOR  (0xFFFF << 0)
 280 #define RTL8380MP_TC0INT        (RTL838X_TIMER0_BASE + 0xC)
 281 #define RTL8380MP_TC1INT        (RTL838X_TIMER0_BASE + 0x1C)
 282 #define RTL8380MP_TCIE          (1 << 20)
 283 #define RTL8380MP_TCIP          (1 << 16)
 284 #define RTL8380MP_WDTCNR        (RTL838X_TIMER0_BASE + 0x50)
 285
 286 #define DIVISOR_RTL8390         55
 287 #define DIVISOR_RTL8380         2500
 288 #define DIVISOR_MAX             16834
 289
 290 /*
 291  * Memory Controller
 292  */
 293 #define MC_MCR                  0xB8001000
 294 #define MC_MCR_VAL              0x00000000
 295
 296 #define MC_DCR                  0xB8001004
 297 #define MC_DCR0_VAL             0x54480000
 298
 299 #define MC_DTCR                 0xB8001008
 300 #define MC_DTCR_VAL             0xFFFF05C0
 301
 302 /*
 303  * GPIO
 304  */
 305 #define GPIO_CTRL_REG_BASE              ((volatile void *) 0xb8003500)
 306 #define RTL838X_GPIO_PABC_CNR           (GPIO_CTRL_REG_BASE + 0x0)
 307 #define RTL838X_GPIO_PABC_TYPE          (GPIO_CTRL_REG_BASE + 0x04)
 308 #define RTL838X_GPIO_PABC_DIR           (GPIO_CTRL_REG_BASE + 0x8)
 309 #define RTL838X_GPIO_PABC_DATA          (GPIO_CTRL_REG_BASE + 0xc)
 310 #define RTL838X_GPIO_PABC_ISR           (GPIO_CTRL_REG_BASE + 0x10)
 311 #define RTL838X_GPIO_PAB_IMR            (GPIO_CTRL_REG_BASE + 0x14)
 312 #define RTL838X_GPIO_PC_IMR             (GPIO_CTRL_REG_BASE + 0x18)
 313
 314 #define RTL838X_MODEL_NAME_INFO         (0x00D4)
 315 #define RTL839X_MODEL_NAME_INFO         (0x0FF0)
 316 #define RTL838X_LED_GLB_CTRL            (0xA000)
 317 #define RTL839X_LED_GLB_CTRL            (0x00E4)
 318 #define RTL838X_EXT_GPIO_DIR_0          (0xA08C)
 319 #define RTL838X_EXT_GPIO_DIR_1          (0xA090)
 320 #define RTL838X_EXT_GPIO_DATA_0         (0xA094)
 321 #define RTL838X_EXT_GPIO_DATA_1         (0xA098)
 322 #define RTL838X_EXT_GPIO_INDRT_ACCESS   (0xA09C)
 323 #define RTL838X_EXTRA_GPIO_CTRL         (0xA0E0)
 324 #define RTL838X_EXTRA_GPIO_DIR_0        (0xA0E4)
 325 #define RTL838X_EXTRA_GPIO_DIR_1        (0xA0E8)
 326 #define RTL838X_EXTRA_GPIO_DATA_0       (0xA0EC)
 327 #define RTL838X_EXTRA_GPIO_DATA_1       (0xA0F0)
 328 #define RTL838X_DMY_REG5                (0x0144)
 329 #define RTL838X_EXTRA_GPIO_CTRL         (0xA0E0)
 330
 331 #define RTL838X_GMII_INTF_SEL           (0x1000)
 332 #define RTL838X_IO_DRIVING_ABILITY_CTRL (0x1010)
 333
 334 #define RTL838X_GPIO_A7         31
 335 #define RTL838X_GPIO_A6         30
 336 #define RTL838X_GPIO_A5         29
 337 #define RTL838X_GPIO_A4         28
 338 #define RTL838X_GPIO_A3         27
 339 #define RTL838X_GPIO_A2         26
 340 #define RTL838X_GPIO_A1         25
 341 #define RTL838X_GPIO_A0         24
 342 #define RTL838X_GPIO_B7         23
 343 #define RTL838X_GPIO_B6         22
 344 #define RTL838X_GPIO_B5         21
 345 #define RTL838X_GPIO_B4         20
 346 #define RTL838X_GPIO_B3         19
 347 #define RTL838X_GPIO_B2         18
 348 #define RTL838X_GPIO_B1         17
 349 #define RTL838X_GPIO_B0         16
 350 #define RTL838X_GPIO_C7         15
 351 #define RTL838X_GPIO_C6         14
 352 #define RTL838X_GPIO_C5         13
 353 #define RTL838X_GPIO_C4         12
 354 #define RTL838X_GPIO_C3         11
 355 #define RTL838X_GPIO_C2         10
 356 #define RTL838X_GPIO_C1         9
 357 #define RTL838X_GPIO_C0         8
 358
 359 #define RTL838X_INT_RW_CTRL             (0x0058)
 360 #define RTL838X_EXT_VERSION             (0x00D0)
 361 #define RTL838X_PLL_CML_CTRL            (0x0FF8)
 362 #define RTL838X_STRAP_DBG               (0x100C)
 363
 364 /*
 365  * Reset
 366  */
 367 #define RGCR                            (0x1E70)
 368 #define RTL839X_RST_GLB_CTRL            (0x0014)
 369 #define RTL838X_RST_GLB_CTRL_1          (0x0040)
 370
 371 /* LED control by switch */
 372 #define RTL838X_LED_MODE_SEL            (0x1004)
 373 #define RTL838X_LED_MODE_CTRL           (0xA004)
 374 #define RTL838X_LED_P_EN_CTRL           (0xA008)
 375
 376 /* LED control by software */
 377 #define RTL838X_LED_SW_CTRL             (0xA00C)
 378 #define RTL838X_LED0_SW_P_EN_CTRL       (0xA010)
 379 #define RTL838X_LED1_SW_P_EN_CTRL       (0xA014)
 380 #define RTL838X_LED2_SW_P_EN_CTRL       (0xA018)
 381 #define RTL838X_LED_SW_P_CTRL(p)        (0xA01C + ((p) << 2))
 382
 383 #define RTL839X_MAC_EFUSE_CTRL          (0x02ac)
 384
 385 /*
 386  * MDIO via Realtek's SMI interface
 387  */
 388 #define RTL838X_SMI_GLB_CTRL            (0xa100)
 389 #define RTL838X_SMI_ACCESS_PHY_CTRL_0   (0xa1b8)
 390 #define RTL838X_SMI_ACCESS_PHY_CTRL_1   (0xa1bc)
 391 #define RTL838X_SMI_ACCESS_PHY_CTRL_2   (0xa1c0)
 392 #define RTL838X_SMI_ACCESS_PHY_CTRL_3   (0xa1c4)
 393 #define RTL838X_SMI_PORT0_5_ADDR_CTRL   (0xa1c8)
 394 #define RTL838X_SMI_POLL_CTRL           (0xa17c)
 395
 396 #define RTL839X_SMI_GLB_CTRL            (0x03f8)
 397 #define RTL839X_SMI_PORT_POLLING_CTRL   (0x03fc)
 398 #define RTL839X_PHYREG_ACCESS_CTRL      (0x03DC)
 399 #define RTL839X_PHYREG_CTRL             (0x03E0)
 400 #define RTL839X_PHYREG_PORT_CTRL(p)     (0x03E4 + ((p >> 5) << 2))
 401 #define RTL839X_PHYREG_DATA_CTRL        (0x03F0)
 402
 403 /*
 404  * Switch interrupts
 405  */
 406 #define RTL838X_IMR_GLB                 (0x1100)
 407 #define RTL838X_IMR_PORT_LINK_STS_CHG   (0x1104)
 408 #define RTL838X_ISR_GLB_SRC             (0x1148)
 409 #define RTL838X_ISR_PORT_LINK_STS_CHG   (0x114C)
 410 #define RTL839X_IMR_GLB                 (0x0064)
 411 #define RTL839X_IMR_PORT_LINK_STS_CHG   (0x0068)
 412 #define RTL839X_ISR_GLB_SRC             (0x009c)
 413 #define RTL839X_ISR_PORT_LINK_STS_CHG   (0x00a0)
 414
 415 /* Definition of family IDs */
 416 #define RTL8389_FAMILY_ID   (0x8389)
 417 #define RTL8328_FAMILY_ID   (0x8328)
 418 #define RTL8390_FAMILY_ID   (0x8390)
 419 #define RTL8350_FAMILY_ID   (0x8350)
 420 #define RTL8380_FAMILY_ID   (0x8380)
 421 #define RTL8330_FAMILY_ID   (0x8330)
 422
 423 struct rtl838x_soc_info {
 424         unsigned char *name;
 425         unsigned int id;
 426         unsigned int family;
 427         unsigned char *compatible;
 428         volatile void *sw_base;
 429         volatile void *icu_base;
 430 };
 431
 432 extern struct rtl838x_soc_info soc_info;
 433 extern struct mutex smi_lock;
 434
 435 void rtl838x_soc_detect(struct rtl838x_soc_info *i);
 436
 437 #endif   /* _MACH_RTL838X_H_ */