221da9ec0f6a3163177e01e799d6b8f36e49d010
[openwrt/staging/hauke.git] / target / linux / ramips / dts / mt7620a_linksys_e1700.dts
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2014 Imre Kaloz <kaloz@openwrt.org>
4 */
5
6 #include "mt7620a.dtsi"
7
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10
11 / {
12 compatible = "linksys,e1700", "ralink,mt7620a-soc";
13 model = "Linksys E1700";
14
15 aliases {
16 led-boot = &led_power;
17 led-failsafe = &led_power;
18 led-running = &led_power;
19 led-upgrade = &led_power;
20 };
21
22 keys {
23 compatible = "gpio-keys";
24
25 reset {
26 label = "reset";
27 gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
28 linux,code = <KEY_RESTART>;
29 };
30
31 wps {
32 label = "wps";
33 gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
34 linux,code = <KEY_WPS_BUTTON>;
35 };
36 };
37
38 leds {
39 compatible = "gpio-leds";
40
41 led_power: power {
42 label = "green:power";
43 gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
44 };
45
46 wan {
47 label = "green:wps";
48 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
49 };
50 };
51 };
52
53 &spi0 {
54 status = "okay";
55
56 flash@0 {
57 compatible = "jedec,spi-nor";
58 reg = <0>;
59 spi-max-frequency = <10000000>;
60
61 partitions {
62 compatible = "fixed-partitions";
63 #address-cells = <1>;
64 #size-cells = <1>;
65
66 partition@0 {
67 label = "u-boot";
68 reg = <0x0 0x30000>;
69 read-only;
70 };
71
72 partition@30000 {
73 label = "config";
74 reg = <0x30000 0x10000>;
75 read-only;
76 };
77
78 factory: partition@40000 {
79 compatible = "nvmem-cells";
80 label = "factory";
81 reg = <0x40000 0x10000>;
82 #address-cells = <1>;
83 #size-cells = <1>;
84 read-only;
85
86 eeprom_factory_0: eeprom@0 {
87 reg = <0x0 0x200>;
88 };
89
90 macaddr_factory_28: macaddr@28 {
91 reg = <0x28 0x6>;
92 };
93 };
94
95 partition@50000 {
96 compatible = "denx,uimage";
97 label = "firmware";
98 reg = <0x50000 0x7b0000>;
99 };
100 };
101 };
102 };
103
104 &state_default {
105 gpio {
106 groups = "i2c", "uartf";
107 function = "gpio";
108 };
109 };
110
111 &ethernet {
112 pinctrl-names = "default";
113 pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
114
115 nvmem-cells = <&macaddr_factory_28>;
116 nvmem-cell-names = "mac-address";
117
118 port@5 {
119 status = "okay";
120 mediatek,fixed-link = <1000 1 1 1>;
121 phy-mode = "rgmii";
122 };
123
124 mdio-bus {
125 status = "okay";
126
127 phy0: ethernet-phy@0 {
128 reg = <0>;
129 phy-mode = "rgmii";
130 };
131
132 phy1: ethernet-phy@1 {
133 reg = <1>;
134 phy-mode = "rgmii";
135 };
136
137 phy2: ethernet-phy@2 {
138 reg = <2>;
139 phy-mode = "rgmii";
140 };
141
142 phy3: ethernet-phy@3 {
143 reg = <3>;
144 phy-mode = "rgmii";
145 };
146
147 phy4: ethernet-phy@4 {
148 reg = <4>;
149 phy-mode = "rgmii";
150 };
151
152 phy1f: ethernet-phy@1f {
153 reg = <0x1f>;
154 phy-mode = "rgmii";
155 };
156 };
157 };
158
159 &gsw {
160 mediatek,ephy-base = /bits/ 8 <12>;
161 };
162
163 &wmac {
164 nvmem-cells = <&eeprom_factory_0>;
165 nvmem-cell-names = "eeprom";
166 };