ramips: mt7620a: convert to nvmem-layout
[openwrt/staging/hauke.git] / target / linux / ramips / dts / mt7620a_fon_fon2601.dts
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include "mt7620a.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "fon,fon2601", "ralink,mt7620a-soc";
10 model = "Fon FON2601";
11
12 aliases {
13 led-boot = &led_power;
14 led-failsafe = &led_power;
15 led-running = &led_power;
16 led-upgrade = &led_power;
17 };
18
19 leds {
20 compatible = "gpio-leds";
21
22 led_power: power_r {
23 label = "red:power";
24 gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
25 };
26
27 internet_g {
28 label = "green:internet";
29 gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
30 };
31
32 net_g {
33 label = "green:net";
34 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
35 };
36
37 wifi_g {
38 label = "green:wifi";
39 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
40 };
41 };
42
43 keys {
44 compatible = "gpio-keys";
45
46 reset {
47 label = "reset";
48 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
49 linux,code = <KEY_RESTART>;
50 };
51 };
52 };
53
54 &spi0 {
55 status = "okay";
56
57 flash@0 {
58 compatible = "jedec,spi-nor";
59 reg = <0>;
60 spi-max-frequency = <10000000>;
61
62 partitions {
63 compatible = "fixed-partitions";
64 #address-cells = <1>;
65 #size-cells = <1>;
66
67 partition@0 {
68 label = "u-boot";
69 reg = <0x0 0x30000>;
70 read-only;
71 };
72
73 partition@30000 {
74 label = "u-boot-env";
75 reg = <0x30000 0x10000>;
76 read-only;
77 };
78
79 factory: partition@40000 {
80 label = "factory";
81 reg = <0x40000 0x10000>;
82 read-only;
83
84 nvmem-layout {
85 compatible = "fixed-layout";
86 #address-cells = <1>;
87 #size-cells = <1>;
88
89 eeprom_factory_0: eeprom@0 {
90 reg = <0x0 0x200>;
91 };
92
93 eeprom_factory_8000: eeprom@8000 {
94 reg = <0x8000 0x200>;
95 };
96
97 macaddr_factory_4: macaddr@4 {
98 reg = <0x4 0x6>;
99 };
100 };
101 };
102
103 partition@50000 {
104 compatible = "openwrt,uimage", "denx,uimage";
105 openwrt,padding = <32>;
106 label = "firmware";
107 reg = <0x50000 0xf90000>;
108 };
109
110 partition@fe0000 {
111 label = "board_data";
112 reg = <0xfe0000 0x20000>;
113 read-only;
114 };
115 };
116 };
117 };
118
119 &state_default {
120 gpio {
121 groups = "i2c", "uartf";
122 function = "gpio";
123 };
124 nd_sd {
125 groups = "nd_sd";
126 function = "sd";
127 };
128 spi_cs {
129 groups = "spi refclk";
130 function = "spi refclk";
131 };
132 };
133
134 &ethernet {
135 pinctrl-names = "default";
136 pinctrl-0 = <&rgmii2_pins &mdio_pins>;
137
138 nvmem-cells = <&macaddr_factory_4>;
139 nvmem-cell-names = "mac-address";
140
141 port@4 {
142 status = "okay";
143 phy-handle = <&phy4>;
144 phy-mode = "rgmii";
145 };
146
147 mdio-bus {
148 status = "okay";
149
150 phy4: ethernet-phy@4 {
151 reg = <4>;
152 phy-mode = "rgmii";
153 };
154 };
155 };
156
157 &gsw {
158 mediatek,port4-gmac;
159 mediatek,ephy-base = /bits/ 8 <8>;
160 };
161
162 &wmac {
163 nvmem-cells = <&eeprom_factory_0>;
164 nvmem-cell-names = "eeprom";
165
166 pinctrl-names = "default", "pa_gpio";
167 pinctrl-0 = <&pa_pins>, <&wled_pins>;
168 pinctrl-1 = <&pa_gpio_pins>, <&wled_pins>;
169 };
170
171 &pcie {
172 status = "okay";
173 };
174 &pcie0 {
175 wifi@0,0 {
176 compatible = "pci14c3,7662";
177 reg = <0x0000 0 0 0 0>;
178 nvmem-cells = <&eeprom_factory_8000>;
179 nvmem-cell-names = "eeprom";
180 ieee80211-freq-limit = <5000000 6000000>;
181 };
182 };
183
184 &ehci {
185 status = "okay";
186 };
187
188 &ohci {
189 status = "okay";
190 };