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qualcommax: set default switch MAC modes
[openwrt/staging/hauke.git] / target / linux / qualcommax / files / arch / arm64 / boot / dts / qcom / ipq8074-ess.dtsi
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <dt-bindings/net/qcom-ipq-ess.h>
4
5 &clocks {
6 bias_pll_cc_clk {
7 compatible = "fixed-clock";
8 clock-frequency = <300000000>;
9 #clock-cells = <0>;
10 };
11
12 bias_pll_nss_noc_clk {
13 compatible = "fixed-clock";
14 clock-frequency = <416500000>;
15 #clock-cells = <0>;
16 };
17 };
18
19 &soc {
20 switch: ess-switch@3a000000 {
21 compatible = "qcom,ess-switch-ipq807x";
22 reg = <0x3a000000 0x1000000>;
23 switch_access_mode = "local bus";
24 switch_cpu_bmp = <ESS_PORT0>; /* cpu port bitmap */
25 switch_inner_bmp = <ESS_PORT7>; /*inner port bitmap*/
26 /* This is a special binding that controls how the malibu PHY are
27 * init. This value reflect the PHY addr of the first malibu PHY.
28 * Malibu PHY are in a bundle of 5 PHY.
29 * Some device might have some port not connected.
30 * SSDK still needs the addrs of the first PHY (even if not connected)
31 * to correctly setup the malibu PHY.
32 *
33 * This is needed as previously SSDK based this on the port bmp, but
34 * this can be problematic now that we specify correct bmp.
35 *
36 * Most common configuration have the malibu PHY placed at 0.
37 * But some device might have it placed at address 16.
38 * To drive the correct value, check the port id of the malibu PHY
39 * and try to understand what is the first one in devices where some
40 * port are missing. port_phyinfo is normally the way to go to derive
41 * this value in the few special cases.
42 */
43 malibu_first_phy_addr = <0>;
44 clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
45 <&gcc GCC_CMN_12GPLL_SYS_CLK>,
46 <&gcc GCC_UNIPHY0_AHB_CLK>,
47 <&gcc GCC_UNIPHY0_SYS_CLK>,
48 <&gcc GCC_UNIPHY1_AHB_CLK>,
49 <&gcc GCC_UNIPHY1_SYS_CLK>,
50 <&gcc GCC_UNIPHY2_AHB_CLK>,
51 <&gcc GCC_UNIPHY2_SYS_CLK>,
52 <&gcc GCC_PORT1_MAC_CLK>,
53 <&gcc GCC_PORT2_MAC_CLK>,
54 <&gcc GCC_PORT3_MAC_CLK>,
55 <&gcc GCC_PORT4_MAC_CLK>,
56 <&gcc GCC_PORT5_MAC_CLK>,
57 <&gcc GCC_PORT6_MAC_CLK>,
58 <&gcc GCC_NSS_PPE_CLK>,
59 <&gcc GCC_NSS_PPE_CFG_CLK>,
60 <&gcc GCC_NSSNOC_PPE_CLK>,
61 <&gcc GCC_NSSNOC_PPE_CFG_CLK>,
62 <&gcc GCC_NSS_EDMA_CLK>,
63 <&gcc GCC_NSS_EDMA_CFG_CLK>,
64 <&gcc GCC_NSS_PPE_IPE_CLK>,
65 <&gcc GCC_NSS_PPE_BTQ_CLK>,
66 <&gcc GCC_MDIO_AHB_CLK>,
67 <&gcc GCC_NSS_NOC_CLK>,
68 <&gcc GCC_NSSNOC_SNOC_CLK>,
69 <&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
70 <&gcc GCC_NSS_CRYPTO_CLK>,
71 <&gcc GCC_NSS_IMEM_CLK>,
72 <&gcc GCC_NSS_PTP_REF_CLK>,
73 <&gcc GCC_NSS_PORT1_RX_CLK>,
74 <&gcc GCC_NSS_PORT1_TX_CLK>,
75 <&gcc GCC_NSS_PORT2_RX_CLK>,
76 <&gcc GCC_NSS_PORT2_TX_CLK>,
77 <&gcc GCC_NSS_PORT3_RX_CLK>,
78 <&gcc GCC_NSS_PORT3_TX_CLK>,
79 <&gcc GCC_NSS_PORT4_RX_CLK>,
80 <&gcc GCC_NSS_PORT4_TX_CLK>,
81 <&gcc GCC_NSS_PORT5_RX_CLK>,
82 <&gcc GCC_NSS_PORT5_TX_CLK>,
83 <&gcc GCC_NSS_PORT6_RX_CLK>,
84 <&gcc GCC_NSS_PORT6_TX_CLK>,
85 <&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
86 <&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
87 <&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
88 <&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
89 <&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
90 <&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
91 <&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
92 <&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
93 <&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
94 <&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
95 <&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
96 <&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
97 <&gcc GCC_UNIPHY2_PORT6_RX_CLK>,
98 <&gcc GCC_UNIPHY2_PORT6_TX_CLK>,
99 <&gcc NSS_PORT5_RX_CLK_SRC>,
100 <&gcc NSS_PORT5_TX_CLK_SRC>;
101 clock-names = "cmn_ahb_clk", "cmn_sys_clk",
102 "uniphy0_ahb_clk", "uniphy0_sys_clk",
103 "uniphy1_ahb_clk", "uniphy1_sys_clk",
104 "uniphy2_ahb_clk", "uniphy2_sys_clk",
105 "port1_mac_clk", "port2_mac_clk",
106 "port3_mac_clk", "port4_mac_clk",
107 "port5_mac_clk", "port6_mac_clk",
108 "nss_ppe_clk", "nss_ppe_cfg_clk",
109 "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
110 "nss_edma_clk", "nss_edma_cfg_clk",
111 "nss_ppe_ipe_clk", "nss_ppe_btq_clk",
112 "gcc_mdio_ahb_clk", "gcc_nss_noc_clk",
113 "gcc_nssnoc_snoc_clk",
114 "gcc_mem_noc_nss_axi_clk",
115 "gcc_nss_crypto_clk",
116 "gcc_nss_imem_clk",
117 "gcc_nss_ptp_ref_clk",
118 "nss_port1_rx_clk", "nss_port1_tx_clk",
119 "nss_port2_rx_clk", "nss_port2_tx_clk",
120 "nss_port3_rx_clk", "nss_port3_tx_clk",
121 "nss_port4_rx_clk", "nss_port4_tx_clk",
122 "nss_port5_rx_clk", "nss_port5_tx_clk",
123 "nss_port6_rx_clk", "nss_port6_tx_clk",
124 "uniphy0_port1_rx_clk",
125 "uniphy0_port1_tx_clk",
126 "uniphy0_port2_rx_clk",
127 "uniphy0_port2_tx_clk",
128 "uniphy0_port3_rx_clk",
129 "uniphy0_port3_tx_clk",
130 "uniphy0_port4_rx_clk",
131 "uniphy0_port4_tx_clk",
132 "uniphy0_port5_rx_clk",
133 "uniphy0_port5_tx_clk",
134 "uniphy1_port5_rx_clk",
135 "uniphy1_port5_tx_clk",
136 "uniphy2_port6_rx_clk",
137 "uniphy2_port6_tx_clk",
138 "nss_port5_rx_clk_src",
139 "nss_port5_tx_clk_src";
140 resets = <&gcc GCC_PPE_FULL_RESET>,
141 <&gcc GCC_UNIPHY0_SOFT_RESET>,
142 <&gcc GCC_UNIPHY0_XPCS_RESET>,
143 <&gcc GCC_UNIPHY1_SOFT_RESET>,
144 <&gcc GCC_UNIPHY1_XPCS_RESET>,
145 <&gcc GCC_UNIPHY2_SOFT_RESET>,
146 <&gcc GCC_UNIPHY2_XPCS_RESET>,
147 <&gcc GCC_NSSPORT1_RESET>,
148 <&gcc GCC_NSSPORT2_RESET>,
149 <&gcc GCC_NSSPORT3_RESET>,
150 <&gcc GCC_NSSPORT4_RESET>,
151 <&gcc GCC_NSSPORT5_RESET>,
152 <&gcc GCC_NSSPORT6_RESET>;
153 reset-names = "ppe_rst", "uniphy0_soft_rst",
154 "uniphy0_xpcs_rst", "uniphy1_soft_rst",
155 "uniphy1_xpcs_rst", "uniphy2_soft_rst",
156 "uniphy2_xpcs_rst", "nss_port1_rst",
157 "nss_port2_rst", "nss_port3_rst",
158 "nss_port4_rst", "nss_port5_rst",
159 "nss_port6_rst";
160 mdio-bus = <&mdio>;
161
162 switch_mac_mode = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 0 */
163 switch_mac_mode1 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 1 */
164 switch_mac_mode2 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 2 */
165
166 status = "disabled";
167
168 port_scheduler_resource {
169 port@0 {
170 port_id = <0>;
171 ucast_queue = <0 143>;
172 mcast_queue = <256 271>;
173 l0sp = <0 35>;
174 l0cdrr = <0 47>;
175 l0edrr = <0 47>;
176 l1cdrr = <0 7>;
177 l1edrr = <0 7>;
178 };
179 port@1 {
180 port_id = <1>;
181 ucast_queue = <144 159>;
182 mcast_queue = <272 275>;
183 l0sp = <36 39>;
184 l0cdrr = <48 63>;
185 l0edrr = <48 63>;
186 l1cdrr = <8 11>;
187 l1edrr = <8 11>;
188 };
189 port@2 {
190 port_id = <2>;
191 ucast_queue = <160 175>;
192 mcast_queue = <276 279>;
193 l0sp = <40 43>;
194 l0cdrr = <64 79>;
195 l0edrr = <64 79>;
196 l1cdrr = <12 15>;
197 l1edrr = <12 15>;
198 };
199 port@3 {
200 port_id = <3>;
201 ucast_queue = <176 191>;
202 mcast_queue = <280 283>;
203 l0sp = <44 47>;
204 l0cdrr = <80 95>;
205 l0edrr = <80 95>;
206 l1cdrr = <16 19>;
207 l1edrr = <16 19>;
208 };
209 port@4 {
210 port_id = <4>;
211 ucast_queue = <192 207>;
212 mcast_queue = <284 287>;
213 l0sp = <48 51>;
214 l0cdrr = <96 111>;
215 l0edrr = <96 111>;
216 l1cdrr = <20 23>;
217 l1edrr = <20 23>;
218 };
219 port@5 {
220 port_id = <5>;
221 ucast_queue = <208 223>;
222 mcast_queue = <288 291>;
223 l0sp = <52 55>;
224 l0cdrr = <112 127>;
225 l0edrr = <112 127>;
226 l1cdrr = <24 27>;
227 l1edrr = <24 27>;
228 };
229 port@6 {
230 port_id = <6>;
231 ucast_queue = <224 239>;
232 mcast_queue = <292 295>;
233 l0sp = <56 59>;
234 l0cdrr = <128 143>;
235 l0edrr = <128 143>;
236 l1cdrr = <28 31>;
237 l1edrr = <28 31>;
238 };
239 port@7 {
240 port_id = <7>;
241 ucast_queue = <240 255>;
242 mcast_queue = <296 299>;
243 l0sp = <60 63>;
244 l0cdrr = <144 159>;
245 l0edrr = <144 159>;
246 l1cdrr = <32 35>;
247 l1edrr = <32 35>;
248 };
249 };
250 port_scheduler_config {
251 port@0 {
252 port_id = <0>;
253 l1scheduler {
254 group@0 {
255 sp = <0 1>; /*L0 SPs*/
256 /*cpri cdrr epri edrr*/
257 cfg = <0 0 0 0>;
258 };
259 };
260 l0scheduler {
261 group@0 {
262 /*unicast queues*/
263 ucast_queue = <0 4 8>;
264 /*multicast queues*/
265 mcast_queue = <256 260>;
266 /*sp cpri cdrr epri edrr*/
267 cfg = <0 0 0 0 0>;
268 };
269 group@1 {
270 ucast_queue = <1 5 9>;
271 mcast_queue = <257 261>;
272 cfg = <0 1 1 1 1>;
273 };
274 group@2 {
275 ucast_queue = <2 6 10>;
276 mcast_queue = <258 262>;
277 cfg = <0 2 2 2 2>;
278 };
279 group@3 {
280 ucast_queue = <3 7 11>;
281 mcast_queue = <259 263>;
282 cfg = <0 3 3 3 3>;
283 };
284 };
285 };
286 port@1 {
287 port_id = <1>;
288 l1scheduler {
289 group@0 {
290 sp = <36>;
291 cfg = <0 8 0 8>;
292 };
293 group@1 {
294 sp = <37>;
295 cfg = <1 9 1 9>;
296 };
297 };
298 l0scheduler {
299 group@0 {
300 ucast_queue = <144>;
301 ucast_loop_pri = <16>;
302 mcast_queue = <272>;
303 mcast_loop_pri = <4>;
304 cfg = <36 0 48 0 48>;
305 };
306 };
307 };
308 port@2 {
309 port_id = <2>;
310 l1scheduler {
311 group@0 {
312 sp = <40>;
313 cfg = <0 12 0 12>;
314 };
315 group@1 {
316 sp = <41>;
317 cfg = <1 13 1 13>;
318 };
319 };
320 l0scheduler {
321 group@0 {
322 ucast_queue = <160>;
323 ucast_loop_pri = <16>;
324 mcast_queue = <276>;
325 mcast_loop_pri = <4>;
326 cfg = <40 0 64 0 64>;
327 };
328 };
329 };
330 port@3 {
331 port_id = <3>;
332 l1scheduler {
333 group@0 {
334 sp = <44>;
335 cfg = <0 16 0 16>;
336 };
337 group@1 {
338 sp = <45>;
339 cfg = <1 17 1 17>;
340 };
341 };
342 l0scheduler {
343 group@0 {
344 ucast_queue = <176>;
345 ucast_loop_pri = <16>;
346 mcast_queue = <280>;
347 mcast_loop_pri = <4>;
348 cfg = <44 0 80 0 80>;
349 };
350 };
351 };
352 port@4 {
353 port_id = <4>;
354 l1scheduler {
355 group@0 {
356 sp = <48>;
357 cfg = <0 20 0 20>;
358 };
359 group@1 {
360 sp = <49>;
361 cfg = <1 21 1 21>;
362 };
363 };
364 l0scheduler {
365 group@0 {
366 ucast_queue = <192>;
367 ucast_loop_pri = <16>;
368 mcast_queue = <284>;
369 mcast_loop_pri = <4>;
370 cfg = <48 0 96 0 96>;
371 };
372 };
373 };
374 port@5 {
375 port_id = <5>;
376 l1scheduler {
377 group@0 {
378 sp = <52>;
379 cfg = <0 24 0 24>;
380 };
381 group@1 {
382 sp = <53>;
383 cfg = <1 25 1 25>;
384 };
385 };
386 l0scheduler {
387 group@0 {
388 ucast_queue = <208>;
389 ucast_loop_pri = <16>;
390 mcast_queue = <288>;
391 mcast_loop_pri = <4>;
392 cfg = <52 0 112 0 112>;
393 };
394 };
395 };
396 port@6 {
397 port_id = <6>;
398 l1scheduler {
399 group@0 {
400 sp = <56>;
401 cfg = <0 28 0 28>;
402 };
403 group@1 {
404 sp = <57>;
405 cfg = <1 29 1 29>;
406 };
407 };
408 l0scheduler {
409 group@0 {
410 ucast_queue = <224>;
411 ucast_loop_pri = <16>;
412 mcast_queue = <292>;
413 mcast_loop_pri = <4>;
414 cfg = <56 0 128 0 128>;
415 };
416 };
417 };
418 port@7 {
419 port_id = <7>;
420 l1scheduler {
421 group@0 {
422 sp = <60>;
423 cfg = <0 32 0 32>;
424 };
425 group@1 {
426 sp = <61>;
427 cfg = <1 33 1 33>;
428 };
429 };
430 l0scheduler {
431 group@0 {
432 ucast_queue = <240>;
433 ucast_loop_pri = <16>;
434 mcast_queue = <296>;
435 cfg = <60 0 144 0 144>;
436 };
437 };
438 };
439 };
440 };
441
442 ess-uniphy@7a00000 {
443 compatible = "qcom,ess-uniphy";
444 reg = <0x7a00000 0x30000>;
445 uniphy_access_mode = "local bus";
446 };
447
448 edma: edma@3ab00000 {
449 compatible = "qcom,edma";
450 reg = <0x3ab00000 0x76900>;
451 reg-names = "edma-reg-base";
452 qcom,txdesc-ring-start = <23>;
453 qcom,txdesc-rings = <1>;
454 qcom,txcmpl-ring-start = <7>;
455 qcom,txcmpl-rings = <1>;
456 qcom,rxfill-ring-start = <7>;
457 qcom,rxfill-rings = <1>;
458 qcom,rxdesc-ring-start = <15>;
459 qcom,rxdesc-rings = <1>;
460 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
464 resets = <&gcc GCC_EDMA_HW_RESET>;
465 reset-names = "edma_rst";
466 status = "disabled";
467 };
468
469 dp1: dp1 {
470 device_type = "network";
471 compatible = "qcom,nss-dp";
472 qcom,id = <1>;
473 reg = <0x3a001000 0x200>;
474 qcom,mactype = <0>;
475 local-mac-address = [000000000000];
476 phy-mode = "sgmii";
477 status = "disabled";
478 };
479
480 dp2: dp2 {
481 device_type = "network";
482 compatible = "qcom,nss-dp";
483 qcom,id = <2>;
484 reg = <0x3a001200 0x200>;
485 qcom,mactype = <0>;
486 local-mac-address = [000000000000];
487 phy-mode = "sgmii";
488 status = "disabled";
489 };
490
491 dp3: dp3 {
492 device_type = "network";
493 compatible = "qcom,nss-dp";
494 qcom,id = <3>;
495 reg = <0x3a001400 0x200>;
496 qcom,mactype = <0>;
497 local-mac-address = [000000000000];
498 phy-mode = "sgmii";
499 status = "disabled";
500 };
501
502 dp4: dp4 {
503 device_type = "network";
504 compatible = "qcom,nss-dp";
505 qcom,id = <4>;
506 reg = <0x3a001600 0x200>;
507 qcom,mactype = <0>;
508 local-mac-address = [000000000000];
509 phy-mode = "sgmii";
510 status = "disabled";
511 };
512
513 dp5: dp5 {
514 device_type = "network";
515 compatible = "qcom,nss-dp";
516 qcom,id = <5>;
517 reg = <0x3a001800 0x200>;
518 qcom,mactype = <0>;
519 local-mac-address = [000000000000];
520 phy-mode = "sgmii";
521 status = "disabled";
522 };
523
524 dp6: dp6 {
525 device_type = "network";
526 compatible = "qcom,nss-dp";
527 qcom,id = <6>;
528 reg = <0x3a001a00 0x200>;
529 qcom,mactype = <0>;
530 local-mac-address = [000000000000];
531 phy-mode = "sgmii";
532 status = "disabled";
533 };
534
535 dp5_syn: dp5-syn {
536 device_type = "network";
537 compatible = "qcom,nss-dp";
538 qcom,id = <5>;
539 reg = <0x3a003000 0x3fff>;
540 qcom,mactype = <1>;
541 local-mac-address = [000000000000];
542 phy-mode = "sgmii";
543 status = "disabled";
544 };
545
546 dp6_syn: dp6-syn {
547 device_type = "network";
548 compatible = "qcom,nss-dp";
549 qcom,id = <6>;
550 reg = <0x3a007000 0x3fff>;
551 qcom,mactype = <1>;
552 local-mac-address = [000000000000];
553 phy-mode = "sgmii";
554 status = "disabled";
555 };
556 };
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