target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq8074-ess.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2
   3 #include <dt-bindings/net/qcom-ipq-ess.h>
   4
   5 &clocks {
   6         bias_pll_cc_clk {
   7                 compatible = "fixed-clock";
   8                 clock-frequency = <300000000>;
   9                 #clock-cells = <0>;
  10         };
  11
  12         bias_pll_nss_noc_clk {
  13                 compatible = "fixed-clock";
  14                 clock-frequency = <416500000>;
  15                 #clock-cells = <0>;
  16         };
  17 };
  18
  19 &soc {
  20         switch: ess-switch@3a000000 {
  21                 compatible = "qcom,ess-switch-ipq807x";
  22                 reg = <0x3a000000 0x1000000>;
  23                 switch_access_mode = "local bus";
  24                 switch_cpu_bmp = <ESS_PORT0>;  /* cpu port bitmap */
  25                 switch_inner_bmp = <ESS_PORT7>; /*inner port bitmap*/
  26                 clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
  27                          <&gcc GCC_CMN_12GPLL_SYS_CLK>,
  28                          <&gcc GCC_UNIPHY0_AHB_CLK>,
  29                          <&gcc GCC_UNIPHY0_SYS_CLK>,
  30                          <&gcc GCC_UNIPHY1_AHB_CLK>,
  31                          <&gcc GCC_UNIPHY1_SYS_CLK>,
  32                          <&gcc GCC_UNIPHY2_AHB_CLK>,
  33                          <&gcc GCC_UNIPHY2_SYS_CLK>,
  34                          <&gcc GCC_PORT1_MAC_CLK>,
  35                          <&gcc GCC_PORT2_MAC_CLK>,
  36                          <&gcc GCC_PORT3_MAC_CLK>,
  37                          <&gcc GCC_PORT4_MAC_CLK>,
  38                          <&gcc GCC_PORT5_MAC_CLK>,
  39                          <&gcc GCC_PORT6_MAC_CLK>,
  40                          <&gcc GCC_NSS_PPE_CLK>,
  41                          <&gcc GCC_NSS_PPE_CFG_CLK>,
  42                          <&gcc GCC_NSSNOC_PPE_CLK>,
  43                          <&gcc GCC_NSSNOC_PPE_CFG_CLK>,
  44                          <&gcc GCC_NSS_EDMA_CLK>,
  45                          <&gcc GCC_NSS_EDMA_CFG_CLK>,
  46                          <&gcc GCC_NSS_PPE_IPE_CLK>,
  47                          <&gcc GCC_NSS_PPE_BTQ_CLK>,
  48                          <&gcc GCC_MDIO_AHB_CLK>,
  49                          <&gcc GCC_NSS_NOC_CLK>,
  50                          <&gcc GCC_NSSNOC_SNOC_CLK>,
  51                          <&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
  52                          <&gcc GCC_NSS_CRYPTO_CLK>,
  53                          <&gcc GCC_NSS_IMEM_CLK>,
  54                          <&gcc GCC_NSS_PTP_REF_CLK>,
  55                          <&gcc GCC_NSS_PORT1_RX_CLK>,
  56                          <&gcc GCC_NSS_PORT1_TX_CLK>,
  57                          <&gcc GCC_NSS_PORT2_RX_CLK>,
  58                          <&gcc GCC_NSS_PORT2_TX_CLK>,
  59                          <&gcc GCC_NSS_PORT3_RX_CLK>,
  60                          <&gcc GCC_NSS_PORT3_TX_CLK>,
  61                          <&gcc GCC_NSS_PORT4_RX_CLK>,
  62                          <&gcc GCC_NSS_PORT4_TX_CLK>,
  63                          <&gcc GCC_NSS_PORT5_RX_CLK>,
  64                          <&gcc GCC_NSS_PORT5_TX_CLK>,
  65                          <&gcc GCC_NSS_PORT6_RX_CLK>,
  66                          <&gcc GCC_NSS_PORT6_TX_CLK>,
  67                          <&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
  68                          <&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
  69                          <&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
  70                          <&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
  71                          <&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
  72                          <&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
  73                          <&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
  74                          <&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
  75                          <&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
  76                          <&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
  77                          <&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
  78                          <&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
  79                          <&gcc GCC_UNIPHY2_PORT6_RX_CLK>,
  80                          <&gcc GCC_UNIPHY2_PORT6_TX_CLK>,
  81                          <&gcc NSS_PORT5_RX_CLK_SRC>,
  82                          <&gcc NSS_PORT5_TX_CLK_SRC>;
  83                 clock-names = "cmn_ahb_clk", "cmn_sys_clk",
  84                               "uniphy0_ahb_clk", "uniphy0_sys_clk",
  85                               "uniphy1_ahb_clk", "uniphy1_sys_clk",
  86                               "uniphy2_ahb_clk", "uniphy2_sys_clk",
  87                               "port1_mac_clk", "port2_mac_clk",
  88                               "port3_mac_clk", "port4_mac_clk",
  89                               "port5_mac_clk", "port6_mac_clk",
  90                               "nss_ppe_clk", "nss_ppe_cfg_clk",
  91                               "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
  92                               "nss_edma_clk", "nss_edma_cfg_clk",
  93                               "nss_ppe_ipe_clk", "nss_ppe_btq_clk",
  94                               "gcc_mdio_ahb_clk", "gcc_nss_noc_clk",
  95                               "gcc_nssnoc_snoc_clk",
  96                               "gcc_mem_noc_nss_axi_clk",
  97                               "gcc_nss_crypto_clk",
  98                               "gcc_nss_imem_clk",
  99                               "gcc_nss_ptp_ref_clk",
 100                               "nss_port1_rx_clk", "nss_port1_tx_clk",
 101                               "nss_port2_rx_clk", "nss_port2_tx_clk",
 102                               "nss_port3_rx_clk", "nss_port3_tx_clk",
 103                               "nss_port4_rx_clk", "nss_port4_tx_clk",
 104                               "nss_port5_rx_clk", "nss_port5_tx_clk",
 105                               "nss_port6_rx_clk", "nss_port6_tx_clk",
 106                               "uniphy0_port1_rx_clk",
 107                               "uniphy0_port1_tx_clk",
 108                               "uniphy0_port2_rx_clk",
 109                               "uniphy0_port2_tx_clk",
 110                               "uniphy0_port3_rx_clk",
 111                               "uniphy0_port3_tx_clk",
 112                               "uniphy0_port4_rx_clk",
 113                               "uniphy0_port4_tx_clk",
 114                               "uniphy0_port5_rx_clk",
 115                               "uniphy0_port5_tx_clk",
 116                               "uniphy1_port5_rx_clk",
 117                               "uniphy1_port5_tx_clk",
 118                               "uniphy2_port6_rx_clk",
 119                               "uniphy2_port6_tx_clk",
 120                               "nss_port5_rx_clk_src",
 121                               "nss_port5_tx_clk_src";
 122                 resets = <&gcc GCC_PPE_FULL_RESET>,
 123                          <&gcc GCC_UNIPHY0_SOFT_RESET>,
 124                          <&gcc GCC_UNIPHY0_XPCS_RESET>,
 125                          <&gcc GCC_UNIPHY1_SOFT_RESET>,
 126                          <&gcc GCC_UNIPHY1_XPCS_RESET>,
 127                          <&gcc GCC_UNIPHY2_SOFT_RESET>,
 128                          <&gcc GCC_UNIPHY2_XPCS_RESET>,
 129                          <&gcc GCC_NSSPORT1_RESET>,
 130                          <&gcc GCC_NSSPORT2_RESET>,
 131                          <&gcc GCC_NSSPORT3_RESET>,
 132                          <&gcc GCC_NSSPORT4_RESET>,
 133                          <&gcc GCC_NSSPORT5_RESET>,
 134                          <&gcc GCC_NSSPORT6_RESET>;
 135                 reset-names = "ppe_rst", "uniphy0_soft_rst",
 136                               "uniphy0_xpcs_rst", "uniphy1_soft_rst",
 137                               "uniphy1_xpcs_rst", "uniphy2_soft_rst",
 138                               "uniphy2_xpcs_rst", "nss_port1_rst",
 139                               "nss_port2_rst", "nss_port3_rst",
 140                               "nss_port4_rst", "nss_port5_rst",
 141                               "nss_port6_rst";
 142                 mdio-bus = <&mdio>;
 143                 status = "disabled";
 144
 145                 port_scheduler_resource {
 146                         port@0 {
 147                                 port_id = <0>;
 148                                 ucast_queue = <0 143>;
 149                                 mcast_queue = <256 271>;
 150                                 l0sp = <0 35>;
 151                                 l0cdrr = <0 47>;
 152                                 l0edrr = <0 47>;
 153                                 l1cdrr = <0 7>;
 154                                 l1edrr = <0 7>;
 155                         };
 156                         port@1 {
 157                                 port_id = <1>;
 158                                 ucast_queue = <144 159>;
 159                                 mcast_queue = <272 275>;
 160                                 l0sp = <36 39>;
 161                                 l0cdrr = <48 63>;
 162                                 l0edrr = <48 63>;
 163                                 l1cdrr = <8 11>;
 164                                 l1edrr = <8 11>;
 165                         };
 166                         port@2 {
 167                                 port_id = <2>;
 168                                 ucast_queue = <160 175>;
 169                                 mcast_queue = <276 279>;
 170                                 l0sp = <40 43>;
 171                                 l0cdrr = <64 79>;
 172                                 l0edrr = <64 79>;
 173                                 l1cdrr = <12 15>;
 174                                 l1edrr = <12 15>;
 175                         };
 176                         port@3 {
 177                                 port_id = <3>;
 178                                 ucast_queue = <176 191>;
 179                                 mcast_queue = <280 283>;
 180                                 l0sp = <44 47>;
 181                                 l0cdrr = <80 95>;
 182                                 l0edrr = <80 95>;
 183                                 l1cdrr = <16 19>;
 184                                 l1edrr = <16 19>;
 185                         };
 186                         port@4 {
 187                                 port_id = <4>;
 188                                 ucast_queue = <192 207>;
 189                                 mcast_queue = <284 287>;
 190                                 l0sp = <48 51>;
 191                                 l0cdrr = <96 111>;
 192                                 l0edrr = <96 111>;
 193                                 l1cdrr = <20 23>;
 194                                 l1edrr = <20 23>;
 195                         };
 196                         port@5 {
 197                                 port_id = <5>;
 198                                 ucast_queue = <208 223>;
 199                                 mcast_queue = <288 291>;
 200                                 l0sp = <52 55>;
 201                                 l0cdrr = <112 127>;
 202                                 l0edrr = <112 127>;
 203                                 l1cdrr = <24 27>;
 204                                 l1edrr = <24 27>;
 205                         };
 206                         port@6 {
 207                                 port_id = <6>;
 208                                 ucast_queue = <224 239>;
 209                                 mcast_queue = <292 295>;
 210                                 l0sp = <56 59>;
 211                                 l0cdrr = <128 143>;
 212                                 l0edrr = <128 143>;
 213                                 l1cdrr = <28 31>;
 214                                 l1edrr = <28 31>;
 215                         };
 216                         port@7 {
 217                                 port_id = <7>;
 218                                 ucast_queue = <240 255>;
 219                                 mcast_queue = <296 299>;
 220                                 l0sp = <60 63>;
 221                                 l0cdrr = <144 159>;
 222                                 l0edrr = <144 159>;
 223                                 l1cdrr = <32 35>;
 224                                 l1edrr = <32 35>;
 225                         };
 226                 };
 227                 port_scheduler_config {
 228                         port@0 {
 229                                 port_id = <0>;
 230                                 l1scheduler {
 231                                         group@0 {
 232                                                 sp = <0 1>; /*L0 SPs*/
 233                                                 /*cpri cdrr epri edrr*/
 234                                                 cfg = <0 0 0 0>;
 235                                         };
 236                                 };
 237                                 l0scheduler {
 238                                         group@0 {
 239                                                 /*unicast queues*/
 240                                                 ucast_queue = <0 4 8>;
 241                                                 /*multicast queues*/
 242                                                 mcast_queue = <256 260>;
 243                                                 /*sp cpri cdrr epri edrr*/
 244                                                 cfg = <0 0 0 0 0>;
 245                                         };
 246                                         group@1 {
 247                                                 ucast_queue = <1 5 9>;
 248                                                 mcast_queue = <257 261>;
 249                                                 cfg = <0 1 1 1 1>;
 250                                         };
 251                                         group@2 {
 252                                                 ucast_queue = <2 6 10>;
 253                                                 mcast_queue = <258 262>;
 254                                                 cfg = <0 2 2 2 2>;
 255                                         };
 256                                         group@3 {
 257                                                 ucast_queue = <3 7 11>;
 258                                                 mcast_queue = <259 263>;
 259                                                 cfg = <0 3 3 3 3>;
 260                                         };
 261                                 };
 262                         };
 263                         port@1 {
 264                                 port_id = <1>;
 265                                 l1scheduler {
 266                                         group@0 {
 267                                                 sp = <36>;
 268                                                 cfg = <0 8 0 8>;
 269                                         };
 270                                         group@1 {
 271                                                 sp = <37>;
 272                                                 cfg = <1 9 1 9>;
 273                                         };
 274                                 };
 275                                 l0scheduler {
 276                                         group@0 {
 277                                                 ucast_queue = <144>;
 278                                                 ucast_loop_pri = <16>;
 279                                                 mcast_queue = <272>;
 280                                                 mcast_loop_pri = <4>;
 281                                                 cfg = <36 0 48 0 48>;
 282                                         };
 283                                 };
 284                         };
 285                         port@2 {
 286                                 port_id = <2>;
 287                                 l1scheduler {
 288                                         group@0 {
 289                                                 sp = <40>;
 290                                                 cfg = <0 12 0 12>;
 291                                         };
 292                                         group@1 {
 293                                                 sp = <41>;
 294                                                 cfg = <1 13 1 13>;
 295                                         };
 296                                 };
 297                                 l0scheduler {
 298                                         group@0 {
 299                                                 ucast_queue = <160>;
 300                                                 ucast_loop_pri = <16>;
 301                                                 mcast_queue = <276>;
 302                                                 mcast_loop_pri = <4>;
 303                                                 cfg = <40 0 64 0 64>;
 304                                         };
 305                                 };
 306                         };
 307                         port@3 {
 308                                 port_id = <3>;
 309                                 l1scheduler {
 310                                         group@0 {
 311                                                 sp = <44>;
 312                                                 cfg = <0 16 0 16>;
 313                                         };
 314                                         group@1 {
 315                                                 sp = <45>;
 316                                                 cfg = <1 17 1 17>;
 317                                         };
 318                                 };
 319                                 l0scheduler {
 320                                         group@0 {
 321                                                 ucast_queue = <176>;
 322                                                 ucast_loop_pri = <16>;
 323                                                 mcast_queue = <280>;
 324                                                 mcast_loop_pri = <4>;
 325                                                 cfg = <44 0 80 0 80>;
 326                                         };
 327                                 };
 328                         };
 329                         port@4 {
 330                                 port_id = <4>;
 331                                 l1scheduler {
 332                                         group@0 {
 333                                                 sp = <48>;
 334                                                 cfg = <0 20 0 20>;
 335                                         };
 336                                         group@1 {
 337                                                 sp = <49>;
 338                                                 cfg = <1 21 1 21>;
 339                                         };
 340                                 };
 341                                 l0scheduler {
 342                                         group@0 {
 343                                                 ucast_queue = <192>;
 344                                                 ucast_loop_pri = <16>;
 345                                                 mcast_queue = <284>;
 346                                                 mcast_loop_pri = <4>;
 347                                                 cfg = <48 0 96 0 96>;
 348                                         };
 349                                 };
 350                         };
 351                         port@5 {
 352                                 port_id = <5>;
 353                                 l1scheduler {
 354                                         group@0 {
 355                                                 sp = <52>;
 356                                                 cfg = <0 24 0 24>;
 357                                         };
 358                                         group@1 {
 359                                                 sp = <53>;
 360                                                 cfg = <1 25 1 25>;
 361                                         };
 362                                 };
 363                                 l0scheduler {
 364                                         group@0 {
 365                                                 ucast_queue = <208>;
 366                                                 ucast_loop_pri = <16>;
 367                                                 mcast_queue = <288>;
 368                                                 mcast_loop_pri = <4>;
 369                                                 cfg = <52 0 112 0 112>;
 370                                         };
 371                                 };
 372                         };
 373                         port@6 {
 374                                 port_id = <6>;
 375                                 l1scheduler {
 376                                         group@0 {
 377                                                 sp = <56>;
 378                                                 cfg = <0 28 0 28>;
 379                                         };
 380                                         group@1 {
 381                                                 sp = <57>;
 382                                                 cfg = <1 29 1 29>;
 383                                         };
 384                                 };
 385                                 l0scheduler {
 386                                         group@0 {
 387                                                 ucast_queue = <224>;
 388                                                 ucast_loop_pri = <16>;
 389                                                 mcast_queue = <292>;
 390                                                 mcast_loop_pri = <4>;
 391                                                 cfg = <56 0 128 0 128>;
 392                                         };
 393                                 };
 394                         };
 395                         port@7 {
 396                                 port_id = <7>;
 397                                 l1scheduler {
 398                                         group@0 {
 399                                                 sp = <60>;
 400                                                 cfg = <0 32 0 32>;
 401                                         };
 402                                         group@1 {
 403                                                 sp = <61>;
 404                                                 cfg = <1 33 1 33>;
 405                                         };
 406                                 };
 407                                 l0scheduler {
 408                                         group@0 {
 409                                                 ucast_queue = <240>;
 410                                                 ucast_loop_pri = <16>;
 411                                                 mcast_queue = <296>;
 412                                                 cfg = <60 0 144 0 144>;
 413                                         };
 414                                 };
 415                         };
 416                 };
 417         };
 418
 419         ess-uniphy@7a00000 {
 420                 compatible = "qcom,ess-uniphy";
 421                 reg = <0x7a00000 0x30000>;
 422                 uniphy_access_mode = "local bus";
 423         };
 424
 425         edma: edma@3ab00000 {
 426                 compatible = "qcom,edma";
 427                 reg = <0x3ab00000 0x76900>;
 428                 reg-names = "edma-reg-base";
 429                 qcom,txdesc-ring-start = <23>;
 430                 qcom,txdesc-rings = <1>;
 431                 qcom,txcmpl-ring-start = <7>;
 432                 qcom,txcmpl-rings = <1>;
 433                 qcom,rxfill-ring-start = <7>;
 434                 qcom,rxfill-rings = <1>;
 435                 qcom,rxdesc-ring-start = <15>;
 436                 qcom,rxdesc-rings = <1>;
 437                 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
 438                              <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
 439                              <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
 440                              <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
 441                 resets = <&gcc GCC_EDMA_HW_RESET>;
 442                 reset-names = "edma_rst";
 443                 status = "disabled";
 444         };
 445
 446         dp1: dp1 {
 447                 device_type = "network";
 448                 compatible = "qcom,nss-dp";
 449                 qcom,id = <1>;
 450                 reg = <0x3a001000 0x200>;
 451                 qcom,mactype = <0>;
 452                 local-mac-address = [000000000000];
 453                 phy-mode = "sgmii";
 454                 status = "disabled";
 455         };
 456
 457         dp2: dp2 {
 458                 device_type = "network";
 459                 compatible = "qcom,nss-dp";
 460                 qcom,id = <2>;
 461                 reg = <0x3a001200 0x200>;
 462                 qcom,mactype = <0>;
 463                 local-mac-address = [000000000000];
 464                 phy-mode = "sgmii";
 465                 status = "disabled";
 466         };
 467
 468         dp3: dp3 {
 469                 device_type = "network";
 470                 compatible = "qcom,nss-dp";
 471                 qcom,id = <3>;
 472                 reg = <0x3a001400 0x200>;
 473                 qcom,mactype = <0>;
 474                 local-mac-address = [000000000000];
 475                 phy-mode = "sgmii";
 476                 status = "disabled";
 477         };
 478
 479         dp4: dp4 {
 480                 device_type = "network";
 481                 compatible = "qcom,nss-dp";
 482                 qcom,id = <4>;
 483                 reg = <0x3a001600 0x200>;
 484                 qcom,mactype = <0>;
 485                 local-mac-address = [000000000000];
 486                 phy-mode = "sgmii";
 487                 status = "disabled";
 488         };
 489
 490         dp5: dp5 {
 491                 device_type = "network";
 492                 compatible = "qcom,nss-dp";
 493                 qcom,id = <5>;
 494                 reg = <0x3a001800 0x200>;
 495                 qcom,mactype = <0>;
 496                 local-mac-address = [000000000000];
 497                 phy-mode = "sgmii";
 498                 status = "disabled";
 499         };
 500
 501         dp6: dp6 {
 502                 device_type = "network";
 503                 compatible = "qcom,nss-dp";
 504                 qcom,id = <6>;
 505                 reg = <0x3a001a00 0x200>;
 506                 qcom,mactype = <0>;
 507                 local-mac-address = [000000000000];
 508                 phy-mode = "sgmii";
 509                 status = "disabled";
 510         };
 511
 512         dp5_syn: dp5-syn {
 513                 device_type = "network";
 514                 compatible = "qcom,nss-dp";
 515                 qcom,id = <5>;
 516                 reg = <0x3a003000 0x3fff>;
 517                 qcom,mactype = <1>;
 518                 local-mac-address = [000000000000];
 519                 phy-mode = "sgmii";
 520                 status = "disabled";
 521         };
 522
 523         dp6_syn: dp6-syn {
 524                 device_type = "network";
 525                 compatible = "qcom,nss-dp";
 526                 qcom,id = <6>;
 527                 reg = <0x3a007000 0x3fff>;
 528                 qcom,mactype = <1>;
 529                 local-mac-address = [000000000000];
 530                 phy-mode = "sgmii";
 531                 status = "disabled";
 532         };
 533 };