f8eb9c9fe822dbc78720519a581f210be96c0c6c
[openwrt/staging/hauke.git] / target / linux / qualcommax / files / arch / arm64 / boot / dts / qcom / ipq8072-ax880.dts
1 // SPDX-License-Identifier: MIT, GPL-2.0 or later
2 /* Copyright (c) 2023, Ruslan Isaev <legale.legale@gmail.com> */
3
4 /dts-v1/;
5
6 #include "ipq8074.dtsi"
7 #include "ipq8074-hk-cpu.dtsi"
8 #include "ipq8074-ess.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11
12 / {
13 model = "Yuncore AX880";
14 compatible = "yuncore,ax880", "qcom,ipq8074", "qcom,ipq8074-hk09";
15
16 aliases {
17 serial0 = &blsp1_uart5;
18 serial1 = &blsp1_uart3;
19 led-boot = &led_system;
20 led-failsafe = &led_system;
21 led-running = &led_system;
22 led-upgrade = &led_system;
23 /* Aliases as required by u-boot to patch MAC addresses */
24 ethernet0 = &dp5_syn;
25 ethernet1 = &dp6_syn;
26 label-mac-device = &dp5_syn;
27 };
28
29 chosen {
30 stdout-path = "serial0:115200n8";
31 bootargs-append = " root=/dev/ubiblock0_1";
32 };
33
34 keys {
35 compatible = "gpio-keys";
36 pinctrl-0 = <&button_pins>;
37 pinctrl-names = "default";
38
39 reset {
40 label = "reset";
41 gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
42 linux,code = <KEY_RESTART>;
43 };
44 };
45
46 leds {
47 compatible = "gpio-leds";
48
49 led_system: system {
50 label = "system";
51 color = "red";
52 gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
53 };
54
55 wlan2g {
56 label = "wlan2g";
57 color = "green";
58 linux,default-trigger = "phy0tpt";
59 gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
60 };
61
62 wlan5g {
63 label = "wlan5g";
64 color = "blue";
65 linux,default-trigger = "phy1tpt";
66 gpios = <&tlmm 9 GPIO_ACTIVE_HIGH>;
67 };
68 };
69 };
70
71 &tlmm {
72 mdio_pins: mdio-pins {
73 mdc {
74 pins = "gpio68";
75 function = "mdc";
76 drive-strength = <8>;
77 bias-pull-up;
78 };
79
80 mdio {
81 pins = "gpio69";
82 function = "mdio";
83 drive-strength = <8>;
84 bias-pull-up;
85 };
86 };
87
88 button_pins: button_pins {
89 reset_button {
90 pins = "gpio57";
91 function = "gpio";
92 drive-strength = <8>;
93 bias-pull-up;
94 };
95 };
96 };
97
98 &blsp1_spi1 {
99 status = "okay";
100
101 flash@0 {
102 #address-cells = <1>;
103 #size-cells = <1>;
104 reg = <0>;
105 compatible = "jedec,spi-nor";
106 spi-max-frequency = <50000000>;
107
108 partitions {
109 compatible = "fixed-partitions";
110 #address-cells = <1>;
111 #size-cells = <1>;
112
113 partition@0 {
114 label = "0:sbl1";
115 reg = <0x0 0x50000>;
116 read-only;
117 };
118
119 partition@50000 {
120 label = "0:mibib";
121 reg = <0x50000 0x10000>;
122 read-only;
123 };
124
125 partition@60000 {
126 label = "0:bootconfig";
127 reg = <0x60000 0x20000>;
128 read-only;
129 };
130
131 partition@80000 {
132 label = "0:bootconfig1";
133 reg = <0x80000 0x20000>;
134 read-only;
135 };
136
137 partition@a0000 {
138 label = "0:qsee_1";
139 reg = <0xa0000 0x180000>;
140 read-only;
141 };
142
143 partition@220000 {
144 label = "0:qsee";
145 reg = <0x220000 0x180000>;
146 read-only;
147 };
148
149 partition@3a0000 {
150 label = "0:devcfg";
151 reg = <0x3a0000 0x10000>;
152 read-only;
153 };
154
155 partition@3b0000 {
156 label = "0:devcfg_1";
157 reg = <0x3b0000 0x10000>;
158 read-only;
159 };
160
161 partition@3c0000 {
162 label = "0:apdp";
163 reg = <0x3c0000 0x10000>;
164 read-only;
165 };
166
167 partition@3d0000 {
168 label = "0:apdp_1";
169 reg = <0x3d0000 0x10000>;
170 read-only;
171 };
172
173 partition@3e0000 {
174 label = "0:rpm_1";
175 reg = <0x3e0000 0x40000>;
176 read-only;
177 };
178
179 partition@420000 {
180 label = "0:rpm";
181 reg = <0x420000 0x40000>;
182 read-only;
183 };
184
185 partition@460000 {
186 label = "0:cdt_1";
187 reg = <0x460000 0x10000>;
188 read-only;
189 };
190
191 partition@470000 {
192 label = "0:cdt";
193 reg = <0x470000 0x10000>;
194 read-only;
195 };
196
197 partition@480000 {
198 label = "0:appsblenv";
199 reg = <0x480000 0x10000>;
200 };
201
202 partition@490000 {
203 label = "0:appsbl_1";
204 reg = <0x490000 0xa0000>;
205 read-only;
206 };
207
208 partition@550000 {
209 label = "0:appsbl";
210 reg = <0x530000 0xa0000>;
211 read-only;
212 };
213
214 partition@610000 {
215 label = "0:art";
216 reg = <0x5d0000 0x40000>;
217 read-only;
218 };
219
220 partition@650000 {
221 label = "0:ethphyfw";
222 reg = <0x610000 0x80000>;
223 read-only;
224 };
225
226 };
227 };
228 };
229
230 //serial interface
231 &blsp1_uart3 {
232 status = "okay";
233 };
234
235 &blsp1_uart5 {
236 status = "okay";
237 };
238
239 &crypto {
240 status = "okay";
241 };
242
243 &cryptobam {
244 status = "okay";
245 };
246
247 &prng {
248 status = "okay";
249 };
250
251 &qpic_bam {
252 status = "okay";
253 };
254
255 &qusb_phy_0 {
256 status = "okay";
257 };
258
259 &ssphy_0 {
260 status = "okay";
261 };
262
263 &usb_0 {
264 status = "okay";
265 };
266
267 &qpic_nand {
268 status = "okay";
269
270 nand@0 {
271 reg = <0>;
272 nand-ecc-strength = <4>;
273 nand-ecc-step-size = <512>;
274 nand-bus-width = <8>;
275
276 partitions {
277 compatible = "fixed-partitions";
278 #address-cells = <1>;
279 #size-cells = <1>;
280
281 partition@0 {
282 label = "rootfs_1";
283 reg = <0x0000000 0x3400000>;
284 };
285
286 partition@3400000 {
287 label = "0:wififw";
288 reg = <0x3400000 0x800000>;
289 read-only;
290 };
291
292 rootfs: partition@3c00000 {
293 label = "rootfs";
294 reg = <0x3c00000 0x3400000>;
295 };
296
297 partition@7000000 {
298 label = "0:wififw_1";
299 reg = <0x7000000 0x800000>;
300 read-only;
301 };
302 };
303 };
304 };
305
306 &mdio {
307 status = "okay";
308
309 pinctrl-0 = <&mdio_pins>;
310 pinctrl-names = "default";
311
312 qca8081_24: ethernet-phy@24 {
313 compatible = "ethernet-phy-id004d.d101";
314 reg = <24>;
315 reset-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
316 };
317
318 qca8081_28: ethernet-phy@28 {
319 compatible = "ethernet-phy-id004d.d101";
320 reg = <28>;
321 reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
322 };
323 };
324
325 &switch {
326 status = "okay";
327
328 switch_lan_bmp = <ESS_PORT5>; /* lan port bitmap */
329 switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
330 switch_mac_mode1 = <MAC_MODE_SGMII_CHANNEL0>; /* mac mode for uniphy instance1*/
331 switch_mac_mode2 = <MAC_MODE_SGMII_CHANNEL0>; /* mac mode for uniphy instance2*/
332 bm_tick_mode = <0>; /* bm tick mode */
333 tm_tick_mode = <0>; /* tm tick mode */
334
335 qcom,port_phyinfo {
336 port@4 {
337 port_id = <5>;
338 phy_address = <24>;
339 port_mac_sel = "QGMAC_PORT";
340 };
341 port@5 {
342 port_id = <6>;
343 phy_address = <28>;
344 port_mac_sel = "QGMAC_PORT";
345 };
346 };
347 };
348
349 &edma {
350 status = "okay";
351 };
352
353 &dp5_syn {
354 status = "okay";
355 phy-handle = <&qca8081_24>;
356 label = "wan";
357 };
358
359 &dp6_syn {
360 status = "okay";
361 phy-handle = <&qca8081_28>;
362 label = "lan";
363 };
364
365 &wifi {
366 status = "okay";
367 qcom,ath11k-calibration-variant = "Yuncore-AX880";
368 };