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68539ea788dfcce5e52cb996693de7766607e05e
[openwrt/staging/hauke.git] / target / linux / mediatek / files-6.1 / arch / arm64 / boot / dts / mediatek / mt7986a.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mt7986-clk.h>
10 #include <dt-bindings/reset/mt7986-resets.h>
11 #include <dt-bindings/phy/phy.h>
12
13 / {
14 compatible = "mediatek,mt7986a";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 clk40m: oscillator-40m {
20 compatible = "fixed-clock";
21 clock-frequency = <40000000>;
22 #clock-cells = <0>;
23 clock-output-names = "clkxtal";
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29 cpu0: cpu@0 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a53";
32 enable-method = "psci";
33 reg = <0x0>;
34 #cooling-cells = <2>;
35 };
36
37 cpu1: cpu@1 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 reg = <0x1>;
42 #cooling-cells = <2>;
43 };
44
45 cpu2: cpu@2 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a53";
48 enable-method = "psci";
49 reg = <0x2>;
50 #cooling-cells = <2>;
51 };
52
53 cpu3: cpu@3 {
54 device_type = "cpu";
55 enable-method = "psci";
56 compatible = "arm,cortex-a53";
57 reg = <0x3>;
58 #cooling-cells = <2>;
59 };
60 };
61
62 psci {
63 compatible = "arm,psci-0.2";
64 method = "smc";
65 };
66
67 reserved-memory {
68 #address-cells = <2>;
69 #size-cells = <2>;
70 ranges;
71 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
72 secmon_reserved: secmon@43000000 {
73 reg = <0 0x43000000 0 0x30000>;
74 no-map;
75 };
76
77 wmcpu_emi: wmcpu-reserved@4fc00000 {
78 no-map;
79 reg = <0 0x4fc00000 0 0x00100000>;
80 };
81
82 wo_emi0: wo-emi@4fd00000 {
83 reg = <0 0x4fd00000 0 0x40000>;
84 no-map;
85 };
86
87 wo_emi1: wo-emi@4fd40000 {
88 reg = <0 0x4fd40000 0 0x40000>;
89 no-map;
90 };
91
92 wo_ilm0: wo-ilm@151e0000 {
93 reg = <0 0x151e0000 0 0x8000>;
94 no-map;
95 };
96
97 wo_ilm1: wo-ilm@151f0000 {
98 reg = <0 0x151f0000 0 0x8000>;
99 no-map;
100 };
101
102 wo_data: wo-data@4fd80000 {
103 reg = <0 0x4fd80000 0 0x240000>;
104 no-map;
105 };
106
107 wo_dlm0: wo-dlm@151e8000 {
108 reg = <0 0x151e8000 0 0x2000>;
109 no-map;
110 };
111
112 wo_dlm1: wo-dlm@151f8000 {
113 reg = <0 0x151f8000 0 0x2000>;
114 no-map;
115 };
116
117 wo_boot: wo-boot@15194000 {
118 reg = <0 0x15194000 0 0x1000>;
119 no-map;
120 };
121
122 };
123
124 timer {
125 compatible = "arm,armv8-timer";
126 interrupt-parent = <&gic>;
127 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
128 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
129 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
130 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
131 };
132
133 soc {
134 #address-cells = <2>;
135 #size-cells = <2>;
136 compatible = "simple-bus";
137 ranges;
138
139 gic: interrupt-controller@c000000 {
140 compatible = "arm,gic-v3";
141 #interrupt-cells = <3>;
142 interrupt-parent = <&gic>;
143 interrupt-controller;
144 reg = <0 0x0c000000 0 0x10000>, /* GICD */
145 <0 0x0c080000 0 0x80000>, /* GICR */
146 <0 0x0c400000 0 0x2000>, /* GICC */
147 <0 0x0c410000 0 0x1000>, /* GICH */
148 <0 0x0c420000 0 0x2000>; /* GICV */
149 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
150 };
151
152 infracfg: infracfg@10001000 {
153 compatible = "mediatek,mt7986-infracfg", "syscon";
154 reg = <0 0x10001000 0 0x1000>;
155 #clock-cells = <1>;
156 };
157
158 wed_pcie: wed-pcie@10003000 {
159 compatible = "mediatek,mt7986-wed-pcie",
160 "syscon";
161 reg = <0 0x10003000 0 0x10>;
162 };
163
164 topckgen: topckgen@1001b000 {
165 compatible = "mediatek,mt7986-topckgen", "syscon";
166 reg = <0 0x1001B000 0 0x1000>;
167 #clock-cells = <1>;
168 };
169
170 watchdog: watchdog@1001c000 {
171 compatible = "mediatek,mt7986-wdt";
172 reg = <0 0x1001c000 0 0x1000>;
173 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
174 #reset-cells = <1>;
175 status = "disabled";
176 };
177
178 apmixedsys: apmixedsys@1001e000 {
179 compatible = "mediatek,mt7986-apmixedsys";
180 reg = <0 0x1001E000 0 0x1000>;
181 #clock-cells = <1>;
182 };
183
184 pio: pinctrl@1001f000 {
185 compatible = "mediatek,mt7986a-pinctrl";
186 reg = <0 0x1001f000 0 0x1000>,
187 <0 0x11c30000 0 0x1000>,
188 <0 0x11c40000 0 0x1000>,
189 <0 0x11e20000 0 0x1000>,
190 <0 0x11e30000 0 0x1000>,
191 <0 0x11f00000 0 0x1000>,
192 <0 0x11f10000 0 0x1000>,
193 <0 0x1000b000 0 0x1000>;
194 reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
195 "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
196 gpio-controller;
197 #gpio-cells = <2>;
198 gpio-ranges = <&pio 0 0 100>;
199 interrupt-controller;
200 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
201 interrupt-parent = <&gic>;
202 #interrupt-cells = <2>;
203 };
204
205 sgmiisys0: syscon@10060000 {
206 compatible = "mediatek,mt7986-sgmiisys_0",
207 "syscon";
208 reg = <0 0x10060000 0 0x1000>;
209 #clock-cells = <1>;
210 };
211
212 sgmiisys1: syscon@10070000 {
213 compatible = "mediatek,mt7986-sgmiisys_1",
214 "syscon";
215 reg = <0 0x10070000 0 0x1000>;
216 #clock-cells = <1>;
217 };
218
219 trng: rng@1020f000 {
220 compatible = "mediatek,mt7986-rng",
221 "mediatek,mt7623-rng";
222 reg = <0 0x1020f000 0 0x100>;
223 clocks = <&infracfg CLK_INFRA_TRNG_CK>;
224 clock-names = "rng";
225 status = "disabled";
226 };
227
228 crypto: crypto@10320000 {
229 compatible = "inside-secure,safexcel-eip97";
230 reg = <0 0x10320000 0 0x40000>;
231 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
235 interrupt-names = "ring0", "ring1", "ring2", "ring3";
236 clocks = <&infracfg CLK_INFRA_EIP97_CK>;
237 clock-names = "infra_eip97_ck";
238 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
239 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
240 status = "disabled";
241 };
242
243 pwm: pwm@10048000 {
244 compatible = "mediatek,mt7986-pwm";
245 reg = <0 0x10048000 0 0x1000>;
246 #clock-cells = <1>;
247 #pwm-cells = <2>;
248 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
249 clocks = <&topckgen CLK_TOP_PWM_SEL>,
250 <&infracfg CLK_INFRA_PWM_STA>,
251 <&infracfg CLK_INFRA_PWM1_CK>,
252 <&infracfg CLK_INFRA_PWM2_CK>;
253 clock-names = "top", "main", "pwm1", "pwm2";
254 status = "disabled";
255 };
256
257 uart0: serial@11002000 {
258 compatible = "mediatek,mt7986-uart",
259 "mediatek,mt6577-uart";
260 reg = <0 0x11002000 0 0x400>;
261 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
263 <&infracfg CLK_INFRA_UART0_CK>;
264 clock-names = "baud", "bus";
265 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
266 <&infracfg CLK_INFRA_UART0_SEL>;
267 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
268 <&topckgen CLK_TOP_UART_SEL>;
269 status = "disabled";
270 };
271
272 uart1: serial@11003000 {
273 compatible = "mediatek,mt7986-uart",
274 "mediatek,mt6577-uart";
275 reg = <0 0x11003000 0 0x400>;
276 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
278 <&infracfg CLK_INFRA_UART1_CK>;
279 clock-names = "baud", "bus";
280 assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
281 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
282 status = "disabled";
283 };
284
285 uart2: serial@11004000 {
286 compatible = "mediatek,mt7986-uart",
287 "mediatek,mt6577-uart";
288 reg = <0 0x11004000 0 0x400>;
289 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
291 <&infracfg CLK_INFRA_UART2_CK>;
292 clock-names = "baud", "bus";
293 assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
294 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
295 status = "disabled";
296 };
297
298 i2c0: i2c@11008000 {
299 compatible = "mediatek,mt7986-i2c";
300 reg = <0 0x11008000 0 0x90>,
301 <0 0x10217080 0 0x80>;
302 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
303 clock-div = <5>;
304 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
305 <&infracfg CLK_INFRA_AP_DMA_CK>;
306 clock-names = "main", "dma";
307 #address-cells = <1>;
308 #size-cells = <0>;
309 status = "disabled";
310 };
311
312 spi0: spi@1100a000 {
313 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
314 #address-cells = <1>;
315 #size-cells = <0>;
316 reg = <0 0x1100a000 0 0x100>;
317 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&topckgen CLK_TOP_MPLL_D2>,
319 <&topckgen CLK_TOP_SPI_SEL>,
320 <&infracfg CLK_INFRA_SPI0_CK>,
321 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
322 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
323 status = "disabled";
324 };
325
326 spi1: spi@1100b000 {
327 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
328 #address-cells = <1>;
329 #size-cells = <0>;
330 reg = <0 0x1100b000 0 0x100>;
331 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&topckgen CLK_TOP_MPLL_D2>,
333 <&topckgen CLK_TOP_SPIM_MST_SEL>,
334 <&infracfg CLK_INFRA_SPI1_CK>,
335 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
336 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
337 status = "disabled";
338 };
339
340 auxadc: adc@1100d000 {
341 compatible = "mediatek,mt7986-auxadc";
342 reg = <0 0x1100d000 0 0x1000>;
343 clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
344 clock-names = "main";
345 #io-channel-cells = <1>;
346 status = "disabled";
347 };
348
349 ssusb: usb@11200000 {
350 compatible = "mediatek,mt7986-xhci",
351 "mediatek,mtk-xhci";
352 reg = <0 0x11200000 0 0x2e00>,
353 <0 0x11203e00 0 0x0100>;
354 reg-names = "mac", "ippc";
355 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
357 <&infracfg CLK_INFRA_IUSB_CK>,
358 <&infracfg CLK_INFRA_IUSB_133_CK>,
359 <&infracfg CLK_INFRA_IUSB_66M_CK>,
360 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
361 clock-names = "sys_ck",
362 "ref_ck",
363 "mcu_ck",
364 "dma_ck",
365 "xhci_ck";
366 phys = <&u2port0 PHY_TYPE_USB2>,
367 <&u3port0 PHY_TYPE_USB3>,
368 <&u2port1 PHY_TYPE_USB2>;
369 status = "disabled";
370 };
371
372 mmc0: mmc@11230000 {
373 compatible = "mediatek,mt7986-mmc";
374 reg = <0 0x11230000 0 0x1000>,
375 <0 0x11c20000 0 0x1000>;
376 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
378 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
379 <&infracfg CLK_INFRA_MSDC_CK>,
380 <&infracfg CLK_INFRA_MSDC_133M_CK>,
381 <&infracfg CLK_INFRA_MSDC_66M_CK>;
382 clock-names = "source", "hclk", "source_cg", "bus_clk",
383 "sys_cg";
384 status = "disabled";
385 };
386
387 thermal: thermal@1100c800 {
388 #thermal-sensor-cells = <1>;
389 compatible = "mediatek,mt7986-thermal";
390 reg = <0 0x1100c800 0 0x800>;
391 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&infracfg CLK_INFRA_THERM_CK>,
393 <&infracfg CLK_INFRA_ADC_26M_CK>,
394 <&infracfg CLK_INFRA_ADC_FRC_CK>;
395 clock-names = "therm", "auxadc", "adc_32k";
396 mediatek,auxadc = <&auxadc>;
397 mediatek,apmixedsys = <&apmixedsys>;
398 nvmem-cells = <&thermal_calibration>;
399 nvmem-cell-names = "calibration-data";
400 };
401
402 pcie: pcie@11280000 {
403 compatible = "mediatek,mt7986-pcie",
404 "mediatek,mt8192-pcie";
405 device_type = "pci";
406 #address-cells = <3>;
407 #size-cells = <2>;
408 reg = <0x00 0x11280000 0x00 0x4000>;
409 reg-names = "pcie-mac";
410 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
411 bus-range = <0x00 0xff>;
412 ranges = <0x82000000 0x00 0x20000000 0x00
413 0x20000000 0x00 0x10000000>;
414 clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
415 <&infracfg CLK_INFRA_IPCIE_CK>,
416 <&infracfg CLK_INFRA_IPCIER_CK>,
417 <&infracfg CLK_INFRA_IPCIEB_CK>;
418 clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
419 status = "disabled";
420
421 phys = <&pcie_port PHY_TYPE_PCIE>;
422 phy-names = "pcie-phy";
423
424 #interrupt-cells = <1>;
425 interrupt-map-mask = <0 0 0 0x7>;
426 interrupt-map = <0 0 0 1 &pcie_intc 0>,
427 <0 0 0 2 &pcie_intc 1>,
428 <0 0 0 3 &pcie_intc 2>,
429 <0 0 0 4 &pcie_intc 3>;
430 pcie_intc: interrupt-controller {
431 #address-cells = <0>;
432 #interrupt-cells = <1>;
433 interrupt-controller;
434 };
435 };
436
437 pcie_phy: t-phy@11c00000 {
438 compatible = "mediatek,mt7986-tphy",
439 "mediatek,generic-tphy-v2";
440 #address-cells = <2>;
441 #size-cells = <2>;
442 ranges;
443 status = "disabled";
444
445 pcie_port: pcie-phy@11c00000 {
446 reg = <0 0x11c00000 0 0x20000>;
447 clocks = <&clk40m>;
448 clock-names = "ref";
449 #phy-cells = <1>;
450 };
451 };
452
453 efuse: efuse@11d00000 {
454 compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
455 reg = <0 0x11d00000 0 0x1000>;
456 #address-cells = <1>;
457 #size-cells = <1>;
458
459 thermal_calibration: calib@274 {
460 reg = <0x274 0xc>;
461 };
462 };
463
464 usb_phy: t-phy@11e10000 {
465 compatible = "mediatek,mt7986-tphy",
466 "mediatek,generic-tphy-v2";
467 #address-cells = <1>;
468 #size-cells = <1>;
469 ranges = <0 0 0x11e10000 0x1700>;
470 status = "disabled";
471
472 u2port0: usb-phy@0 {
473 reg = <0x0 0x700>;
474 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
475 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
476 clock-names = "ref", "da_ref";
477 #phy-cells = <1>;
478 };
479
480 u3port0: usb-phy@700 {
481 reg = <0x700 0x900>;
482 clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
483 clock-names = "ref";
484 #phy-cells = <1>;
485 };
486
487 u2port1: usb-phy@1000 {
488 reg = <0x1000 0x700>;
489 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
490 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
491 clock-names = "ref", "da_ref";
492 #phy-cells = <1>;
493 };
494 };
495
496 ethsys: syscon@15000000 {
497 #address-cells = <1>;
498 #size-cells = <1>;
499 compatible = "mediatek,mt7986-ethsys",
500 "syscon";
501 reg = <0 0x15000000 0 0x1000>;
502 #clock-cells = <1>;
503 #reset-cells = <1>;
504 };
505
506 wed0: wed@15010000 {
507 compatible = "mediatek,mt7986-wed",
508 "syscon";
509 reg = <0 0x15010000 0 0x1000>;
510 interrupt-parent = <&gic>;
511 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
512 memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
513 <&wo_data>, <&wo_boot>;
514 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
515 "wo-data", "wo-boot";
516 mediatek,wo-ccif = <&wo_ccif0>;
517 };
518
519 wed1: wed@15011000 {
520 compatible = "mediatek,mt7986-wed",
521 "syscon";
522 reg = <0 0x15011000 0 0x1000>;
523 interrupt-parent = <&gic>;
524 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
525 memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
526 <&wo_data>, <&wo_boot>;
527 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
528 "wo-data", "wo-boot";
529 mediatek,wo-ccif = <&wo_ccif1>;
530 };
531
532 wo_ccif0: syscon@151a5000 {
533 compatible = "mediatek,mt7986-wo-ccif", "syscon";
534 reg = <0 0x151a5000 0 0x1000>;
535 interrupt-parent = <&gic>;
536 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
537 };
538
539 wo_ccif1: syscon@151ad000 {
540 compatible = "mediatek,mt7986-wo-ccif", "syscon";
541 reg = <0 0x151ad000 0 0x1000>;
542 interrupt-parent = <&gic>;
543 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
544 };
545
546 eth: ethernet@15100000 {
547 compatible = "mediatek,mt7986-eth";
548 reg = <0 0x15100000 0 0x80000>;
549 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&ethsys CLK_ETH_FE_EN>,
554 <&ethsys CLK_ETH_GP2_EN>,
555 <&ethsys CLK_ETH_GP1_EN>,
556 <&ethsys CLK_ETH_WOCPU1_EN>,
557 <&ethsys CLK_ETH_WOCPU0_EN>,
558 <&sgmiisys0 CLK_SGMII0_TX250M_EN>,
559 <&sgmiisys0 CLK_SGMII0_RX250M_EN>,
560 <&sgmiisys0 CLK_SGMII0_CDR_REF>,
561 <&sgmiisys0 CLK_SGMII0_CDR_FB>,
562 <&sgmiisys1 CLK_SGMII1_TX250M_EN>,
563 <&sgmiisys1 CLK_SGMII1_RX250M_EN>,
564 <&sgmiisys1 CLK_SGMII1_CDR_REF>,
565 <&sgmiisys1 CLK_SGMII1_CDR_FB>,
566 <&topckgen CLK_TOP_NETSYS_SEL>,
567 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
568 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
569 "sgmii_tx250m", "sgmii_rx250m",
570 "sgmii_cdr_ref", "sgmii_cdr_fb",
571 "sgmii2_tx250m", "sgmii2_rx250m",
572 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
573 "netsys0", "netsys1";
574 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
575 <&topckgen CLK_TOP_SGM_325M_SEL>;
576 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
577 <&apmixedsys CLK_APMIXED_SGMPLL>;
578 mediatek,ethsys = <&ethsys>;
579 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
580 mediatek,wed-pcie = <&wed_pcie>;
581 mediatek,wed = <&wed0>, <&wed1>;
582 #reset-cells = <1>;
583 #address-cells = <1>;
584 #size-cells = <0>;
585 status = "disabled";
586 };
587
588 wifi: wifi@18000000 {
589 compatible = "mediatek,mt7986-wmac";
590 resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
591 reset-names = "consys";
592 clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
593 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
594 clock-names = "mcu", "ap2conn";
595 reg = <0 0x18000000 0 0x1000000>,
596 <0 0x10003000 0 0x1000>,
597 <0 0x11d10000 0 0x1000>;
598 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
602 memory-region = <&wmcpu_emi>;
603 };
604 };
605
606 thermal-zones {
607 cpu_thermal: cpu-thermal {
608 polling-delay-passive = <1000>;
609 polling-delay = <1000>;
610 thermal-sensors = <&thermal 0>;
611
612 trips {
613 cpu_trip_active_high: active-high {
614 temperature = <115000>;
615 hysteresis = <2000>;
616 type = "active";
617 };
618
619 cpu_trip_active_low: active-low {
620 temperature = <85000>;
621 hysteresis = <2000>;
622 type = "active";
623 };
624
625 cpu_trip_passive: passive {
626 temperature = <40000>;
627 hysteresis = <2000>;
628 type = "passive";
629 };
630 };
631 };
632 };
633 };
Hauke Mehrtens staging tree