target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2020 MediaTek Inc.
   4  * Author: Sam.Shih <sam.shih@mediatek.com>
   5  * Author: Jianhui Zhao <zhaojh329@gmail.com>
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/phy/phy.h>
  11 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
  12 #include <dt-bindings/reset/mt7986-resets.h>
  13 #include <dt-bindings/pinctrl/mt65xx.h>
  14 #include <dt-bindings/input/linux-event-codes.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/mux/mux.h>
  17
  18 / {
  19         compatible = "mediatek,mt7981";
  20         interrupt-parent = <&gic>;
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a53";
  31                         enable-method = "psci";
  32                         reg = <0x0>;
  33                 };
  34
  35                 cpu@1 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a53";
  38                         enable-method = "psci";
  39                         reg = <0x1>;
  40                 };
  41         };
  42
  43         pwm: pwm@10048000 {
  44                 compatible = "mediatek,mt7981-pwm";
  45                 reg = <0 0x10048000 0 0x1000>;
  46                 #pwm-cells = <2>;
  47                 clocks = <&infracfg CLK_INFRA_PWM_STA>,
  48                          <&infracfg CLK_INFRA_PWM_HCK>,
  49                          <&infracfg CLK_INFRA_PWM1_CK>,
  50                          <&infracfg CLK_INFRA_PWM2_CK>,
  51                          <&infracfg CLK_INFRA_PWM3_CK>;
  52                 clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
  53         };
  54
  55         fan: pwm-fan {
  56                 compatible = "pwm-fan";
  57                 /* cooling level (0, 1, 2, 3) : (0% duty, 50% duty, 75% duty, 100% duty) */
  58                 cooling-levels = <0 128 192 255>;
  59                 #cooling-cells = <2>;
  60                 status = "disabled";
  61         };
  62
  63         thermal-zones {
  64                 cpu_thermal: cpu-thermal {
  65                         polling-delay-passive = <1000>;
  66                         polling-delay = <1000>;
  67                         thermal-sensors = <&thermal 0>;
  68                         trips {
  69                                 cpu_trip_crit: crit {
  70                                         temperature = <125000>;
  71                                         hysteresis = <2000>;
  72                                         type = "critical";
  73                                 };
  74
  75                                 cpu_trip_hot: hot {
  76                                         temperature = <120000>;
  77                                         hysteresis = <2000>;
  78                                         type = "hot";
  79                                 };
  80
  81                                 cpu_trip_active_high: active-high {
  82                                         temperature = <115000>;
  83                                         hysteresis = <2000>;
  84                                         type = "active";
  85                                 };
  86
  87                                 cpu_trip_active_med: active-med {
  88                                         temperature = <85000>;
  89                                         hysteresis = <2000>;
  90                                         type = "active";
  91                                 };
  92
  93                                 cpu_trip_active_low: active-low {
  94                                         temperature = <60000>;
  95                                         hysteresis = <2000>;
  96                                         type = "active";
  97                                 };
  98                         };
  99
 100                         cooling-maps {
 101                                 cpu-active-high {
 102                                         /* active: set fan to cooling level 3 */
 103                                         cooling-device = <&fan 3 3>;
 104                                         trip = <&cpu_trip_active_high>;
 105                                 };
 106
 107                                 cpu-active-med {
 108                                         /* active: set fan to cooling level 2 */
 109                                         cooling-device = <&fan 2 2>;
 110                                         trip = <&cpu_trip_active_med>;
 111                                 };
 112
 113                                 cpu-active-low {
 114                                         /* passive: set fan to cooling level 1 */
 115                                         cooling-device = <&fan 1 1>;
 116                                         trip = <&cpu_trip_active_low>;
 117                                 };
 118                         };
 119                 };
 120         };
 121
 122         thermal: thermal@1100c800 {
 123                 #thermal-sensor-cells = <1>;
 124                 compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
 125                 reg = <0 0x1100c800 0 0x800>;
 126                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 127                 clocks = <&infracfg CLK_INFRA_THERM_CK>,
 128                          <&infracfg CLK_INFRA_ADC_26M_CK>;
 129                 clock-names = "therm", "auxadc";
 130                 mediatek,auxadc = <&auxadc>;
 131                 mediatek,apmixedsys = <&apmixedsys>;
 132                 nvmem-cells = <&thermal_calibration>;
 133                 nvmem-cell-names = "calibration-data";
 134         };
 135
 136         auxadc: adc@1100d000 {
 137                 compatible = "mediatek,mt7981-auxadc",
 138                              "mediatek,mt7986-auxadc",
 139                              "mediatek,mt7622-auxadc";
 140                 reg = <0 0x1100d000 0 0x1000>;
 141                 clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
 142                          <&infracfg CLK_INFRA_ADC_FRC_CK>;
 143                 clock-names = "main", "32k";
 144                 #io-channel-cells = <1>;
 145         };
 146
 147         wdma: wdma@15104800 {
 148                 compatible = "mediatek,wed-wdma";
 149                 reg = <0 0x15104800 0 0x400>,
 150                       <0 0x15104c00 0 0x400>;
 151         };
 152
 153         ap2woccif: ap2woccif@151a5000 {
 154                 compatible = "mediatek,ap2woccif";
 155                 reg = <0 0x151a5000 0 0x1000>,
 156                       <0 0x151ad000 0 0x1000>;
 157                 interrupt-parent = <&gic>;
 158                 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 159                              <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
 160         };
 161
 162         reserved-memory {
 163                 #address-cells = <2>;
 164                 #size-cells = <2>;
 165                 ranges;
 166
 167                 /* 64 KiB reserved for ramoops/pstore */
 168                 ramoops@42ff0000 {
 169                         compatible = "ramoops";
 170                         reg = <0 0x42ff0000 0 0x10000>;
 171                         record-size = <0x1000>;
 172                 };
 173
 174                 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
 175                 secmon_reserved: secmon@43000000 {
 176                         reg = <0 0x43000000 0 0x30000>;
 177                         no-map;
 178                 };
 179
 180                 wmcpu_emi: wmcpu-reserved@47c80000 {
 181                         reg = <0 0x47c80000 0 0x100000>;
 182                         no-map;
 183                 };
 184
 185                 wo_emi0: wo-emi@47d80000 {
 186                         reg = <0 0x47d80000 0 0x40000>;
 187                         no-map;
 188                 };
 189
 190                 wo_data: wo-data@47dc0000 {
 191                         reg = <0 0x47dc0000 0 0x240000>;
 192                         no-map;
 193                 };
 194
 195                 wo_ilm0: wo-ilm@151e0000 {
 196                         reg = <0 0x151e0000 0 0x8000>;
 197                         no-map;
 198                 };
 199
 200                 wo_dlm0: wo-dlm@151e8000 {
 201                         reg = <0 0x151e8000 0 0x2000>;
 202                         no-map;
 203                 };
 204
 205                 wo_boot: wo-boot@15194000 {
 206                         reg = <0 0x15194000 0 0x1000>;
 207                         no-map;
 208                 };
 209         };
 210
 211         psci {
 212                 compatible  = "arm,psci-0.2";
 213                 method      = "smc";
 214         };
 215
 216         trng {
 217                 compatible = "mediatek,mt7981-rng";
 218         };
 219
 220         clk40m: oscillator@0 {
 221                 compatible = "fixed-clock";
 222                 #clock-cells = <0>;
 223                 clock-frequency = <40000000>;
 224                 clock-output-names = "clkxtal";
 225         };
 226
 227         infracfg: infracfg@10001000 {
 228                 compatible = "mediatek,mt7981-infracfg", "syscon";
 229                 reg = <0 0x10001000 0 0x1000>;
 230                 #clock-cells = <1>;
 231         };
 232
 233         topckgen: topckgen@1001B000 {
 234                 compatible = "mediatek,mt7981-topckgen", "syscon";
 235                 reg = <0 0x1001B000 0 0x1000>;
 236                 #clock-cells = <1>;
 237         };
 238
 239         apmixedsys: apmixedsys@1001E000 {
 240                 compatible = "mediatek,mt7981-apmixedsys", "mediatek,mt7986-apmixedsys", "syscon";
 241                 reg = <0 0x1001E000 0 0x1000>;
 242                 #clock-cells = <1>;
 243         };
 244
 245         timer {
 246                 compatible = "arm,armv8-timer";
 247                 interrupt-parent = <&gic>;
 248                 clock-frequency = <13000000>;
 249                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 250                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 251                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 252                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 253
 254         };
 255
 256         watchdog: watchdog@1001c000 {
 257                 compatible = "mediatek,mt7986-wdt",
 258                              "mediatek,mt6589-wdt";
 259                 reg = <0 0x1001c000 0 0x1000>;
 260                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 261                 #reset-cells = <1>;
 262                 status = "disabled";
 263         };
 264
 265         gic: interrupt-controller@c000000 {
 266                 compatible = "arm,gic-v3";
 267                 #interrupt-cells = <3>;
 268                 interrupt-parent = <&gic>;
 269                 interrupt-controller;
 270                 reg = <0 0x0c000000 0 0x40000>,  /* GICD */
 271                       <0 0x0c080000 0 0x200000>; /* GICR */
 272
 273                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 274         };
 275
 276         uart0: serial@11002000 {
 277                 compatible = "mediatek,mt6577-uart";
 278                 reg = <0 0x11002000 0 0x400>;
 279                 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 280                 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
 281                         <&infracfg CLK_INFRA_UART0_CK>;
 282                 clock-names = "baud", "bus";
 283                 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 284                                   <&infracfg CLK_INFRA_UART0_SEL>;
 285                 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
 286                                          <&topckgen CLK_TOP_UART_SEL>;
 287                 pinctrl-0 = <&uart0_pins>;
 288                 pinctrl-names = "default";
 289                 status = "disabled";
 290         };
 291
 292         uart1: serial@11003000 {
 293                 compatible = "mediatek,mt6577-uart";
 294                 reg = <0 0x11003000 0 0x400>;
 295                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 296                 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
 297                         <&infracfg CLK_INFRA_UART1_CK>;
 298                 clock-names = "baud", "bus";
 299                 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 300                                   <&infracfg CLK_INFRA_UART1_SEL>;
 301                 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
 302                                          <&topckgen CLK_TOP_UART_SEL>;
 303                 status = "disabled";
 304         };
 305
 306         uart2: serial@11004000 {
 307                 compatible = "mediatek,mt6577-uart";
 308                 reg = <0 0x11004000 0 0x400>;
 309                 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 310                 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
 311                         <&infracfg CLK_INFRA_UART2_CK>;
 312                 clock-names = "baud", "bus";
 313                 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 314                                   <&infracfg CLK_INFRA_UART2_SEL>;
 315                 assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
 316                                          <&topckgen CLK_TOP_UART_SEL>;
 317                 status = "disabled";
 318         };
 319
 320         i2c0: i2c@11007000 {
 321                 compatible = "mediatek,mt7981-i2c";
 322                 reg = <0 0x11007000 0 0x1000>,
 323                       <0 0x10217080 0 0x80>;
 324                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 325                 clock-div = <1>;
 326                 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
 327                          <&infracfg CLK_INFRA_AP_DMA_CK>,
 328                          <&infracfg CLK_INFRA_I2C_MCK_CK>,
 329                          <&infracfg CLK_INFRA_I2C_PCK_CK>;
 330                 clock-names = "main", "dma", "mck", "pck";
 331                 #address-cells = <1>;
 332                 #size-cells = <0>;
 333                 status = "disabled";
 334         };
 335
 336         pcie: pcie@11280000 {
 337                 compatible = "mediatek,mt7981-pcie",
 338                              "mediatek,mt7986-pcie";
 339                 device_type = "pci";
 340                 reg = <0 0x11280000 0 0x4000>;
 341                 reg-names = "pcie-mac";
 342                 #address-cells = <3>;
 343                 #size-cells = <2>;
 344                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 345                 bus-range = <0x00 0xff>;
 346                 ranges = <0x82000000 0 0x20000000
 347                           0x0 0x20000000 0 0x10000000>;
 348                 status = "disabled";
 349
 350                 clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
 351                          <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
 352                          <&infracfg CLK_INFRA_IPCIER_CK>,
 353                          <&infracfg CLK_INFRA_IPCIEB_CK>;
 354
 355                 phys = <&u3port0 PHY_TYPE_PCIE>;
 356                 phy-names = "pcie-phy";
 357
 358                 #interrupt-cells = <1>;
 359                 interrupt-map-mask = <0 0 0 7>;
 360                 interrupt-map = <0 0 0 1 &pcie_intc 0>,
 361                                 <0 0 0 2 &pcie_intc 1>,
 362                                 <0 0 0 3 &pcie_intc 2>,
 363                                 <0 0 0 4 &pcie_intc 3>;
 364                 pcie_intc: interrupt-controller {
 365                         interrupt-controller;
 366                         #address-cells = <0>;
 367                         #interrupt-cells = <1>;
 368                 };
 369         };
 370
 371         crypto: crypto@10320000 {
 372                 compatible = "inside-secure,safexcel-eip97";
 373                 reg = <0 0x10320000 0 0x40000>;
 374                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 375                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 376                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 377                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 378                 interrupt-names = "ring0", "ring1", "ring2", "ring3";
 379                 clocks = <&topckgen CLK_TOP_EIP97B>;
 380                 clock-names = "top_eip97_ck";
 381                 assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
 382                 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
 383         };
 384
 385         pio: pinctrl@11d00000 {
 386                 compatible = "mediatek,mt7981-pinctrl";
 387                 reg = <0 0x11d00000 0 0x1000>,
 388                       <0 0x11c00000 0 0x1000>,
 389                       <0 0x11c10000 0 0x1000>,
 390                       <0 0x11d20000 0 0x1000>,
 391                       <0 0x11e00000 0 0x1000>,
 392                       <0 0x11e20000 0 0x1000>,
 393                       <0 0x11f00000 0 0x1000>,
 394                       <0 0x11f10000 0 0x1000>,
 395                       <0 0x1000b000 0 0x1000>;
 396                 reg-names = "gpio", "iocfg_rt", "iocfg_rm",
 397                             "iocfg_rb", "iocfg_lb", "iocfg_bl",
 398                             "iocfg_tm", "iocfg_tl", "eint";
 399                 gpio-controller;
 400                 #gpio-cells = <2>;
 401                 gpio-ranges = <&pio 0 0 56>;
 402                 interrupt-controller;
 403                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 404                 interrupt-parent = <&gic>;
 405                 #interrupt-cells = <2>;
 406
 407                 mdio_pins: mdc-mdio-pins {
 408                         mux {
 409                                 function = "eth";
 410                                 groups = "smi_mdc_mdio";
 411                         };
 412                 };
 413
 414                 uart0_pins: uart0-pins {
 415                         mux {
 416                                 function = "uart";
 417                                 groups = "uart0";
 418                         };
 419                 };
 420
 421                 wifi_dbdc_pins: wifi-dbdc-pins {
 422                         mux {
 423                                 function = "eth";
 424                                 groups = "wf0_mode1";
 425                         };
 426                         conf {
 427                                 pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
 428                                        "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
 429                                        "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
 430                                        "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
 431                                        "WF_CBA_RESETB", "WF_DIG_RESETB";
 432                                 drive-strength = <4>;
 433                         };
 434                 };
 435         };
 436
 437         ethsys: syscon@15000000 {
 438                 #address-cells = <1>;
 439                 #size-cells = <1>;
 440                 compatible = "mediatek,mt7981-ethsys",
 441                              "mediatek,mt7986-ethsys",
 442                              "syscon";
 443                 reg = <0 0x15000000 0 0x1000>;
 444                 #clock-cells = <1>;
 445                 #reset-cells = <1>;
 446         };
 447
 448         wed: wed@15010000 {
 449                 compatible = "mediatek,mt7981-wed",
 450                              "mediatek,mt7986-wed",
 451                              "syscon";
 452                 reg = <0 0x15010000 0 0x1000>;
 453                 interrupt-parent = <&gic>;
 454                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 455                 memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
 456                                 <&wo_data>, <&wo_boot>;
 457                 memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
 458                                       "wo-data", "wo-boot";
 459                 mediatek,wo-ccif = <&wo_ccif0>;
 460         };
 461
 462         eth: ethernet@15100000 {
 463                 compatible = "mediatek,mt7981-eth";
 464                 reg = <0 0x15100000 0 0x80000>;
 465                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 466                                 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
 467                                 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 468                                 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 469                 clocks = <&ethsys CLK_ETH_FE_EN>,
 470                         <&ethsys CLK_ETH_GP2_EN>,
 471                         <&ethsys CLK_ETH_GP1_EN>,
 472                         <&ethsys CLK_ETH_WOCPU0_EN>,
 473                         <&sgmiisys0 CLK_SGM0_TX_EN>,
 474                         <&sgmiisys0 CLK_SGM0_RX_EN>,
 475                         <&sgmiisys0 CLK_SGM0_CK0_EN>,
 476                         <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
 477                         <&sgmiisys1 CLK_SGM1_TX_EN>,
 478                         <&sgmiisys1 CLK_SGM1_RX_EN>,
 479                         <&sgmiisys1 CLK_SGM1_CK1_EN>,
 480                         <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
 481                         <&topckgen CLK_TOP_SGM_REG>,
 482                         <&topckgen CLK_TOP_NETSYS_SEL>,
 483                         <&topckgen CLK_TOP_NETSYS_500M_SEL>;
 484                 clock-names = "fe", "gp2", "gp1", "wocpu0",
 485                                         "sgmii_tx250m", "sgmii_rx250m",
 486                                         "sgmii_cdr_ref", "sgmii_cdr_fb",
 487                                         "sgmii2_tx250m", "sgmii2_rx250m",
 488                                         "sgmii2_cdr_ref", "sgmii2_cdr_fb",
 489                                         "sgmii_ck", "netsys0", "netsys1";
 490                 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
 491                                   <&topckgen CLK_TOP_SGM_325M_SEL>;
 492                 assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
 493                                          <&topckgen CLK_TOP_CB_SGM_325M>;
 494                 mediatek,ethsys = <&ethsys>;
 495                 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
 496                 mediatek,infracfg = <&topmisc>;
 497                 mediatek,wed = <&wed>;
 498                 #reset-cells = <1>;
 499                 #address-cells = <1>;
 500                 #size-cells = <0>;
 501                 status = "disabled";
 502
 503                 mdio_bus: mdio-bus {
 504                         #address-cells = <1>;
 505                         #size-cells = <0>;
 506
 507                         int_gbe_phy: ethernet-phy@0 {
 508                                 reg = <0>;
 509                                 compatible = "ethernet-phy-ieee802.3-c22";
 510                                 phy-mode = "gmii";
 511                                 phy-is-integrated;
 512                                 nvmem-cells = <&phy_calibration>;
 513                                 nvmem-cell-names = "phy-cal-data";
 514                         };
 515                 };
 516         };
 517
 518         wo_ccif0: syscon@151a5000 {
 519                 compatible = "mediatek,mt7986-wo-ccif", "syscon";
 520                 reg = <0 0x151a5000 0 0x1000>;
 521                 interrupt-parent = <&gic>;
 522                 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
 523         };
 524
 525         sgmiisys0: syscon@10060000 {
 526                 compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon";
 527                 reg = <0 0x10060000 0 0x1000>;
 528                 mediatek,pnswap;
 529                 #clock-cells = <1>;
 530         };
 531
 532         sgmiisys1: syscon@10070000 {
 533                 compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon";
 534                 reg = <0 0x10070000 0 0x1000>;
 535                 #clock-cells = <1>;
 536         };
 537
 538         topmisc: topmisc@11d10000 {
 539                 compatible = "mediatek,mt7981-topmisc", "syscon";
 540                 reg = <0 0x11d10000 0 0x10000>;
 541                 #clock-cells = <1>;
 542         };
 543
 544         snand: snfi@11005000 {
 545                 compatible = "mediatek,mt7986-snand";
 546                 reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
 547                 reg-names = "nfi", "ecc";
 548                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 549                 clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
 550                          <&infracfg CLK_INFRA_NFI1_CK>,
 551                          <&infracfg CLK_INFRA_NFI_HCK_CK>;
 552                 clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
 553                 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
 554                                   <&topckgen CLK_TOP_NFI1X_SEL>;
 555                 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
 556                                          <&topckgen CLK_TOP_CB_M_D8>;
 557                 #address-cells = <1>;
 558                 #size-cells = <0>;
 559                 status = "disabled";
 560         };
 561
 562         mmc0: mmc@11230000 {
 563                 compatible = "mediatek,mt7986-mmc",
 564                                         "mediatek,mt7981-mmc";
 565                 reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
 566                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 567                 clocks = <&infracfg CLK_INFRA_MSDC_CK>,
 568                          <&infracfg CLK_INFRA_MSDC_HCK_CK>,
 569                          <&infracfg CLK_INFRA_MSDC_66M_CK>,
 570                          <&infracfg CLK_INFRA_MSDC_133M_CK>;
 571                 assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
 572                                   <&topckgen CLK_TOP_EMMC_400M_SEL>;
 573                 assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
 574                                          <&topckgen CLK_TOP_CB_NET2_D2>;
 575                 clock-names = "source", "hclk", "axi_cg", "ahb_cg";
 576                 status = "disabled";
 577         };
 578
 579         wed_pcie: wed_pcie@10003000 {
 580                 compatible = "mediatek,wed_pcie";
 581                 reg = <0 0x10003000 0 0x10>;
 582         };
 583
 584         spi0: spi@1100a000 {
 585                 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
 586                 #address-cells = <1>;
 587                 #size-cells = <0>;
 588                 reg = <0 0x1100a000 0 0x100>;
 589                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 590                 clocks = <&topckgen CLK_TOP_CB_M_D2>,
 591                          <&topckgen CLK_TOP_SPI_SEL>,
 592                          <&infracfg CLK_INFRA_SPI0_CK>,
 593                          <&infracfg CLK_INFRA_SPI0_HCK_CK>;
 594
 595                 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 596                 status = "disabled";
 597         };
 598
 599         spi1: spi@1100b000 {
 600                 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
 601                 #address-cells = <1>;
 602                 #size-cells = <0>;
 603                 reg = <0 0x1100b000 0 0x100>;
 604                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 605                 clocks = <&topckgen CLK_TOP_CB_M_D2>,
 606                          <&topckgen CLK_TOP_SPIM_MST_SEL>,
 607                          <&infracfg CLK_INFRA_SPI1_CK>,
 608                          <&infracfg CLK_INFRA_SPI1_HCK_CK>;
 609                 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 610                 status = "disabled";
 611         };
 612
 613         spi2: spi@11009000 {
 614                 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
 615                 #address-cells = <1>;
 616                 #size-cells = <0>;
 617                 reg = <0 0x11009000 0 0x100>;
 618                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 619                 clocks = <&topckgen CLK_TOP_CB_M_D2>,
 620                          <&topckgen CLK_TOP_SPI_SEL>,
 621                          <&infracfg CLK_INFRA_SPI2_CK>,
 622                          <&infracfg CLK_INFRA_SPI2_HCK_CK>;
 623                 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 624                 status = "disabled";
 625         };
 626
 627         consys: consys@10000000 {
 628                 compatible = "mediatek,mt7981-consys";
 629                 reg = <0 0x10000000 0 0x8600000>;
 630                 memory-region = <&wmcpu_emi>;
 631         };
 632
 633         xhci: usb@11200000 {
 634                 compatible = "mediatek,mt7986-xhci",
 635                              "mediatek,mtk-xhci";
 636                 reg = <0 0x11200000 0 0x2e00>,
 637                       <0 0x11203e00 0 0x0100>;
 638                 reg-names = "mac", "ippc";
 639                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 640                 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
 641                          <&infracfg CLK_INFRA_IUSB_CK>,
 642                          <&infracfg CLK_INFRA_IUSB_133_CK>,
 643                          <&infracfg CLK_INFRA_IUSB_66M_CK>,
 644                          <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
 645                 clock-names = "sys_ck",
 646                               "ref_ck",
 647                               "mcu_ck",
 648                               "dma_ck",
 649                               "xhci_ck";
 650                 phys = <&u2port0 PHY_TYPE_USB2>,
 651                        <&u3port0 PHY_TYPE_USB3>;
 652                 vusb33-supply = <&reg_3p3v>;
 653                 status = "disabled";
 654         };
 655
 656         usb_phy: usb-phy@11e10000 {
 657                 compatible = "mediatek,mt7981",
 658                              "mediatek,generic-tphy-v2";
 659                 #address-cells = <1>;
 660                 #size-cells = <1>;
 661                 ranges = <0 0 0x11e10000 0x1700>;
 662                 status = "disabled";
 663
 664                 u2port0: usb-phy@0 {
 665                         reg = <0x0 0x700>;
 666                         clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
 667                         clock-names = "ref";
 668                         #phy-cells = <1>;
 669                 };
 670
 671                 u3port0: usb-phy@700 {
 672                         reg = <0x700 0x900>;
 673                         clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
 674                         clock-names = "ref";
 675                         #phy-cells = <1>;
 676                         mediatek,syscon-type = <&topmisc 0x218 0>;
 677                         status = "okay";
 678                 };
 679         };
 680
 681         reg_3p3v: regulator-3p3v {
 682                 compatible = "regulator-fixed";
 683                 regulator-name = "fixed-3.3V";
 684                 regulator-min-microvolt = <3300000>;
 685                 regulator-max-microvolt = <3300000>;
 686                 regulator-boot-on;
 687                 regulator-always-on;
 688         };
 689
 690         efuse: efuse@11f20000 {
 691                 compatible = "mediatek,mt7981-efuse",
 692                              "mediatek,efuse";
 693                 reg = <0 0x11f20000 0 0x1000>;
 694                 #address-cells = <1>;
 695                 #size-cells = <1>;
 696                 status = "okay";
 697
 698                 thermal_calibration: thermal-calib@274 {
 699                         reg = <0x274 0xc>;
 700                 };
 701
 702                 phy_calibration: phy-calib@8dc {
 703                         reg = <0x8dc 0x10>;
 704                 };
 705
 706                 comb_rx_imp_p0: usb3-rx-imp@8c8 {
 707                         reg = <0x8c8 1>;
 708                         bits = <0 5>;
 709                 };
 710
 711                 comb_tx_imp_p0: usb3-tx-imp@8c8 {
 712                         reg = <0x8c8 2>;
 713                         bits = <5 5>;
 714                 };
 715
 716                 comb_intr_p0: usb3-intr@8c9 {
 717                         reg = <0x8c9 1>;
 718                         bits = <2 6>;
 719                 };
 720         };
 721
 722         afe: audio-controller@11210000 {
 723                 compatible = "mediatek,mt79xx-audio";
 724                 reg = <0 0x11210000 0 0x9000>;
 725                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 726                 clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
 727                          <&infracfg CLK_INFRA_AUD_26M_CK>,
 728                          <&infracfg CLK_INFRA_AUD_L_CK>,
 729                          <&infracfg CLK_INFRA_AUD_AUD_CK>,
 730                          <&infracfg CLK_INFRA_AUD_EG2_CK>,
 731                          <&topckgen CLK_TOP_AUD_SEL>;
 732                 clock-names = "aud_bus_ck",
 733                               "aud_26m_ck",
 734                               "aud_l_ck",
 735                               "aud_aud_ck",
 736                               "aud_eg2_ck",
 737                               "aud_sel";
 738                 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
 739                                   <&topckgen CLK_TOP_A1SYS_SEL>,
 740                                   <&topckgen CLK_TOP_AUD_L_SEL>,
 741                                   <&topckgen CLK_TOP_A_TUNER_SEL>;
 742                 assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
 743                                          <&topckgen CLK_TOP_APLL2_D4>,
 744                                          <&topckgen CLK_TOP_CB_APLL2_196M>,
 745                                          <&topckgen CLK_TOP_APLL2_D4>;
 746                 status = "disabled";
 747         };
 748
 749         ice: ice_debug {
 750                 compatible = "mediatek,mt7981-ice_debug",
 751                            "mediatek,mt2701-ice_debug";
 752                 clocks = <&infracfg CLK_INFRA_DBG_CK>;
 753                 clock-names = "ice_dbg";
 754         };
 755
 756         wifi: wifi@18000000 {
 757                 compatible = "mediatek,mt7981-wmac";
 758                 resets = <&watchdog MT7986_TOPRGU_CONSYS_RST>;
 759                 reset-names = "consys";
 760                 pinctrl-0 = <&wifi_dbdc_pins>;
 761                 pinctrl-names = "dbdc";
 762                 clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
 763                          <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
 764                 clock-names = "mcu", "ap2conn";
 765                 reg = <0 0x18000000 0 0x1000000>,
 766                       <0 0x10003000 0 0x1000>,
 767                       <0 0x11d10000 0 0x1000>;
 768                 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 769                              <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 770                              <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 771                              <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 772                 memory-region = <&wmcpu_emi>;
 773                 status = "disabled";
 774         };
 775 };