target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-stock.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2021 MediaTek Inc.
   4  * Author: Sam.Shih <sam.shih@mediatek.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "mt7986a.dtsi"
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/input/input.h>
  11
  12 / {
  13         model = "Zyxel EX5601-T0";
  14         compatible = "zyxel,ex5601-t0", "mediatek,mt7986a-rfb-snand";
  15
  16         aliases {
  17                 serial0 = &uart0;
  18         };
  19
  20         chosen {
  21                 stdout-path = "serial0:115200n8";
  22         };
  23
  24         memory {
  25                 reg = <0 0x40000000 0 0x40000000>;
  26         };
  27
  28         reg_1p8v: regulator-1p8v {
  29                 compatible = "regulator-fixed";
  30                 regulator-name = "fixed-1.8V";
  31                 regulator-min-microvolt = <1800000>;
  32                 regulator-max-microvolt = <1800000>;
  33                 regulator-boot-on;
  34                 regulator-always-on;
  35         };
  36
  37         reg_3p3v: regulator-3p3v {
  38                 compatible = "regulator-fixed";
  39                 regulator-name = "fixed-3.3V";
  40                 regulator-min-microvolt = <3300000>;
  41                 regulator-max-microvolt = <3300000>;
  42                 regulator-boot-on;
  43                 regulator-always-on;
  44         };
  45
  46         reg_5v: regulator-5v {
  47                 compatible = "regulator-fixed";
  48                 regulator-name = "fixed-5V";
  49                 regulator-min-microvolt = <5000000>;
  50                 regulator-max-microvolt = <5000000>;
  51                 regulator-boot-on;
  52                 regulator-always-on;
  53         };
  54
  55         gpio-keys {
  56                 compatible = "gpio-keys";
  57                 poll-interval = <20>;
  58
  59                 reset-button {
  60                         label = "reset";
  61                         gpios = <&pio 21 GPIO_ACTIVE_LOW>;
  62                         linux,code = <KEY_RESTART>;
  63                 };
  64
  65                 wlan-button {
  66                         label = "wlan";
  67                         gpios = <&pio 11 GPIO_ACTIVE_LOW>;
  68                         linux,code = <KEY_WLAN>;
  69                 };
  70                 wps-button {
  71                         label = "wps";
  72                         gpios = <&pio 56 GPIO_ACTIVE_LOW>;
  73                         linux,code = <KEY_WPS_BUTTON>;
  74                 };
  75         };
  76
  77         zyleds {
  78                 compatible = "gpio-leds";
  79
  80                 led_green_wifi24g {
  81                         label = "zyled-green-wifi24g";
  82                         gpios = <&pio 1 GPIO_ACTIVE_LOW>;
  83                         default-state = "off";
  84                 };
  85
  86                 led_green_wifi5g {
  87                         label = "zyled-green-wifi5g";
  88                         gpios = <&pio 2 GPIO_ACTIVE_LOW>;
  89                         default-state = "off";
  90                 };
  91
  92                 led_green_inet {
  93                         label = "zyled-green-inet";
  94                         gpios = <&pio 14 GPIO_ACTIVE_LOW>;
  95                         default-state = "off";
  96                 };
  97
  98                 led_red_inet {
  99                         label = "zyled-red-inet";
 100                         gpios = <&pio 15 GPIO_ACTIVE_LOW>;
 101                         default-state = "off";
 102                 };
 103
 104                 led_green_pwr {
 105                         label = "zyled-green-pwr";
 106                         gpios = <&pio 13 GPIO_ACTIVE_LOW>;
 107                         linux,default-trigger = "timer"; /* Default blinking */
 108                         led-pattern = <125 125>; /* Fast blink is 4 HZ */
 109                 };
 110
 111                 led_red_pwr {
 112                         label = "zyled-red-pwr";
 113                         gpios = <&pio 12 GPIO_ACTIVE_LOW>;
 114                         default-state = "off";
 115                 };
 116
 117                 led_green_fxs {
 118                         label = "zyled-green-fxs";
 119                         gpios = <&pio 16 GPIO_ACTIVE_HIGH>;
 120                         default-state = "off";
 121                 };
 122
 123                 led_amber_fxs {
 124                         label = "zyled-amber-fxs";
 125                         gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
 126                         default-state = "off";
 127                 };
 128
 129                 led_amber_wps24g {
 130                         label = "zyled-amber-wps24g";
 131                         gpios = <&pio 18 GPIO_ACTIVE_HIGH>;
 132                         default-state = "off";
 133                 };
 134
 135                 led_amber_wps5g {
 136                         label = "zyled-amber-wps5g";
 137                         gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
 138                         default-state = "off";
 139                 };
 140
 141                 led_green_lan {
 142                         label = "zyled-green-lan";
 143                         gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
 144                         default-state = "off";
 145                 };
 146
 147                 led_green_sfp {
 148                         label = "zyled-green-sfp";
 149                         gpios = <&pio 24 GPIO_ACTIVE_HIGH>;
 150                         default-state = "off";
 151                 };
 152
 153         };
 154
 155 };
 156
 157 &eth {
 158         status = "okay";
 159
 160         gmac0: mac@0 {
 161                 compatible = "mediatek,eth-mac";
 162                 reg = <0>;
 163                 phy-mode = "2500base-x";
 164
 165                 nvmem-cells = <&macaddr_factory_002a>;
 166                 nvmem-cell-names = "mac-address";
 167
 168                 fixed-link {
 169                         speed = <2500>;
 170                         full-duplex;
 171                         pause;
 172                 };
 173         };
 174
 175         gmac1: mac@1 {
 176                 compatible = "mediatek,eth-mac";
 177                 reg = <1>;
 178                 phy-mode = "2500base-x";
 179                 phy = <&phy6>;
 180
 181                 nvmem-cells = <&macaddr_factory_0024>;
 182                 nvmem-cell-names = "mac-address";
 183         };
 184
 185         mdio: mdio-bus {
 186                 #address-cells = <1>;
 187                 #size-cells = <0>;
 188                 reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
 189                 reset-delay-us = <1500000>;
 190                 reset-post-delay-us = <1000000>;
 191
 192                 phy5: phy@5 {
 193                         compatible = "ethernet-phy-ieee802.3-c45";
 194                         reg = <5>;
 195                 };
 196
 197                 phy6: phy@6 {
 198                         compatible = "ethernet-phy-ieee802.3-c45";
 199                         reg = <6>;
 200                 };
 201
 202                 switch@0 {
 203                         compatible = "mediatek,mt7531";
 204                         reg = <31>;
 205                         reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
 206
 207                         ports {
 208                                 #address-cells = <1>;
 209                                 #size-cells = <0>;
 210
 211                                 port@1 {
 212                                         reg = <1>;
 213                                         label = "lan1";
 214                                 };
 215
 216                                 port@2 {
 217                                         reg = <2>;
 218                                         label = "lan2";
 219                                 };
 220
 221                                 port@3 {
 222                                         reg = <3>;
 223                                         label = "lan3";
 224                                 };
 225
 226                                 port@5 {
 227                                         reg = <5>;
 228                                         label = "lan4";
 229                                         phy-mode = "2500base-x";
 230                                         phy = <&phy5>;
 231                                 };
 232
 233                                 port@6 {
 234                                         reg = <6>;
 235                                         ethernet = <&gmac0>;
 236                                         phy-mode = "2500base-x";
 237
 238                                         fixed-link {
 239                                                 speed = <2500>;
 240                                                 full-duplex;
 241                                                 pause;
 242                                         };
 243                                 };
 244                         };
 245                 };
 246         };
 247 };
 248
 249 &watchdog {
 250         status = "okay";
 251 };
 252
 253 &wifi {
 254         status = "okay";
 255         pinctrl-names = "default", "dbdc";
 256         pinctrl-0 = <&wf_2g_5g_pins>;
 257         pinctrl-1 = <&wf_dbdc_pins>;
 258         mediatek,mtd-eeprom = <&factory 0x0>;
 259         nvmem-cells = <&macaddr_factory_0004>;
 260         nvmem-cell-names = "mac-address";
 261 };
 262
 263 &crypto {
 264         status = "okay";
 265 };
 266
 267 &mmc0 {
 268         pinctrl-names = "default", "state_uhs";
 269         pinctrl-0 = <&mmc0_pins_default>;
 270         pinctrl-1 = <&mmc0_pins_uhs>;
 271         bus-width = <8>;
 272         max-frequency = <200000000>;
 273         cap-mmc-highspeed;
 274         mmc-hs200-1_8v;
 275         mmc-hs400-1_8v;
 276         hs400-ds-delay = <0x14014>;
 277         vmmc-supply = <&reg_3p3v>;
 278         vqmmc-supply = <&reg_1p8v>;
 279         non-removable;
 280         no-sd;
 281         no-sdio;
 282         status = "disabled";
 283 };
 284
 285 &pcie {
 286         pinctrl-names = "default";
 287         pinctrl-0 = <&pcie_pins>;
 288         status = "okay";
 289 };
 290
 291 &pcie_phy {
 292         status = "okay";
 293 };
 294
 295 &pio {
 296         mmc0_pins_default: mmc0-pins {
 297                 mux {
 298                         function = "emmc";
 299                         groups = "emmc_51";
 300                 };
 301                 conf-cmd-dat {
 302                         pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
 303                                "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
 304                                "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
 305                         input-enable;
 306                         drive-strength = <4>;
 307                         mediatek,pull-up-adv = <1>;     /* pull-up 10K */
 308                 };
 309                 conf-clk {
 310                         pins = "EMMC_CK";
 311                         drive-strength = <6>;
 312                         mediatek,pull-down-adv = <2>;   /* pull-down 50K */
 313                 };
 314                 conf-ds {
 315                         pins = "EMMC_DSL";
 316                         mediatek,pull-down-adv = <2>;   /* pull-down 50K */
 317                 };
 318                 conf-rst {
 319                         pins = "EMMC_RSTB";
 320                         drive-strength = <4>;
 321                         mediatek,pull-up-adv = <1>;     /* pull-up 10K */
 322                 };
 323         };
 324
 325         mmc0_pins_uhs: mmc0-uhs-pins {
 326                 mux {
 327                         function = "emmc";
 328                         groups = "emmc_51";
 329                 };
 330                 conf-cmd-dat {
 331                         pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
 332                                "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
 333                                "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
 334                         input-enable;
 335                         drive-strength = <4>;
 336                         mediatek,pull-up-adv = <1>;     /* pull-up 10K */
 337                 };
 338                 conf-clk {
 339                         pins = "EMMC_CK";
 340                         drive-strength = <6>;
 341                         mediatek,pull-down-adv = <2>;   /* pull-down 50K */
 342                 };
 343                 conf-ds {
 344                         pins = "EMMC_DSL";
 345                         mediatek,pull-down-adv = <2>;   /* pull-down 50K */
 346                 };
 347                 conf-rst {
 348                         pins = "EMMC_RSTB";
 349                         drive-strength = <4>;
 350                         mediatek,pull-up-adv = <1>;     /* pull-up 10K */
 351                 };
 352         };
 353
 354         pcie_pins: pcie-pins {
 355                 mux {
 356                         function = "pcie";
 357                         groups = "pcie_clk", "pcie_wake", "pcie_pereset";
 358                 };
 359         };
 360
 361         spic_pins_g2: spic-pins-29-to-32 {
 362                 mux {
 363                         function = "spi";
 364                         groups = "spi1_2";
 365                 };
 366         };
 367
 368         spi_flash_pins: spi-flash-pins-33-to-38 {
 369                 mux {
 370                         function = "spi";
 371                         groups = "spi0", "spi0_wp_hold";
 372                 };
 373                 conf-pu {
 374                         pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
 375                         drive-strength = <8>;
 376                         mediatek,pull-up-adv = <0>;     /* bias-disable */
 377                 };
 378                 conf-pd {
 379                         pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
 380                         drive-strength = <8>;
 381                         mediatek,pull-down-adv = <0>;   /* bias-disable */
 382                 };
 383         };
 384
 385         uart1_pins: uart1-pins {
 386                 mux {
 387                         function = "uart";
 388                         groups = "uart1";
 389                 };
 390         };
 391
 392         uart2_pins: uart2-pins {
 393                 mux {
 394                         function = "uart";
 395                         groups = "uart2";
 396                 };
 397         };
 398
 399         wf_2g_5g_pins: wf_2g_5g-pins {
 400                 mux {
 401                         function = "wifi";
 402                         groups = "wf_2g", "wf_5g";
 403                 };
 404                 conf {
 405                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 406                                "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 407                                "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 408                                "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 409                                "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 410                                "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 411                                "WF1_TOP_CLK", "WF1_TOP_DATA";
 412                         drive-strength = <4>;
 413                 };
 414         };
 415
 416         wf_dbdc_pins: wf_dbdc-pins {
 417                 mux {
 418                         function = "wifi";
 419                         groups = "wf_dbdc";
 420                 };
 421                 conf {
 422                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 423                                "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 424                                "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 425                                "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 426                                "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 427                                "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 428                                "WF1_TOP_CLK", "WF1_TOP_DATA";
 429                         drive-strength = <4>;
 430                 };
 431         };
 432 };
 433
 434 &spi0 {
 435         pinctrl-names = "default";
 436         pinctrl-0 = <&spi_flash_pins>;
 437         cs-gpios = <0>, <0>;
 438         #address-cells = <1>;
 439         #size-cells = <0>;
 440         status = "okay";
 441
 442         spi_nand: spi_nand@0 {
 443                 #address-cells = <1>;
 444                 #size-cells = <1>;
 445                 compatible = "spi-nand";
 446                 reg = <1>;
 447                 spi-max-frequency = <10000000>;
 448                 spi-tx-bus-width = <4>;
 449                 spi-rx-bus-width = <4>;
 450
 451                 partitions {
 452                         compatible = "fixed-partitions";
 453                         #address-cells = <1>;
 454                         #size-cells = <1>;
 455
 456                         partition@0 {
 457                                 label = "BL2";
 458                                 reg = <0x00000 0x0100000>;
 459                                 read-only;
 460                         };
 461
 462                         partition@100000 {
 463                                 label = "u-boot-env";
 464                                 reg = <0x0100000 0x0080000>;
 465                         };
 466
 467                         factory: partition@180000 {
 468                                 label = "Factory";
 469                                 reg = <0x180000 0x0200000>;
 470                                 read-only;
 471                         };
 472
 473                         partition@380000 {
 474                                 label = "FIP";
 475                                 reg = <0x380000 0x01C0000>;
 476                                 read-only;
 477                         };
 478
 479                         partition@540000 {
 480                                 label = "zloader";
 481                                 reg = <0x540000 0x0040000>;
 482                                 read-only;
 483                         };
 484
 485                         partition@580000 {
 486                                 label = "ubi";
 487                                 reg = <0x580000 0x4000000>;
 488                         };
 489
 490                         partition@4580000 {
 491                                 label = "ubi2";
 492                                 reg = <0x4580000 0x4000000>;
 493                                 read-only;
 494                         };
 495
 496                         partition@8580000 {
 497                                 label = "zyubi";
 498                                 reg = <0x8580000 0x15A80000>;
 499                         };
 500                 };
 501         };
 502 };
 503
 504 &spi1 {
 505         pinctrl-names = "default";
 506         pinctrl-0 = <&spic_pins_g2>;
 507         status = "okay";
 508
 509         proslic_spi: proslic_spi@0 {
 510                 compatible = "silabs,proslic_spi";
 511                 reg = <0>;
 512                 spi-max-frequency = <10000000>;
 513                 spi-cpha = <1>;
 514                 spi-cpol = <1>;
 515                 channel_count = <1>;
 516                 debug_level = <4>;       /* 1 = TRC, 2 = DBG, 4 = ERR */
 517                 reset_gpio = <&pio 7 GPIO_ACTIVE_HIGH>;
 518                 ig,enable-spi = <1>;     /* 1: Enable, 0: Disable */
 519         };
 520 };
 521
 522 &ssusb {
 523         vusb33-supply = <&reg_3p3v>;
 524         vbus-supply = <&reg_5v>;
 525         status = "okay";
 526 };
 527
 528 &trng {
 529         status = "okay";
 530 };
 531
 532 &uart0 {
 533         status = "okay";
 534 };
 535
 536 &uart1 {
 537         pinctrl-names = "default";
 538         pinctrl-0 = <&uart1_pins>;
 539         status = "okay";
 540 };
 541
 542 &uart2 {
 543         pinctrl-names = "default";
 544         pinctrl-0 = <&uart2_pins>;
 545         status = "okay";
 546 };
 547
 548 &usb_phy {
 549         status = "okay";
 550 };
 551
 552 &factory {
 553         compatible = "nvmem-cells";
 554         #address-cells = <1>;
 555         #size-cells = <1>;
 556
 557         macaddr_factory_0004: macaddr@0004 {
 558                 reg = <0x0004 0x6>;
 559         };
 560
 561         macaddr_factory_0024: macaddr@0024 {
 562                 reg = <0x0024 0x6>;
 563         };
 564
 565         macaddr_factory_002a: macaddr@002a {
 566                 reg = <0x002a 0x6>;
 567         };
 568 };