target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /dts-v1/;
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/leds/common.h>
   7
   8 #include "mt7986a.dtsi"
   9
  10 / {
  11         aliases {
  12                 serial0 = &uart0;
  13                 led-boot = &led_status_rgb;
  14                 led-failsafe = &led_status_rgb;
  15                 led-running = &led_status_rgb;
  16                 led-upgrade = &led_status_rgb;
  17         };
  18
  19         chosen {
  20                 stdout-path = "serial0:115200n8";
  21         };
  22
  23         memory {
  24                 reg = <0 0x40000000 0 0x20000000>;
  25         };
  26
  27         keys {
  28                 compatible = "gpio-keys";
  29
  30                 reset {
  31                         label = "reset";
  32                         gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  33                         linux,code = <KEY_RESTART>;
  34                 };
  35
  36                 mesh {
  37                         label = "mesh";
  38                         gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  39                         linux,code = <BTN_9>;
  40                         linux,input-type = <EV_SW>;
  41                 };
  42         };
  43 };
  44
  45 &crypto {
  46         status = "okay";
  47 };
  48
  49 &eth {
  50         status = "okay";
  51
  52         gmac0: mac@0 {
  53                 compatible = "mediatek,eth-mac";
  54                 reg = <0>;
  55                 phy-mode = "2500base-x";
  56
  57                 nvmem-cells = <&macaddr_factory_4 (-1)>;
  58                 nvmem-cell-names = "mac-address";
  59
  60                 fixed-link {
  61                         speed = <2500>;
  62                         full-duplex;
  63                         pause;
  64                 };
  65         };
  66
  67         mdio: mdio-bus {
  68                 #address-cells = <1>;
  69                 #size-cells = <0>;
  70         };
  71 };
  72
  73 &mdio {
  74         switch: switch@1f {
  75                 compatible = "mediatek,mt7531";
  76                 reg = <31>;
  77                 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
  78                 interrupt-controller;
  79                 #interrupt-cells = <1>;
  80                 interrupt-parent = <&pio>;
  81                 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
  82         };
  83 };
  84
  85 &pio {
  86         spi_flash_pins: spi-flash-pins-33-to-38 {
  87                 mux {
  88                         function = "spi";
  89                         groups = "spi0", "spi0_wp_hold";
  90                 };
  91                 conf-pu {
  92                         pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
  93                         drive-strength = <8>;
  94                         mediatek,pull-up-adv = <0>; /* bias-disable */
  95                 };
  96                 conf-pd {
  97                         pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
  98                         drive-strength = <8>;
  99                         mediatek,pull-down-adv = <0>; /* bias-disable */
 100                 };
 101         };
 102
 103         spi_led_pins: spic-pins-29-to-32 {
 104                 mux {
 105                         function = "spi";
 106                         groups = "spi1_2";
 107                 };
 108         };
 109
 110         wf_2g_5g_pins: wf_2g_5g-pins {
 111                 mux {
 112                         function = "wifi";
 113                         groups = "wf_2g", "wf_5g";
 114                 };
 115                 conf {
 116                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 117                                "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 118                                "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 119                                "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 120                                "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 121                                "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 122                                "WF1_TOP_CLK", "WF1_TOP_DATA";
 123                         drive-strength = <4>;
 124                 };
 125         };
 126 };
 127
 128 &spi0 {
 129         pinctrl-names = "default";
 130         pinctrl-0 = <&spi_flash_pins>;
 131         status = "okay";
 132
 133         spi_nand_flash: flash@0 {
 134                 compatible = "spi-nand";
 135                 #address-cells = <1>;
 136                 #size-cells = <1>;
 137                 reg = <0>;
 138
 139                 spi-max-frequency = <20000000>;
 140                 spi-tx-bus-width = <4>;
 141                 spi-rx-bus-width = <4>;
 142
 143                 partitions: partitions {
 144                         compatible = "fixed-partitions";
 145                         #address-cells = <1>;
 146                         #size-cells = <1>;
 147
 148                         partition@0 {
 149                                 label = "BL2";
 150                                 reg = <0x0 0x100000>;
 151                                 read-only;
 152                         };
 153
 154                         partition@100000 {
 155                                 label = "Nvram";
 156                                 reg = <0x100000 0x40000>;
 157                         };
 158
 159                         partition@140000 {
 160                                 label = "Bdata";
 161                                 reg = <0x140000 0x40000>;
 162                         };
 163
 164                         factory: partition@180000 {
 165                                 label = "Factory";
 166                                 reg = <0x180000 0x200000>;
 167                                 read-only;
 168
 169                                 nvmem-layout {
 170                                         compatible = "fixed-layout";
 171                                         #address-cells = <1>;
 172                                         #size-cells = <1>;
 173
 174                                         macaddr_factory_4: macaddr@4 {
 175                                                 compatible = "mac-base";
 176                                                 reg = <0x4 0x6>;
 177                                                 #nvmem-cell-cells = <1>;
 178                                         };
 179                                 };
 180                         };
 181
 182                         partition@380000 {
 183                                 label = "FIP";
 184                                 reg = <0x380000 0x200000>;
 185                                 read-only;
 186                         };
 187                 };
 188         };
 189 };
 190
 191 &spi1 {
 192         pinctrl-names = "default";
 193         pinctrl-0 = <&spi_led_pins>;
 194         status = "okay";
 195
 196         ws2812b@0 {
 197                 #address-cells = <1>;
 198                 #size-cells = <0>;
 199                 compatible = "worldsemi,ws2812b";
 200                 reg = <0>;
 201                 spi-max-frequency = <3000000>;
 202
 203                 led_status_rgb: led@0 {
 204                         reg = <0>;
 205                         label = "rgb:status";
 206                         color-index = <LED_COLOR_ID_RED LED_COLOR_ID_GREEN LED_COLOR_ID_BLUE>;
 207                 };
 208
 209                 led_network_rgb: led@1 {
 210                         reg = <1>;
 211                         label = "rgb:network";
 212                         color-index = <LED_COLOR_ID_RED LED_COLOR_ID_GREEN LED_COLOR_ID_BLUE>;
 213                 };
 214         };
 215 };
 216
 217 &switch {
 218         ports {
 219                 #address-cells = <1>;
 220                 #size-cells = <0>;
 221
 222                 port@1 {
 223                         reg = <1>;
 224                         label = "lan4";
 225                 };
 226
 227                 port@2 {
 228                         reg = <2>;
 229                         label = "lan3";
 230                 };
 231
 232                 port@3 {
 233                         reg = <3>;
 234                         label = "lan2";
 235                 };
 236
 237                 port@4 {
 238                         reg = <4>;
 239                         label = "wan";
 240                 };
 241
 242                 port@6 {
 243                         reg = <6>;
 244                         ethernet = <&gmac0>;
 245                         phy-mode = "2500base-x";
 246
 247                         fixed-link {
 248                                 speed = <2500>;
 249                                 full-duplex;
 250                                 pause;
 251                         };
 252                 };
 253         };
 254 };
 255
 256 &trng {
 257         status = "okay";
 258 };
 259
 260 &uart0 {
 261         status = "okay";
 262 };
 263
 264 &watchdog {
 265         status = "okay";
 266 };
 267
 268 &wifi {
 269         status = "okay";
 270         pinctrl-names = "default";
 271         pinctrl-0 = <&wf_2g_5g_pins>;
 272
 273         mediatek,mtd-eeprom = <&factory 0x0>;
 274 };
 275
 276 &uart0 {
 277         status = "okay";
 278 };