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[openwrt/staging/hauke.git] / target / linux / layerscape / patches-4.9 / 817-usb-support-layerscape.patch
1 From f8daa8e984213554008e73cd155530dceec5a109 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Wed, 27 Sep 2017 10:34:07 +0800
4 Subject: [PATCH] usb: support layerscape
5
6 This is a integrated patch for layerscape usb support.
7
8 Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
9 Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
10 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
11 Signed-off-by: Changming Huang <jerry.huang@nxp.com>
12 Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
13 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
14 Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
15 Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
16 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
17 ---
18 drivers/usb/common/common.c | 50 ++++++
19 drivers/usb/core/hub.c | 8 +
20 drivers/usb/dwc3/core.c | 235 ++++++++++++++++++++++++++-
21 drivers/usb/dwc3/core.h | 46 +++++-
22 drivers/usb/dwc3/host.c | 15 +-
23 drivers/usb/gadget/udc/fsl_udc_core.c | 46 +++---
24 drivers/usb/gadget/udc/fsl_usb2_udc.h | 16 +-
25 drivers/usb/host/Kconfig | 2 +-
26 drivers/usb/host/ehci-fsl.c | 289 +++++++++++++++++++++++++++++++---
27 drivers/usb/host/ehci-fsl.h | 3 +
28 drivers/usb/host/ehci-hub.c | 2 +
29 drivers/usb/host/ehci.h | 5 +
30 drivers/usb/host/fsl-mph-dr-of.c | 12 ++
31 drivers/usb/phy/phy-fsl-usb.c | 59 +++++--
32 drivers/usb/phy/phy-fsl-usb.h | 8 +
33 include/linux/usb.h | 1 +
34 include/linux/usb/of.h | 2 +
35 17 files changed, 726 insertions(+), 73 deletions(-)
36
37 diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c
38 index 5ef8da6e..176dee01 100644
39 --- a/drivers/usb/common/common.c
40 +++ b/drivers/usb/common/common.c
41 @@ -105,6 +105,56 @@ static const char *const usb_dr_modes[] = {
42 [USB_DR_MODE_OTG] = "otg",
43 };
44
45 +/**
46 + * of_usb_get_dr_mode - Get dual role mode for given device_node
47 + * @np: Pointer to the given device_node
48 + *
49 + * The function gets phy interface string from property 'dr_mode',
50 + * and returns the correspondig enum usb_dr_mode
51 + */
52 +enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np)
53 +{
54 + const char *dr_mode;
55 + int err, i;
56 +
57 + err = of_property_read_string(np, "dr_mode", &dr_mode);
58 + if (err < 0)
59 + return USB_DR_MODE_UNKNOWN;
60 +
61 + for (i = 0; i < ARRAY_SIZE(usb_dr_modes); i++)
62 + if (!strcmp(dr_mode, usb_dr_modes[i]))
63 + return i;
64 +
65 + return USB_DR_MODE_UNKNOWN;
66 +}
67 +EXPORT_SYMBOL_GPL(of_usb_get_dr_mode);
68 +
69 +/**
70 + * of_usb_get_maximum_speed - Get maximum requested speed for a given USB
71 + * controller.
72 + * @np: Pointer to the given device_node
73 + *
74 + * The function gets the maximum speed string from property "maximum-speed",
75 + * and returns the corresponding enum usb_device_speed.
76 + */
77 +enum usb_device_speed of_usb_get_maximum_speed(struct device_node *np)
78 +{
79 + const char *maximum_speed;
80 + int err;
81 + int i;
82 +
83 + err = of_property_read_string(np, "maximum-speed", &maximum_speed);
84 + if (err < 0)
85 + return USB_SPEED_UNKNOWN;
86 +
87 + for (i = 0; i < ARRAY_SIZE(speed_names); i++)
88 + if (strcmp(maximum_speed, speed_names[i]) == 0)
89 + return i;
90 +
91 + return USB_SPEED_UNKNOWN;
92 +}
93 +EXPORT_SYMBOL_GPL(of_usb_get_maximum_speed);
94 +
95 static enum usb_dr_mode usb_get_dr_mode_from_string(const char *str)
96 {
97 int ret;
98 diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
99 index 80d4ef31..e23acf03 100644
100 --- a/drivers/usb/core/hub.c
101 +++ b/drivers/usb/core/hub.c
102 @@ -4412,6 +4412,14 @@ hub_port_init(struct usb_hub *hub, struct usb_device *udev, int port1,
103 else
104 speed = usb_speed_string(udev->speed);
105
106 +#if !defined(CONFIG_FSL_USB2_OTG) && !defined(CONFIG_FSL_USB2_OTG_MODULE)
107 +if (udev->speed != USB_SPEED_SUPER)
108 + dev_info(&udev->dev,
109 + "%s %s USB device number %d using %s\n",
110 + (udev->config) ? "reset" : "new", speed,
111 + devnum, udev->bus->controller->driver->name);
112 +#endif
113 +
114 if (udev->speed < USB_SPEED_SUPER)
115 dev_info(&udev->dev,
116 "%s %s USB device number %d using %s\n",
117 diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
118 index fea44690..e34ef90a 100644
119 --- a/drivers/usb/dwc3/core.c
120 +++ b/drivers/usb/dwc3/core.c
121 @@ -58,6 +58,7 @@ static int dwc3_get_dr_mode(struct dwc3 *dwc)
122 enum usb_dr_mode mode;
123 struct device *dev = dwc->dev;
124 unsigned int hw_mode;
125 + struct device_node *node = dev->of_node;
126
127 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
128 dwc->dr_mode = USB_DR_MODE_OTG;
129 @@ -83,6 +84,24 @@ static int dwc3_get_dr_mode(struct dwc3 *dwc)
130 mode = USB_DR_MODE_HOST;
131 break;
132 default:
133 + /* Adjust Frame Length */
134 + if (dwc->configure_gfladj)
135 + dwc3_writel(dwc->regs, DWC3_GFLADJ, GFLADJ_30MHZ_REG_SEL |
136 + GFLADJ_30MHZ(GFLADJ_30MHZ_DEFAULT));
137 +
138 + /* Change burst beat and outstanding pipelined transfers requests */
139 + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0,
140 + (dwc3_readl(dwc->regs, DWC3_GSBUSCFG0) & ~0xff) | 0xf);
141 + dwc3_writel(dwc->regs, DWC3_GSBUSCFG1,
142 + dwc3_readl(dwc->regs, DWC3_GSBUSCFG1) | 0xf00);
143 +
144 + /* Enable Snooping */
145 + if (node && of_dma_is_coherent(node)) {
146 + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0,
147 + dwc3_readl(dwc->regs, DWC3_GSBUSCFG0) | 0x22220000);
148 + dev_dbg(dev, "enabled snooping for usb\n");
149 + }
150 +
151 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
152 mode = USB_DR_MODE_HOST;
153 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
154 @@ -213,8 +232,9 @@ static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
155
156 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
157 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
158 - if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
159 - "request value same as default, ignoring\n")) {
160 + if (dft == dwc->fladj) {
161 + dev_warn(dwc->dev, "request value same as default, ignoring\n");
162 + } else {
163 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
164 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
165 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
166 @@ -579,6 +599,99 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
167 return 0;
168 }
169
170 +/* set global soc bus configuration registers */
171 +static void dwc3_set_soc_bus_cfg(struct dwc3 *dwc)
172 +{
173 + struct device *dev = dwc->dev;
174 + u32 *vals;
175 + u32 cfg;
176 + int ntype;
177 + int ret;
178 + int i;
179 +
180 + cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
181 +
182 + /*
183 + * Handle property "snps,incr-burst-type-adjustment".
184 + * Get the number of value from this property:
185 + * result <= 0, means this property is not supported.
186 + * result = 1, means INCRx burst mode supported.
187 + * result > 1, means undefined length burst mode supported.
188 + */
189 + ntype = device_property_read_u32_array(dev,
190 + "snps,incr-burst-type-adjustment", NULL, 0);
191 + if (ntype > 0) {
192 + vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
193 + if (!vals) {
194 + dev_err(dev, "Error to get memory\n");
195 + return;
196 + }
197 + /* Get INCR burst type, and parse it */
198 + ret = device_property_read_u32_array(dev,
199 + "snps,incr-burst-type-adjustment", vals, ntype);
200 + if (ret) {
201 + dev_err(dev, "Error to get property\n");
202 + return;
203 + }
204 + *(dwc->incrx_type + 1) = vals[0];
205 + if (ntype > 1) {
206 + *dwc->incrx_type = 1;
207 + for (i = 1; i < ntype; i++) {
208 + if (vals[i] > *(dwc->incrx_type + 1))
209 + *(dwc->incrx_type + 1) = vals[i];
210 + }
211 + } else
212 + *dwc->incrx_type = 0;
213 +
214 + /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
215 + cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
216 + if (*dwc->incrx_type)
217 + cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
218 + switch (*(dwc->incrx_type + 1)) {
219 + case 256:
220 + cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
221 + break;
222 + case 128:
223 + cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
224 + break;
225 + case 64:
226 + cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
227 + break;
228 + case 32:
229 + cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
230 + break;
231 + case 16:
232 + cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
233 + break;
234 + case 8:
235 + cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
236 + break;
237 + case 4:
238 + cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
239 + break;
240 + case 1:
241 + break;
242 + default:
243 + dev_err(dev, "Invalid property\n");
244 + break;
245 + }
246 + }
247 +
248 + /* Handle usb snooping */
249 + if (dwc->dma_snooping_quirk) {
250 + cfg &= ~DWC3_GSBUSCFG0_SNP_MASK;
251 + cfg |= (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DATARD_SHIFT) |
252 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DESCRD_SHIFT) |
253 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DATAWR_SHIFT) |
254 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DESCWR_SHIFT);
255 + }
256 +
257 + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
258 +
259 +}
260 +
261 +
262 +
263 static void dwc3_core_exit(struct dwc3 *dwc)
264 {
265 dwc3_event_buffers_cleanup(dwc);
266 @@ -721,6 +834,8 @@ static int dwc3_core_init(struct dwc3 *dwc)
267 if (ret)
268 goto err1;
269
270 + dwc3_set_soc_bus_cfg(dwc);
271 +
272 /* Adjust Frame Length */
273 dwc3_frame_length_adjustment(dwc);
274
275 @@ -919,11 +1034,109 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc)
276 }
277 }
278
279 +static void dwc3_get_properties(struct dwc3 *dwc)
280 +{
281 + struct device *dev = dwc->dev;
282 + struct device_node *node = dev->of_node;
283 + u8 lpm_nyet_threshold;
284 + u8 tx_de_emphasis;
285 + u8 hird_threshold;
286 +
287 + /* default to highest possible threshold */
288 + lpm_nyet_threshold = 0xff;
289 +
290 + /* default to -3.5dB de-emphasis */
291 + tx_de_emphasis = 1;
292 +
293 + /*
294 + * default to assert utmi_sleep_n and use maximum allowed HIRD
295 + * threshold value of 0b1100
296 + */
297 + hird_threshold = 12;
298 +
299 + dwc->maximum_speed = usb_get_maximum_speed(dev);
300 + dwc->dr_mode = usb_get_dr_mode(dev);
301 + dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
302 +
303 + dwc->sysdev_is_parent = device_property_read_bool(dev,
304 + "linux,sysdev_is_parent");
305 + if (dwc->sysdev_is_parent)
306 + dwc->sysdev = dwc->dev->parent;
307 + else
308 + dwc->sysdev = dwc->dev;
309 +
310 + dwc->has_lpm_erratum = device_property_read_bool(dev,
311 + "snps,has-lpm-erratum");
312 + device_property_read_u8(dev, "snps,lpm-nyet-threshold",
313 + &lpm_nyet_threshold);
314 + dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
315 + "snps,is-utmi-l1-suspend");
316 + device_property_read_u8(dev, "snps,hird-threshold",
317 + &hird_threshold);
318 + dwc->usb3_lpm_capable = device_property_read_bool(dev,
319 + "snps,usb3_lpm_capable");
320 +
321 + dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
322 +
323 + dwc->configure_gfladj =
324 + of_property_read_bool(node, "configure-gfladj");
325 + dwc->dr_mode = usb_get_dr_mode(dev);
326 +
327 + dwc->disable_scramble_quirk = device_property_read_bool(dev,
328 + "snps,disable_scramble_quirk");
329 + dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
330 + "snps,u2exit_lfps_quirk");
331 + dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
332 + "snps,u2ss_inp3_quirk");
333 + dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
334 + "snps,req_p1p2p3_quirk");
335 + dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
336 + "snps,del_p1p2p3_quirk");
337 + dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
338 + "snps,del_phy_power_chg_quirk");
339 + dwc->lfps_filter_quirk = device_property_read_bool(dev,
340 + "snps,lfps_filter_quirk");
341 + dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
342 + "snps,rx_detect_poll_quirk");
343 + dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
344 + "snps,dis_u3_susphy_quirk");
345 + dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
346 + "snps,dis_u2_susphy_quirk");
347 + dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
348 + "snps,dis_enblslpm_quirk");
349 + dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
350 + "snps,dis_rxdet_inp3_quirk");
351 + dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
352 + "snps,dis-u2-freeclk-exists-quirk");
353 + dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
354 + "snps,dis-del-phy-power-chg-quirk");
355 + dwc->dma_snooping_quirk = device_property_read_bool(dev,
356 + "snps,dma-snooping");
357 +
358 + dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
359 + "snps,tx_de_emphasis_quirk");
360 + device_property_read_u8(dev, "snps,tx_de_emphasis",
361 + &tx_de_emphasis);
362 + device_property_read_string(dev, "snps,hsphy_interface",
363 + &dwc->hsphy_interface);
364 + device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
365 + &dwc->fladj);
366 +
367 + dwc->lpm_nyet_threshold = lpm_nyet_threshold;
368 + dwc->tx_de_emphasis = tx_de_emphasis;
369 +
370 + dwc->hird_threshold = hird_threshold
371 + | (dwc->is_utmi_l1_suspend << 4);
372 +
373 + dwc->imod_interval = 0;
374 +}
375 +
376 #define DWC3_ALIGN_MASK (16 - 1)
377
378 static int dwc3_probe(struct platform_device *pdev)
379 {
380 struct device *dev = &pdev->dev;
381 + struct device_node *node = dev->of_node;
382 struct resource *res;
383 struct dwc3 *dwc;
384 u8 lpm_nyet_threshold;
385 @@ -955,6 +1168,11 @@ static int dwc3_probe(struct platform_device *pdev)
386 dwc->xhci_resources[0].flags = res->flags;
387 dwc->xhci_resources[0].name = res->name;
388
389 + if (node) {
390 + dwc->configure_gfladj =
391 + of_property_read_bool(node, "configure-gfladj");
392 + }
393 +
394 res->start += DWC3_GLOBALS_REGS_START;
395
396 /*
397 @@ -997,6 +1215,12 @@ static int dwc3_probe(struct platform_device *pdev)
398 dwc->usb3_lpm_capable = device_property_read_bool(dev,
399 "snps,usb3_lpm_capable");
400
401 + dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
402 +
403 + dwc->configure_gfladj =
404 + of_property_read_bool(node, "configure-gfladj");
405 + dwc->dr_mode = of_usb_get_dr_mode(node);
406 +
407 dwc->disable_scramble_quirk = device_property_read_bool(dev,
408 "snps,disable_scramble_quirk");
409 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
410 @@ -1041,6 +1265,8 @@ static int dwc3_probe(struct platform_device *pdev)
411 dwc->hird_threshold = hird_threshold
412 | (dwc->is_utmi_l1_suspend << 4);
413
414 + dwc3_get_properties(dwc);
415 +
416 platform_set_drvdata(pdev, dwc);
417 dwc3_cache_hwparams(dwc);
418
419 @@ -1064,6 +1290,11 @@ static int dwc3_probe(struct platform_device *pdev)
420 if (ret < 0)
421 goto err1;
422
423 + /* Adjust Frame Length */
424 + if (dwc->configure_gfladj)
425 + dwc3_writel(dwc->regs, DWC3_GFLADJ, GFLADJ_30MHZ_REG_SEL |
426 + GFLADJ_30MHZ(GFLADJ_30MHZ_DEFAULT));
427 +
428 pm_runtime_forbid(dev);
429
430 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
431 diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
432 index 884c4371..9151eef4 100644
433 --- a/drivers/usb/dwc3/core.h
434 +++ b/drivers/usb/dwc3/core.h
435 @@ -26,6 +26,7 @@
436 #include <linux/dma-mapping.h>
437 #include <linux/mm.h>
438 #include <linux/debugfs.h>
439 +#include <linux/of_address.h>
440
441 #include <linux/usb/ch9.h>
442 #include <linux/usb/gadget.h>
443 @@ -154,6 +155,32 @@
444
445 /* Bit fields */
446
447 +/* Global SoC Bus Configuration Register 0 */
448 +#define AXI3_CACHE_TYPE_AW 0x8 /* write allocate */
449 +#define AXI3_CACHE_TYPE_AR 0x4 /* read allocate */
450 +#define AXI3_CACHE_TYPE_SNP 0x2 /* cacheable */
451 +#define AXI3_CACHE_TYPE_BUF 0x1 /* bufferable */
452 +#define DWC3_GSBUSCFG0_DATARD_SHIFT 28
453 +#define DWC3_GSBUSCFG0_DESCRD_SHIFT 24
454 +#define DWC3_GSBUSCFG0_DATAWR_SHIFT 20
455 +#define DWC3_GSBUSCFG0_DESCWR_SHIFT 16
456 +#define DWC3_GSBUSCFG0_SNP_MASK 0xffff0000
457 +#define DWC3_GSBUSCFG0_DATABIGEND (1 << 11)
458 +#define DWC3_GSBUSCFG0_DESCBIGEND (1 << 10)
459 +#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
460 +#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
461 +#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
462 +#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
463 +#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
464 +#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
465 +#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
466 +#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
467 +#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
468 +
469 +/* Global SoC Bus Configuration Register 1 */
470 +#define DWC3_GSBUSCFG1_1KPAGEENA (1 << 12) /* 1K page boundary enable */
471 +#define DWC3_GSBUSCFG1_PTRANSLIMIT_MASK 0xf00
472 +
473 /* Global Debug Queue/FIFO Space Available Register */
474 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
475 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
476 @@ -180,7 +207,6 @@
477 #define DWC3_GCTL_CLK_PIPE (1)
478 #define DWC3_GCTL_CLK_PIPEHALF (2)
479 #define DWC3_GCTL_CLK_MASK (3)
480 -
481 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
482 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
483 #define DWC3_GCTL_PRTCAP_HOST 1
484 @@ -289,6 +315,10 @@
485 /* Global Frame Length Adjustment Register */
486 #define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7)
487 #define DWC3_GFLADJ_30MHZ_MASK 0x3f
488 +#define GFLADJ_30MHZ_REG_SEL (1 << 7)
489 +#define GFLADJ_30MHZ(n) ((n) & 0x3f)
490 +#define GFLADJ_30MHZ_DEFAULT 0x20
491 +
492
493 /* Global User Control Register 2 */
494 #define DWC3_GUCTL2_RST_ACTBITLATER (1 << 14)
495 @@ -753,6 +783,7 @@ struct dwc3_scratchpad_array {
496 * @regs: base address for our registers
497 * @regs_size: address space size
498 * @fladj: frame length adjustment
499 + * @incrx_type: INCR burst type adjustment
500 * @irq_gadget: peripheral controller's IRQ number
501 * @nr_scratch: number of scratch buffers
502 * @u1u2: only used on revisions <1.83a for workaround
503 @@ -847,6 +878,7 @@ struct dwc3 {
504 spinlock_t lock;
505
506 struct device *dev;
507 + struct device *sysdev;
508
509 struct platform_device *xhci;
510 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
511 @@ -872,6 +904,12 @@ struct dwc3 {
512 enum usb_phy_interface hsphy_mode;
513
514 u32 fladj;
515 + /*
516 + * For INCR burst type.
517 + * First field: for undefined length INCR burst type enable.
518 + * Second field: for INCRx burst type enable
519 + */
520 + u32 incrx_type[2];
521 u32 irq_gadget;
522 u32 nr_scratch;
523 u32 u1u2;
524 @@ -948,9 +986,12 @@ struct dwc3 {
525 unsigned ep0_bounced:1;
526 unsigned ep0_expect_in:1;
527 unsigned has_hibernation:1;
528 + unsigned sysdev_is_parent:1;
529 unsigned has_lpm_erratum:1;
530 unsigned is_utmi_l1_suspend:1;
531 unsigned is_fpga:1;
532 + unsigned needs_fifo_resize:1;
533 + unsigned configure_gfladj:1;
534 unsigned pending_events:1;
535 unsigned pullups_connected:1;
536 unsigned setup_packet_pending:1;
537 @@ -971,9 +1012,12 @@ struct dwc3 {
538 unsigned dis_rxdet_inp3_quirk:1;
539 unsigned dis_u2_freeclk_exists_quirk:1;
540 unsigned dis_del_phy_power_chg_quirk:1;
541 + unsigned dma_snooping_quirk:1;
542
543 unsigned tx_de_emphasis_quirk:1;
544 unsigned tx_de_emphasis:2;
545 +
546 + u16 imod_interval;
547 };
548
549 /* -------------------------------------------------------------------------- */
550 diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c
551 index 626d87d5..f1b98273 100644
552 --- a/drivers/usb/dwc3/host.c
553 +++ b/drivers/usb/dwc3/host.c
554 @@ -17,6 +17,8 @@
555
556 #include <linux/platform_device.h>
557
558 +#include <linux/of_device.h>
559 +
560 #include "core.h"
561
562 int dwc3_host_init(struct dwc3 *dwc)
563 @@ -73,12 +75,21 @@ int dwc3_host_init(struct dwc3 *dwc)
564 return -ENOMEM;
565 }
566
567 - dma_set_coherent_mask(&xhci->dev, dwc->dev->coherent_dma_mask);
568 + if (IS_ENABLED(CONFIG_OF) && dwc->dev->of_node)
569 + of_dma_configure(&xhci->dev, dwc->dev->of_node);
570 + else
571 + dma_set_coherent_mask(&xhci->dev, dwc->dev->coherent_dma_mask);
572
573 - xhci->dev.parent = dwc->dev;
574 + xhci->dev.parent = dwc->dev;
575 xhci->dev.dma_mask = dwc->dev->dma_mask;
576 xhci->dev.dma_parms = dwc->dev->dma_parms;
577
578 + /* set DMA operations */
579 + if (dwc->dev->of_node && of_dma_is_coherent(dwc->dev->of_node)) {
580 + xhci->dev.archdata.dma_ops = dwc->dev->archdata.dma_ops;
581 + dev_dbg(dwc->dev, "set dma_ops for usb\n");
582 + }
583 +
584 dwc->xhci = xhci;
585
586 ret = platform_device_add_resources(xhci, dwc->xhci_resources,
587 diff --git a/drivers/usb/gadget/udc/fsl_udc_core.c b/drivers/usb/gadget/udc/fsl_udc_core.c
588 index aac0ce8a..fe49e758 100644
589 --- a/drivers/usb/gadget/udc/fsl_udc_core.c
590 +++ b/drivers/usb/gadget/udc/fsl_udc_core.c
591 @@ -198,7 +198,11 @@ __acquires(ep->udc->lock)
592
593 spin_unlock(&ep->udc->lock);
594
595 - usb_gadget_giveback_request(&ep->ep, &req->req);
596 + /* this complete() should a func implemented by gadget layer,
597 + * eg fsg->bulk_in_complete()
598 + */
599 + if (req->req.complete)
600 + usb_gadget_giveback_request(&ep->ep, &req->req);
601
602 spin_lock(&ep->udc->lock);
603 ep->stopped = stopped;
604 @@ -245,10 +249,10 @@ static int dr_controller_setup(struct fsl_udc *udc)
605 if (udc->pdata->have_sysif_regs) {
606 if (udc->pdata->controller_ver) {
607 /* controller version 1.6 or above */
608 - ctrl = __raw_readl(&usb_sys_regs->control);
609 + ctrl = ioread32be(&usb_sys_regs->control);
610 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
611 ctrl |= USB_CTRL_USB_EN;
612 - __raw_writel(ctrl, &usb_sys_regs->control);
613 + iowrite32be(ctrl, &usb_sys_regs->control);
614 }
615 }
616 portctrl |= PORTSCX_PTS_ULPI;
617 @@ -257,13 +261,14 @@ static int dr_controller_setup(struct fsl_udc *udc)
618 portctrl |= PORTSCX_PTW_16BIT;
619 /* fall through */
620 case FSL_USB2_PHY_UTMI:
621 + case FSL_USB2_PHY_UTMI_DUAL:
622 if (udc->pdata->have_sysif_regs) {
623 if (udc->pdata->controller_ver) {
624 /* controller version 1.6 or above */
625 - ctrl = __raw_readl(&usb_sys_regs->control);
626 + ctrl = ioread32be(&usb_sys_regs->control);
627 ctrl |= (USB_CTRL_UTMI_PHY_EN |
628 USB_CTRL_USB_EN);
629 - __raw_writel(ctrl, &usb_sys_regs->control);
630 + iowrite32be(ctrl, &usb_sys_regs->control);
631 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
632 PHY CLK to become stable - 10ms*/
633 }
634 @@ -329,22 +334,22 @@ static int dr_controller_setup(struct fsl_udc *udc)
635 /* Config control enable i/o output, cpu endian register */
636 #ifndef CONFIG_ARCH_MXC
637 if (udc->pdata->have_sysif_regs) {
638 - ctrl = __raw_readl(&usb_sys_regs->control);
639 + ctrl = ioread32be(&usb_sys_regs->control);
640 ctrl |= USB_CTRL_IOENB;
641 - __raw_writel(ctrl, &usb_sys_regs->control);
642 + iowrite32be(ctrl, &usb_sys_regs->control);
643 }
644 #endif
645
646 -#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
647 +#if !defined(CONFIG_NOT_COHERENT_CACHE)
648 /* Turn on cache snooping hardware, since some PowerPC platforms
649 * wholly rely on hardware to deal with cache coherent. */
650
651 if (udc->pdata->have_sysif_regs) {
652 /* Setup Snooping for all the 4GB space */
653 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
654 - __raw_writel(tmp, &usb_sys_regs->snoop1);
655 + iowrite32be(tmp, &usb_sys_regs->snoop1);
656 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
657 - __raw_writel(tmp, &usb_sys_regs->snoop2);
658 + iowrite32be(tmp, &usb_sys_regs->snoop2);
659 }
660 #endif
661
662 @@ -1057,7 +1062,7 @@ static int fsl_ep_fifo_status(struct usb_ep *_ep)
663 struct ep_queue_head *qh;
664
665 ep = container_of(_ep, struct fsl_ep, ep);
666 - if (!_ep || (!ep->ep.desc && ep_index(ep) != 0))
667 + if (!_ep || !ep->ep.desc || (ep_index(ep) == 0))
668 return -ENODEV;
669
670 udc = (struct fsl_udc *)ep->udc;
671 @@ -1599,14 +1604,13 @@ static int process_ep_req(struct fsl_udc *udc, int pipe,
672 struct fsl_req *curr_req)
673 {
674 struct ep_td_struct *curr_td;
675 - int td_complete, actual, remaining_length, j, tmp;
676 + int actual, remaining_length, j, tmp;
677 int status = 0;
678 int errors = 0;
679 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
680 int direction = pipe % 2;
681
682 curr_td = curr_req->head;
683 - td_complete = 0;
684 actual = curr_req->req.length;
685
686 for (j = 0; j < curr_req->dtd_count; j++) {
687 @@ -1651,11 +1655,9 @@ static int process_ep_req(struct fsl_udc *udc, int pipe,
688 status = -EPROTO;
689 break;
690 } else {
691 - td_complete++;
692 break;
693 }
694 } else {
695 - td_complete++;
696 VDBG("dTD transmitted successful");
697 }
698
699 @@ -1698,7 +1700,7 @@ static void dtd_complete_irq(struct fsl_udc *udc)
700 curr_ep = get_ep_by_pipe(udc, i);
701
702 /* If the ep is configured */
703 - if (curr_ep->name == NULL) {
704 + if (strncmp(curr_ep->name, "ep", 2)) {
705 WARNING("Invalid EP?");
706 continue;
707 }
708 @@ -2420,10 +2422,12 @@ static int fsl_udc_probe(struct platform_device *pdev)
709 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
710 #endif
711
712 +#ifdef CONFIG_ARCH_MXC
713 /* Initialize USB clocks */
714 ret = fsl_udc_clk_init(pdev);
715 if (ret < 0)
716 goto err_iounmap_noclk;
717 +#endif
718
719 /* Read Device Controller Capability Parameters register */
720 dccparams = fsl_readl(&dr_regs->dccparams);
721 @@ -2463,9 +2467,11 @@ static int fsl_udc_probe(struct platform_device *pdev)
722 dr_controller_setup(udc_controller);
723 }
724
725 +#ifdef CONFIG_ARCH_MXC
726 ret = fsl_udc_clk_finalize(pdev);
727 if (ret)
728 goto err_free_irq;
729 +#endif
730
731 /* Setup gadget structure */
732 udc_controller->gadget.ops = &fsl_gadget_ops;
733 @@ -2478,6 +2484,7 @@ static int fsl_udc_probe(struct platform_device *pdev)
734 /* Setup gadget.dev and register with kernel */
735 dev_set_name(&udc_controller->gadget.dev, "gadget");
736 udc_controller->gadget.dev.of_node = pdev->dev.of_node;
737 + set_dma_ops(&udc_controller->gadget.dev, pdev->dev.archdata.dma_ops);
738
739 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
740 udc_controller->gadget.is_otg = 1;
741 @@ -2529,7 +2536,9 @@ static int fsl_udc_probe(struct platform_device *pdev)
742 err_iounmap:
743 if (pdata->exit)
744 pdata->exit(pdev);
745 +#ifdef CONFIG_ARCH_MXC
746 fsl_udc_clk_release();
747 +#endif
748 err_iounmap_noclk:
749 iounmap(dr_regs);
750 err_release_mem_region:
751 @@ -2557,8 +2566,9 @@ static int fsl_udc_remove(struct platform_device *pdev)
752 udc_controller->done = &done;
753 usb_del_gadget_udc(&udc_controller->gadget);
754
755 +#ifdef CONFIG_ARCH_MXC
756 fsl_udc_clk_release();
757 -
758 +#endif
759 /* DR has been stopped in usb_gadget_unregister_driver() */
760 remove_proc_file();
761
762 @@ -2570,7 +2580,7 @@ static int fsl_udc_remove(struct platform_device *pdev)
763 dma_pool_destroy(udc_controller->td_pool);
764 free_irq(udc_controller->irq, udc_controller);
765 iounmap(dr_regs);
766 - if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
767 + if (res && (pdata->operating_mode == FSL_USB2_DR_DEVICE))
768 release_mem_region(res->start, resource_size(res));
769
770 /* free udc --wait for the release() finished */
771 diff --git a/drivers/usb/gadget/udc/fsl_usb2_udc.h b/drivers/usb/gadget/udc/fsl_usb2_udc.h
772 index 84715625..f76c4ddd 100644
773 --- a/drivers/usb/gadget/udc/fsl_usb2_udc.h
774 +++ b/drivers/usb/gadget/udc/fsl_usb2_udc.h
775 @@ -20,6 +20,10 @@
776 #define USB_MAX_CTRL_PAYLOAD 64
777 #define USB_DR_SYS_OFFSET 0x400
778
779 +#ifdef CONFIG_SOC_LS1021A
780 +#undef CONFIG_ARCH_MXC
781 +#endif
782 +
783 /* USB DR device mode registers (Little Endian) */
784 struct usb_dr_device {
785 /* Capability register */
786 @@ -597,18 +601,6 @@ struct platform_device;
787 int fsl_udc_clk_init(struct platform_device *pdev);
788 int fsl_udc_clk_finalize(struct platform_device *pdev);
789 void fsl_udc_clk_release(void);
790 -#else
791 -static inline int fsl_udc_clk_init(struct platform_device *pdev)
792 -{
793 - return 0;
794 -}
795 -static inline int fsl_udc_clk_finalize(struct platform_device *pdev)
796 -{
797 - return 0;
798 -}
799 -static inline void fsl_udc_clk_release(void)
800 -{
801 -}
802 #endif
803
804 #endif
805 diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
806 index 0b80cee3..a57d95c3 100644
807 --- a/drivers/usb/host/Kconfig
808 +++ b/drivers/usb/host/Kconfig
809 @@ -165,7 +165,7 @@ config XPS_USB_HCD_XILINX
810
811 config USB_EHCI_FSL
812 tristate "Support for Freescale PPC on-chip EHCI USB controller"
813 - depends on FSL_SOC
814 + depends on USB_EHCI_HCD
815 select USB_EHCI_ROOT_HUB_TT
816 ---help---
817 Variation of ARC USB block used in some Freescale chips.
818 diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
819 index 9f5ffb62..cd16860c 100644
820 --- a/drivers/usb/host/ehci-fsl.c
821 +++ b/drivers/usb/host/ehci-fsl.c
822 @@ -37,13 +37,141 @@
823 #include <linux/fsl_devices.h>
824 #include <linux/of_platform.h>
825
826 +#ifdef CONFIG_PPC
827 +#include <asm/fsl_pm.h>
828 +#include <linux/suspend.h>
829 +#endif
830 +
831 #include "ehci.h"
832 #include "ehci-fsl.h"
833
834 +#define FSL_USB_PHY_ADDR 0xffe214000
835 +
836 +struct ccsr_usb_port_ctrl {
837 + u32 ctrl;
838 + u32 drvvbuscfg;
839 + u32 pwrfltcfg;
840 + u32 sts;
841 + u8 res_14[0xc];
842 + u32 bistcfg;
843 + u32 biststs;
844 + u32 abistcfg;
845 + u32 abiststs;
846 + u8 res_30[0x10];
847 + u32 xcvrprg;
848 + u32 anaprg;
849 + u32 anadrv;
850 + u32 anasts;
851 +};
852 +
853 +struct ccsr_usb_phy {
854 + u32 id;
855 + struct ccsr_usb_port_ctrl port1;
856 + u8 res_50[0xc];
857 + u32 tvr;
858 + u32 pllprg[4];
859 + u8 res_70[0x4];
860 + u32 anaccfg;
861 + u32 dbg;
862 + u8 res_7c[0x4];
863 + struct ccsr_usb_port_ctrl port2;
864 + u8 res_dc[0x334];
865 +};
866 +
867 #define DRIVER_DESC "Freescale EHCI Host controller driver"
868 #define DRV_NAME "ehci-fsl"
869
870 static struct hc_driver __read_mostly fsl_ehci_hc_driver;
871 +struct ehci_fsl {
872 + /* store current hcd state for otg;
873 + * have_hcd is true when host drv al already part of otg framework,
874 + * otherwise false;
875 + * hcd_add is true when otg framework wants to add host
876 + * drv as part of otg;flase when it wants to remove it
877 + */
878 +unsigned have_hcd:1;
879 +unsigned hcd_add:1;
880 +};
881 +
882 +static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
883 +{
884 +struct ehci_hcd *ehci = hcd_to_ehci(hcd);
885 +
886 +return container_of(ehci, struct ehci_fsl, ehci);
887 +}
888 +
889 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
890 +static void do_change_hcd(struct work_struct *work)
891 +{
892 +struct ehci_hcd *ehci = container_of(work, struct ehci_hcd,
893 + change_hcd_work);
894 +struct usb_hcd *hcd = ehci_to_hcd(ehci);
895 +struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
896 +void __iomem *non_ehci = hcd->regs;
897 +int retval;
898 +
899 + if (ehci_fsl->hcd_add && !ehci_fsl->have_hcd) {
900 + writel(USBMODE_CM_HOST, non_ehci + FSL_SOC_USB_USBMODE);
901 + /* host, gadget and otg share same int line */
902 + retval = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
903 + if (retval == 0)
904 + ehci_fsl->have_hcd = 1;
905 + } else if (!ehci_fsl->hcd_add && ehci_fsl->have_hcd) {
906 + usb_remove_hcd(hcd);
907 + ehci_fsl->have_hcd = 0;
908 + }
909 +}
910 +#endif
911 +
912 +struct ehci_fsl {
913 + struct ehci_hcd ehci;
914 +
915 +#ifdef CONFIG_PM
916 +struct ehci_regs saved_regs;
917 +struct ccsr_usb_phy saved_phy_regs;
918 +/* Saved USB PHY settings, need to restore after deep sleep. */
919 +u32 usb_ctrl;
920 +#endif
921 + /*
922 + * store current hcd state for otg;
923 + * have_hcd is true when host drv al already part of otg framework,
924 + * otherwise false;
925 + * hcd_add is true when otg framework wants to add host
926 + * drv as part of otg;flase when it wants to remove it
927 + */
928 +unsigned have_hcd:1;
929 +unsigned hcd_add:1;
930 +};
931 +
932 +static strut ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
933 +{
934 +struct ehci_hcd *ehci = hcd_to_ehci(hcd);
935 +
936 +return container_of(ehci, struct ehci_fsl, ehci);
937 +}
938 +
939 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
940 +static void do_change_hcd(struct work_struct *work)
941 +{
942 +struct ehci_hcd *ehci = container_of(work, struct ehci_hcd,
943 +change_hcd_work);
944 +struct usb_hcd *hcd = ehci_to_hcd(ehci);
945 +struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
946 +void __iomem *non_ehci = hcd->regs;
947 +int retval;
948 +
949 +if (ehci_fsl->hcd_add && !ehci_fsl->have_hcd) {
950 +writel(USBMODE_CM_HOST, non_ehci + FSL_SOC_USB_USBMODE);
951 +/* host, gadget and otg share same int line */
952 +retval = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
953 +if (retval == 0)
954 +ehci_fsl->have_hcd = 1;
955 +} else if (!ehci_fsl->hcd_add && ehci_fsl->have_hcd) {
956 + usb_remove_hcd(hcd);
957 +ehci_fsl->have_hcd = 0;
958 +}
959 +}
960 +#endif
961
962 /* configure so an HC device and id are always provided */
963 /* always called with process context; sleeping is OK */
964 @@ -131,6 +259,12 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
965 clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
966 CONTROL_REGISTER_W1C_MASK, 0x4);
967
968 + /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
969 + if (pdata->controller_ver == FSL_USB_VER_2_5 &&
970 + pdata->phy_mode == FSL_USB2_PHY_ULPI)
971 + iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL);
972 +
973 +
974 /*
975 * Enable UTMI phy and program PTS field in UTMI mode before asserting
976 * controller reset for USB Controller version 2.5
977 @@ -143,16 +277,20 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
978
979 /* Don't need to set host mode here. It will be done by tdi_reset() */
980
981 - retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
982 + retval = usb_add_hcd(hcd, irq, IRQF_SHARED | IRQF_NO_SUSPEND);
983 if (retval != 0)
984 goto err2;
985 device_wakeup_enable(hcd->self.controller);
986
987 -#ifdef CONFIG_USB_OTG
988 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
989 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
990 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
991 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
992
993 hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
994 +
995 + INIT_WORK(&ehci->change_hcd_work, do_change_hcd);
996 +
997 dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n",
998 hcd, ehci, hcd->usb_phy);
999
1000 @@ -168,6 +306,11 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
1001 retval = -ENODEV;
1002 goto err2;
1003 }
1004 +
1005 + ehci_fsl->have_hcd = 1;
1006 + } else {
1007 + dev_err(&pdev->dev, "wrong operating mode\n");
1008 + return -ENODEV;
1009 }
1010 #endif
1011 return retval;
1012 @@ -181,6 +324,18 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev)
1013 return retval;
1014 }
1015
1016 +static bool usb_phy_clk_valid(struct usb_hcd *hcd,
1017 + enum fsl_usb2_phy_modes phy_mode)
1018 +{
1019 + void __iomem *non_ehci = hcd->regs;
1020 + bool ret = true;
1021 +
1022 + if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
1023 + ret = false;
1024 +
1025 + return ret;
1026 +}
1027 +
1028 static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
1029 enum fsl_usb2_phy_modes phy_mode,
1030 unsigned int port_offset)
1031 @@ -219,6 +374,21 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
1032 /* fall through */
1033 case FSL_USB2_PHY_UTMI:
1034 case FSL_USB2_PHY_UTMI_DUAL:
1035 + if (pdata->has_fsl_erratum_a006918) {
1036 + pr_warn("fsl-ehci: USB PHY clock invalid\n");
1037 + return -EINVAL;
1038 + }
1039 +
1040 + /* PHY_CLK_VALID bit is de-featured from all controller
1041 + * versions below 2.4 and is to be checked only for
1042 + * internal UTMI phy
1043 + */
1044 + if (pdata->controller_ver > FSL_USB_VER_2_4 &&
1045 + pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
1046 + pr_err("fsl-ehci: USB PHY clock invalid\n");
1047 + return -EINVAL;
1048 + }
1049 +
1050 if (pdata->have_sysif_regs && pdata->controller_ver) {
1051 /* controller version 1.6 or above */
1052 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
1053 @@ -292,14 +462,9 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
1054 return -EINVAL;
1055
1056 if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
1057 - unsigned int chip, rev, svr;
1058 -
1059 - svr = mfspr(SPRN_SVR);
1060 - chip = svr >> 16;
1061 - rev = (svr >> 4) & 0xf;
1062
1063 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
1064 - if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
1065 + if (pdata->has_fsl_erratum_14 == 1)
1066 ehci->has_fsl_port_bug = 1;
1067
1068 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
1069 @@ -379,16 +544,57 @@ static int ehci_fsl_setup(struct usb_hcd *hcd)
1070 return retval;
1071 }
1072
1073 -struct ehci_fsl {
1074 - struct ehci_hcd ehci;
1075
1076 #ifdef CONFIG_PM
1077 - /* Saved USB PHY settings, need to restore after deep sleep. */
1078 - u32 usb_ctrl;
1079 -#endif
1080 -};
1081 +void __iomem *phy_reg;
1082
1083 -#ifdef CONFIG_PM
1084 +#ifdef CONFIG_PPC
1085 +/* save usb registers */
1086 +static int ehci_fsl_save_context(struct usb_hcd *hcd)
1087 +{
1088 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1089 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1090 + void __iomem *non_ehci = hcd->regs;
1091 + struct device *dev = hcd->self.controller;
1092 + struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
1093 +
1094 + if (pdata->phy_mode == FSL_USB2_PHY_UTMI_DUAL) {
1095 + phy_reg = ioremap(FSL_USB_PHY_ADDR,
1096 + sizeof(struct ccsr_usb_phy));
1097 + _memcpy_fromio((void *)&ehci_fsl->saved_phy_regs, phy_reg,
1098 + sizeof(struct ccsr_usb_phy));
1099 + }
1100 +
1101 + _memcpy_fromio((void *)&ehci_fsl->saved_regs, ehci->regs,
1102 + sizeof(struct ehci_regs));
1103 + ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
1104 +
1105 + return 0;
1106 +}
1107 +
1108 +/*Restore usb registers */
1109 +static int ehci_fsl_restore_context(struct usb_hcd *hcd)
1110 +{
1111 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1112 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1113 + void __iomem *non_ehci = hcd->regs;
1114 + struct device *dev = hcd->self.controller;
1115 + struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
1116 +
1117 + if (pdata->phy_mode == FSL_USB2_PHY_UTMI_DUAL) {
1118 + if (phy_reg)
1119 + _memcpy_toio(phy_reg,
1120 + (void *)&ehci_fsl->saved_phy_regs,
1121 + sizeof(struct ccsr_usb_phy));
1122 + }
1123 +
1124 + _memcpy_toio(ehci->regs, (void *)&ehci_fsl->saved_regs,
1125 + sizeof(struct ehci_regs));
1126 + iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL);
1127 +
1128 + return 0;
1129 +}
1130 +#endif
1131
1132 #ifdef CONFIG_PPC_MPC512x
1133 static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
1134 @@ -535,26 +741,43 @@ static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
1135 }
1136 #endif /* CONFIG_PPC_MPC512x */
1137
1138 -static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
1139 -{
1140 - struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1141 -
1142 - return container_of(ehci, struct ehci_fsl, ehci);
1143 -}
1144 -
1145 static int ehci_fsl_drv_suspend(struct device *dev)
1146 {
1147 struct usb_hcd *hcd = dev_get_drvdata(dev);
1148 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1149 void __iomem *non_ehci = hcd->regs;
1150 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1151 + struct usb_bus host = hcd->self;
1152 +#endif
1153 +
1154 +#ifdef CONFIG_PPC
1155 +suspend_state_t pm_state;
1156 +pm_state = pm_suspend_state();
1157 +
1158 +if (pm_state == PM_SUSPEND_MEM)
1159 + ehci_fsl_save_context(hcd);
1160 +#endif
1161
1162 if (of_device_is_compatible(dev->parent->of_node,
1163 "fsl,mpc5121-usb2-dr")) {
1164 return ehci_fsl_mpc512x_drv_suspend(dev);
1165 }
1166
1167 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1168 + if (host.is_otg) {
1169 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1170 +
1171 + /* remove hcd */
1172 + ehci_fsl->hcd_add = 0;
1173 + schedule_work(&ehci->change_hcd_work);
1174 + host.is_otg = 0;
1175 + return 0;
1176 + }
1177 +#endif
1178 +
1179 ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
1180 device_may_wakeup(dev));
1181 +
1182 if (!fsl_deep_sleep())
1183 return 0;
1184
1185 @@ -568,12 +791,34 @@ static int ehci_fsl_drv_resume(struct device *dev)
1186 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1187 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1188 void __iomem *non_ehci = hcd->regs;
1189 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1190 + struct usb_bus host = hcd->self;
1191 +#endif
1192 +
1193 +#ifdef CONFIG_PPC
1194 +suspend_state_t pm_state;
1195 +pm_state = pm_suspend_state();
1196 +
1197 +if (pm_state == PM_SUSPEND_MEM)
1198 + ehci_fsl_restore_context(hcd);
1199 +#endif
1200
1201 if (of_device_is_compatible(dev->parent->of_node,
1202 "fsl,mpc5121-usb2-dr")) {
1203 return ehci_fsl_mpc512x_drv_resume(dev);
1204 }
1205
1206 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1207 + if (host.is_otg) {
1208 + /* add hcd */
1209 + ehci_fsl->hcd_add = 1;
1210 + schedule_work(&ehci->change_hcd_work);
1211 + usb_hcd_resume_root_hub(hcd);
1212 + host.is_otg = 0;
1213 + return 0;
1214 + }
1215 +#endif
1216 +
1217 ehci_prepare_ports_for_controller_resume(ehci);
1218 if (!fsl_deep_sleep())
1219 return 0;
1220 diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
1221 index 1a8a60a5..42ea2976 100644
1222 --- a/drivers/usb/host/ehci-fsl.h
1223 +++ b/drivers/usb/host/ehci-fsl.h
1224 @@ -63,4 +63,7 @@
1225 #define UTMI_PHY_EN (1<<9)
1226 #define ULPI_PHY_CLK_SEL (1<<10)
1227 #define PHY_CLK_VALID (1<<17)
1228 +
1229 +/* Retry count for checking UTMI PHY CLK validity */
1230 +#define UTMI_PHY_CLK_VALID_CHK_RETRY 5
1231 #endif /* _EHCI_FSL_H */
1232 diff --git a/drivers/usb/host/ehci-hub.c b/drivers/usb/host/ehci-hub.c
1233 index 255acca8..c8838c33 100644
1234 --- a/drivers/usb/host/ehci-hub.c
1235 +++ b/drivers/usb/host/ehci-hub.c
1236 @@ -305,6 +305,8 @@ static int ehci_bus_suspend (struct usb_hcd *hcd)
1237 USB_PORT_STAT_HIGH_SPEED)
1238 fs_idle_delay = true;
1239 ehci_writel(ehci, t2, reg);
1240 + if (ehci_has_fsl_susp_errata(ehci))
1241 + usleep_range(10000, 20000);
1242 changed = 1;
1243 }
1244 }
1245 diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
1246 index 3b06bb77..f296d1fb 100644
1247 --- a/drivers/usb/host/ehci.h
1248 +++ b/drivers/usb/host/ehci.h
1249 @@ -180,6 +180,9 @@ struct ehci_hcd { /* one per controller */
1250 unsigned periodic_count; /* periodic activity count */
1251 unsigned uframe_periodic_max; /* max periodic time per uframe */
1252
1253 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1254 + struct work_struct change_hcd_work;
1255 +#endif
1256
1257 /* list of itds & sitds completed while now_frame was still active */
1258 struct list_head cached_itd_list;
1259 @@ -706,8 +709,10 @@ ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
1260 * incoming packets get corrupted in HS mode
1261 */
1262 #define ehci_has_fsl_hs_errata(e) ((e)->has_fsl_hs_errata)
1263 +#define ehci_has_fsl_susp_errata(e) ((e)->has_fsl_susp_errata)
1264 #else
1265 #define ehci_has_fsl_hs_errata(e) (0)
1266 +#define ehci_has_fsl_susp_errata(e) (0)
1267 #endif
1268
1269 /*
1270 diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
1271 index f07ccb25..1e59ea9f 100644
1272 --- a/drivers/usb/host/fsl-mph-dr-of.c
1273 +++ b/drivers/usb/host/fsl-mph-dr-of.c
1274 @@ -226,6 +226,18 @@ static int fsl_usb2_mph_dr_of_probe(struct platform_device *ofdev)
1275 of_property_read_bool(np, "fsl,usb-erratum-a007792");
1276 pdata->has_fsl_erratum_a005275 =
1277 of_property_read_bool(np, "fsl,usb-erratum-a005275");
1278 + pdata->has_fsl_erratum_a005697 =
1279 + of_property_read_bool(np, "fsl,usb_erratum-a005697");
1280 + if (of_get_property(np, "fsl,erratum_a006918", NULL))
1281 + pdata->has_fsl_erratum_a006918 = 1;
1282 + else
1283 + pdata->has_fsl_erratum_a006918 = 0;
1284 +
1285 + if (of_get_property(np, "fsl,usb_erratum_14", NULL))
1286 + pdata->has_fsl_erratum_14 = 1;
1287 + else
1288 + pdata->has_fsl_erratum_14 = 0;
1289 +
1290
1291 /*
1292 * Determine whether phy_clk_valid needs to be checked
1293 diff --git a/drivers/usb/phy/phy-fsl-usb.c b/drivers/usb/phy/phy-fsl-usb.c
1294 index 94eb2923..836355fa 100644
1295 --- a/drivers/usb/phy/phy-fsl-usb.c
1296 +++ b/drivers/usb/phy/phy-fsl-usb.c
1297 @@ -1,5 +1,5 @@
1298 /*
1299 - * Copyright (C) 2007,2008 Freescale semiconductor, Inc.
1300 + * Copyright 2007,2008 Freescale Semiconductor, Inc.
1301 *
1302 * Author: Li Yang <LeoLi@freescale.com>
1303 * Jerry Huang <Chang-Ming.Huang@freescale.com>
1304 @@ -463,6 +463,7 @@ void otg_reset_controller(void)
1305 int fsl_otg_start_host(struct otg_fsm *fsm, int on)
1306 {
1307 struct usb_otg *otg = fsm->otg;
1308 + struct usb_bus *host = otg->host;
1309 struct device *dev;
1310 struct fsl_otg *otg_dev =
1311 container_of(otg->usb_phy, struct fsl_otg, phy);
1312 @@ -486,6 +487,7 @@ int fsl_otg_start_host(struct otg_fsm *fsm, int on)
1313 otg_reset_controller();
1314 VDBG("host on......\n");
1315 if (dev->driver->pm && dev->driver->pm->resume) {
1316 + host->is_otg = 1;
1317 retval = dev->driver->pm->resume(dev);
1318 if (fsm->id) {
1319 /* default-b */
1320 @@ -510,8 +512,11 @@ int fsl_otg_start_host(struct otg_fsm *fsm, int on)
1321 else {
1322 VDBG("host off......\n");
1323 if (dev && dev->driver) {
1324 - if (dev->driver->pm && dev->driver->pm->suspend)
1325 + if (dev->driver->pm &&
1326 + dev->driver->pm->suspend) {
1327 + host->is_otg = 1;
1328 retval = dev->driver->pm->suspend(dev);
1329 + }
1330 if (fsm->id)
1331 /* default-b */
1332 fsl_otg_drv_vbus(fsm, 0);
1333 @@ -539,8 +544,17 @@ int fsl_otg_start_gadget(struct otg_fsm *fsm, int on)
1334 dev = otg->gadget->dev.parent;
1335
1336 if (on) {
1337 - if (dev->driver->resume)
1338 + /* Delay gadget resume to synchronize between host and gadget
1339 + * drivers. Upon role-reversal host drv is shutdown by kernel
1340 + * worker thread. By the time host drv shuts down, controller
1341 + * gets programmed for gadget role. Shutting host drv after
1342 + * this results in controller getting reset, and it stops
1343 + * responding to otg events
1344 + */
1345 + if (dev->driver->resume) {
1346 + msleep(1000);
1347 dev->driver->resume(dev);
1348 + }
1349 } else {
1350 if (dev->driver->suspend)
1351 dev->driver->suspend(dev, otg_suspend_state);
1352 @@ -672,6 +686,10 @@ static void fsl_otg_event(struct work_struct *work)
1353 fsl_otg_start_host(fsm, 0);
1354 otg_drv_vbus(fsm, 0);
1355 fsl_otg_start_gadget(fsm, 1);
1356 + } else {
1357 + fsl_otg_start_gadget(fsm, 0);
1358 + otg_drv_vbus(fsm, 1);
1359 + fsl_otg_start_host(fsm, 1);
1360 }
1361 }
1362
1363 @@ -724,6 +742,7 @@ irqreturn_t fsl_otg_isr(int irq, void *dev_id)
1364 {
1365 struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm;
1366 struct usb_otg *otg = ((struct fsl_otg *)dev_id)->phy.otg;
1367 + struct fsl_otg *otg_dev = dev_id;
1368 u32 otg_int_src, otg_sc;
1369
1370 otg_sc = fsl_readl(&usb_dr_regs->otgsc);
1371 @@ -753,18 +772,8 @@ irqreturn_t fsl_otg_isr(int irq, void *dev_id)
1372 otg->gadget->is_a_peripheral = !fsm->id;
1373 VDBG("ID int (ID is %d)\n", fsm->id);
1374
1375 - if (fsm->id) { /* switch to gadget */
1376 - schedule_delayed_work(
1377 - &((struct fsl_otg *)dev_id)->otg_event,
1378 - 100);
1379 - } else { /* switch to host */
1380 - cancel_delayed_work(&
1381 - ((struct fsl_otg *)dev_id)->
1382 - otg_event);
1383 - fsl_otg_start_gadget(fsm, 0);
1384 - otg_drv_vbus(fsm, 1);
1385 - fsl_otg_start_host(fsm, 1);
1386 - }
1387 + schedule_delayed_work(&otg_dev->otg_event, 100);
1388 +
1389 return IRQ_HANDLED;
1390 }
1391 }
1392 @@ -923,12 +932,32 @@ int usb_otg_start(struct platform_device *pdev)
1393 temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
1394 switch (pdata->phy_mode) {
1395 case FSL_USB2_PHY_ULPI:
1396 + if (pdata->controller_ver) {
1397 + /* controller version 1.6 or above */
1398 + setbits32(&p_otg->dr_mem_map->control,
1399 + USB_CTRL_ULPI_PHY_CLK_SEL);
1400 + /*
1401 + * Due to controller issue of PHY_CLK_VALID in ULPI
1402 + * mode, we set USB_CTRL_USB_EN before checking
1403 + * PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work.
1404 + */
1405 + clrsetbits_be32(&p_otg->dr_mem_map->control,
1406 + USB_CTRL_UTMI_PHY_EN, USB_CTRL_IOENB);
1407 + }
1408 temp |= PORTSC_PTS_ULPI;
1409 break;
1410 case FSL_USB2_PHY_UTMI_WIDE:
1411 temp |= PORTSC_PTW_16BIT;
1412 /* fall through */
1413 case FSL_USB2_PHY_UTMI:
1414 + if (pdata->controller_ver) {
1415 + /* controller version 1.6 or above */
1416 + setbits32(&p_otg->dr_mem_map->control,
1417 + USB_CTRL_UTMI_PHY_EN);
1418 + /* Delay for UTMI PHY CLK to become stable - 10ms */
1419 + mdelay(FSL_UTMI_PHY_DLY);
1420 + }
1421 + setbits32(&p_otg->dr_mem_map->control, USB_CTRL_UTMI_PHY_EN);
1422 temp |= PORTSC_PTS_UTMI;
1423 /* fall through */
1424 default:
1425 diff --git a/drivers/usb/phy/phy-fsl-usb.h b/drivers/usb/phy/phy-fsl-usb.h
1426 index 23149954..c4c08730 100644
1427 --- a/drivers/usb/phy/phy-fsl-usb.h
1428 +++ b/drivers/usb/phy/phy-fsl-usb.h
1429 @@ -199,6 +199,14 @@
1430 /* control Register Bit Masks */
1431 #define USB_CTRL_IOENB (0x1<<2)
1432 #define USB_CTRL_ULPI_INT0EN (0x1<<0)
1433 +#define USB_CTRL_WU_INT_EN (0x1<<1)
1434 +#define USB_CTRL_LINE_STATE_FILTER__EN (0x1<<3)
1435 +#define USB_CTRL_KEEP_OTG_ON (0x1<<4)
1436 +#define USB_CTRL_OTG_PORT (0x1<<5)
1437 +#define USB_CTRL_PLL_RESET (0x1<<8)
1438 +#define USB_CTRL_UTMI_PHY_EN (0x1<<9)
1439 +#define USB_CTRL_ULPI_PHY_CLK_SEL (0x1<<10)
1440 +#define USB_CTRL_PHY_CLK_VALID (0x1<<17)
1441
1442 /* BCSR5 */
1443 #define BCSR5_INT_USB (0x02)
1444 diff --git a/include/linux/usb.h b/include/linux/usb.h
1445 index eba1f10e..c334e281 100644
1446 --- a/include/linux/usb.h
1447 +++ b/include/linux/usb.h
1448 @@ -362,6 +362,7 @@ struct usb_bus {
1449 * for control transfers?
1450 */
1451 u8 otg_port; /* 0, or number of OTG/HNP port */
1452 + unsigned is_otg:1; /* true when host is also otg */
1453 unsigned is_b_host:1; /* true during some HNP roleswitches */
1454 unsigned b_hnp_enable:1; /* OTG: did A-Host enable HNP? */
1455 unsigned no_stop_on_short:1; /*
1456 diff --git a/include/linux/usb/of.h b/include/linux/usb/of.h
1457 index 5ff9032e..2a57e0d2 100644
1458 --- a/include/linux/usb/of.h
1459 +++ b/include/linux/usb/of.h
1460 @@ -11,6 +11,8 @@
1461 #include <linux/usb/otg.h>
1462 #include <linux/usb/phy.h>
1463
1464 +enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np);
1465 +
1466 #if IS_ENABLED(CONFIG_OF)
1467 enum usb_dr_mode of_usb_get_dr_mode_by_phy(struct device_node *np, int arg0);
1468 bool of_usb_host_tpl_support(struct device_node *np);
1469 --
1470 2.14.1
1471
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