target/linux/layerscape/patches-4.9/814-rtc-support-layerscape.patch

   1 From 7e7944c484954ff7b5d53047194e59bfffd1540a Mon Sep 17 00:00:00 2001
   2 From: Yangbo Lu <yangbo.lu@nxp.com>
   3 Date: Mon, 25 Sep 2017 12:20:55 +0800
   4 Subject: [PATCH] rtc: support layerscape
   5
   6 This is a integrated patch for layerscape rtc support.
   7
   8 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
   9 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  10 ---
  11  drivers/rtc/rtc-pcf85263.c | 665 +++++++++++++++++++++++++++++++++++++++++++++
  12  1 file changed, 665 insertions(+)
  13  create mode 100644 drivers/rtc/rtc-pcf85263.c
  14
  15 diff --git a/drivers/rtc/rtc-pcf85263.c b/drivers/rtc/rtc-pcf85263.c
  16 new file mode 100644
  17 index 00000000..629c2840
  18 --- /dev/null
  19 +++ b/drivers/rtc/rtc-pcf85263.c
  20 @@ -0,0 +1,665 @@
  21 +/*
  22 + * rtc-pcf85263 Driver for the NXP PCF85263 RTC
  23 + * Copyright 2016 Parkeon
  24 + *
  25 + * This program is free software; you can redistribute it and/or modify
  26 + * it under the terms of the GNU General Public License version 2 as
  27 + * published by the Free Software Foundation.
  28 + */
  29 +
  30 +#include <linux/module.h>
  31 +#include <linux/mutex.h>
  32 +#include <linux/rtc.h>
  33 +#include <linux/i2c.h>
  34 +#include <linux/bcd.h>
  35 +#include <linux/of.h>
  36 +#include <linux/of_device.h>
  37 +#include <linux/regmap.h>
  38 +
  39 +
  40 +#define DRV_NAME "rtc-pcf85263"
  41 +
  42 +/* Quartz capacitance */
  43 +#define PCF85263_QUARTZCAP_7pF         0
  44 +#define PCF85263_QUARTZCAP_6pF         1
  45 +#define PCF85263_QUARTZCAP_12p5pF      2
  46 +
  47 +/* Quartz drive strength */
  48 +#define PCF85263_QUARTZDRIVE_NORMAL    0
  49 +#define PCF85263_QUARTZDRIVE_LOW       1
  50 +#define PCF85263_QUARTZDRIVE_HIGH      2
  51 +
  52 +
  53 +#define PCF85263_REG_RTC_SC    0x01    /* Seconds */
  54 +#define PCF85263_REG_RTC_SC_OS         BIT(7)  /* Oscilator stopped flag */
  55 +
  56 +#define PCF85263_REG_RTC_MN    0x02    /* Minutes */
  57 +#define PCF85263_REG_RTC_HR    0x03    /* Hours */
  58 +#define PCF85263_REG_RTC_DT    0x04    /* Day of month 1-31 */
  59 +#define PCF85263_REG_RTC_DW    0x05    /* Day of week 0-6 */
  60 +#define PCF85263_REG_RTC_MO    0x06    /* Month 1-12 */
  61 +#define PCF85263_REG_RTC_YR    0x07    /* Year 0-99 */
  62 +
  63 +#define PCF85263_REG_ALM1_SC   0x08    /* Seconds */
  64 +#define PCF85263_REG_ALM1_MN   0x09    /* Minutes */
  65 +#define PCF85263_REG_ALM1_HR   0x0a    /* Hours */
  66 +#define PCF85263_REG_ALM1_DT   0x0b    /* Day of month 1-31 */
  67 +#define PCF85263_REG_ALM1_MO   0x0c    /* Month 1-12 */
  68 +
  69 +#define PCF85263_REG_ALM_CTL   0x10
  70 +#define PCF85263_REG_ALM_CTL_ALL_A1E   0x1f /* sec,min,hr,day,mon alarm 1 */
  71 +
  72 +#define PCF85263_REG_OSC       0x25
  73 +#define PCF85263_REG_OSC_CL_MASK       (BIT(0) | BIT(1))
  74 +#define PCF85263_REG_OSC_CL_SHIFT      0
  75 +#define PCF85263_REG_OSC_OSCD_MASK     (BIT(2) | BIT(3))
  76 +#define PCF85263_REG_OSC_OSCD_SHIFT    2
  77 +#define PCF85263_REG_OSC_LOWJ          BIT(4)
  78 +#define PCF85263_REG_OSC_12H           BIT(5)
  79 +
  80 +#define PCF85263_REG_PINIO     0x27
  81 +#define PCF85263_REG_PINIO_INTAPM_MASK (BIT(0) | BIT(1))
  82 +#define PCF85263_REG_PINIO_INTAPM_SHIFT        0
  83 +#define PCF85263_INTAPM_INTA   (0x2 << PCF85263_REG_PINIO_INTAPM_SHIFT)
  84 +#define PCF85263_INTAPM_HIGHZ  (0x3 << PCF85263_REG_PINIO_INTAPM_SHIFT)
  85 +#define PCF85263_REG_PINIO_TSPM_MASK   (BIT(2) | BIT(3))
  86 +#define PCF85263_REG_PINIO_TSPM_SHIFT  2
  87 +#define PCF85263_TSPM_DISABLED         (0x0 << PCF85263_REG_PINIO_TSPM_SHIFT)
  88 +#define PCF85263_TSPM_INTB             (0x1 << PCF85263_REG_PINIO_TSPM_SHIFT)
  89 +#define PCF85263_REG_PINIO_CLKDISABLE  BIT(7)
  90 +
  91 +#define PCF85263_REG_FUNCTION  0x28
  92 +#define PCF85263_REG_FUNCTION_COF_MASK 0x7
  93 +#define PCF85263_REG_FUNCTION_COF_OFF  0x7     /* No clock output */
  94 +
  95 +#define PCF85263_REG_INTA_CTL  0x29
  96 +#define PCF85263_REG_INTB_CTL  0x2A
  97 +#define PCF85263_REG_INTx_CTL_A1E      BIT(4)  /* Alarm 1 */
  98 +#define PCF85263_REG_INTx_CTL_ILP      BIT(7)  /* 0=pulse, 1=level */
  99 +
 100 +#define PCF85263_REG_FLAGS     0x2B
 101 +#define PCF85263_REG_FLAGS_A1F         BIT(5)
 102 +
 103 +#define PCF85263_REG_RAM_BYTE  0x2c
 104 +
 105 +#define PCF85263_REG_STOPENABLE 0x2e
 106 +#define PCF85263_REG_STOPENABLE_STOP   BIT(0)
 107 +
 108 +#define PCF85263_REG_RESET     0x2f    /* Reset command */
 109 +#define PCF85263_REG_RESET_CMD_CPR     0xa4    /* Clear prescaler */
 110 +
 111 +#define PCF85263_MAX_REG 0x2f
 112 +
 113 +#define PCF85263_HR_PM         BIT(5)
 114 +
 115 +enum pcf85263_irqpin {
 116 +       PCF85263_IRQPIN_NONE,
 117 +       PCF85263_IRQPIN_INTA,
 118 +       PCF85263_IRQPIN_INTB
 119 +};
 120 +
 121 +static const char *const pcf85263_irqpin_names[] = {
 122 +       [PCF85263_IRQPIN_NONE] = "None",
 123 +       [PCF85263_IRQPIN_INTA] = "INTA",
 124 +       [PCF85263_IRQPIN_INTB] = "INTB"
 125 +};
 126 +
 127 +struct pcf85263 {
 128 +       struct device *dev;
 129 +       struct rtc_device *rtc;
 130 +       struct regmap *regmap;
 131 +       enum pcf85263_irqpin irq_pin;
 132 +       int irq;
 133 +       bool mode_12h;
 134 +};
 135 +
 136 +/*
 137 + * Helpers to convert 12h to 24h and vice versa.
 138 + * Values in register are stored in BCD with a PM flag in bit 5
 139 + *
 140 + * 23:00 <=> 11PM <=> 0x31
 141 + * 00:00 <=> 12AM <=> 0x12
 142 + * 01:00 <=> 1AM <=> 0x01
 143 + * 12:00 <=> 12PM <=> 0x32
 144 + * 13:00 <=> 1PM <=> 0x21
 145 + */
 146 +static int pcf85263_bcd12h_to_bin24h(int regval)
 147 +{
 148 +       int hr = bcd2bin(regval & 0x1f);
 149 +       bool pm = regval & PCF85263_HR_PM;
 150 +
 151 +       if (hr == 12)
 152 +               return pm ? 12 : 0;
 153 +
 154 +       return pm ? hr + 12 : hr;
 155 +}
 156 +
 157 +static int pcf85263_bin24h_to_bcd12h(int hr24)
 158 +{
 159 +       bool pm = hr24 >= 12;
 160 +       int hr12 = hr24 % 12;
 161 +
 162 +       if (!hr12)
 163 +               hr12++;
 164 +
 165 +       return bin2bcd(hr12) | pm ? 0 : PCF85263_HR_PM;
 166 +}
 167 +
 168 +static int pcf85263_read_time(struct device *dev, struct rtc_time *tm)
 169 +{
 170 +       struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
 171 +       const int first = PCF85263_REG_RTC_SC;
 172 +       const int last = PCF85263_REG_RTC_YR;
 173 +       const int len = last - first + 1;
 174 +       u8 regs[len];
 175 +       u8 hr_reg;
 176 +       int ret;
 177 +
 178 +       ret = regmap_bulk_read(pcf85263->regmap, first, regs, len);
 179 +       if (ret)
 180 +               return ret;
 181 +
 182 +       if (regs[PCF85263_REG_RTC_SC - first] & PCF85263_REG_RTC_SC_OS) {
 183 +               dev_warn(dev, "Oscillator stop detected, date/time is not reliable.\n");
 184 +               return -EINVAL;
 185 +       }
 186 +
 187 +       tm->tm_sec = bcd2bin(regs[PCF85263_REG_RTC_SC - first] & 0x7f);
 188 +       tm->tm_min = bcd2bin(regs[PCF85263_REG_RTC_MN - first] & 0x7f);
 189 +
 190 +       hr_reg = regs[PCF85263_REG_RTC_HR - first];
 191 +       if (pcf85263->mode_12h)
 192 +               tm->tm_hour = pcf85263_bcd12h_to_bin24h(hr_reg);
 193 +       else
 194 +               tm->tm_hour = bcd2bin(hr_reg & 0x3f);
 195 +
 196 +       tm->tm_mday = bcd2bin(regs[PCF85263_REG_RTC_DT - first]);
 197 +       tm->tm_wday = bcd2bin(regs[PCF85263_REG_RTC_DW - first]);
 198 +       tm->tm_mon  = bcd2bin(regs[PCF85263_REG_RTC_MO - first]) - 1;
 199 +       tm->tm_year = bcd2bin(regs[PCF85263_REG_RTC_YR - first]);
 200 +
 201 +       tm->tm_year += 100;  /* Assume 21st century */
 202 +
 203 +       return 0;
 204 +}
 205 +
 206 +static int pcf85263_set_time(struct device *dev, struct rtc_time *tm)
 207 +{
 208 +       struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
 209 +
 210 +       /*
 211 +        * Before setting time need to stop RTC and disable prescaler
 212 +        * Do this all in a single I2C transaction exploiting wraparound
 213 +        * as described in data sheet.
 214 +        * This means that the array below must be in register order
 215 +        */
 216 +       u8 regs[] = {
 217 +               PCF85263_REG_STOPENABLE_STOP,   /* STOP */
 218 +               PCF85263_REG_RESET_CMD_CPR,     /* Disable prescaler */
 219 +               /* Wrap around to register 0 (1/100s) */
 220 +               0,                              /* 1/100s always zero. */
 221 +               bin2bcd(tm->tm_sec),
 222 +               bin2bcd(tm->tm_min),
 223 +               bin2bcd(tm->tm_hour),           /* 24-hour */
 224 +               bin2bcd(tm->tm_mday),
 225 +               bin2bcd(tm->tm_wday + 1),
 226 +               bin2bcd(tm->tm_mon + 1),
 227 +               bin2bcd(tm->tm_year % 100)
 228 +       };
 229 +       int ret;
 230 +
 231 +       ret = regmap_bulk_write(pcf85263->regmap, PCF85263_REG_STOPENABLE,
 232 +                               regs, sizeof(regs));
 233 +       if (ret)
 234 +               return ret;
 235 +
 236 +       /* As we have set the time in 24H update the hardware for that */
 237 +       if (pcf85263->mode_12h) {
 238 +               pcf85263->mode_12h = false;
 239 +               ret = regmap_update_bits(pcf85263->regmap, PCF85263_REG_OSC,
 240 +                                        PCF85263_REG_OSC_12H, 0);
 241 +               if (ret)
 242 +                       return ret;
 243 +       }
 244 +
 245 +       /* Start it again */
 246 +       return regmap_write(pcf85263->regmap, PCF85263_REG_STOPENABLE, 0);
 247 +}
 248 +
 249 +static int pcf85263_enable_alarm(struct pcf85263 *pcf85263, bool enable)
 250 +{
 251 +       int reg;
 252 +       int ret;
 253 +
 254 +       ret = regmap_update_bits(pcf85263->regmap, PCF85263_REG_ALM_CTL,
 255 +                                PCF85263_REG_ALM_CTL_ALL_A1E,
 256 +                                enable ? PCF85263_REG_ALM_CTL_ALL_A1E : 0);
 257 +       if (ret)
 258 +               return ret;
 259 +
 260 +       switch (pcf85263->irq_pin) {
 261 +       case PCF85263_IRQPIN_NONE:
 262 +               return 0;
 263 +
 264 +       case PCF85263_IRQPIN_INTA:
 265 +               reg = PCF85263_REG_INTA_CTL;
 266 +               break;
 267 +
 268 +       case PCF85263_IRQPIN_INTB:
 269 +               reg = PCF85263_REG_INTB_CTL;
 270 +               break;
 271 +
 272 +       default:
 273 +               return -EINVAL;
 274 +       }
 275 +
 276 +       return regmap_update_bits(pcf85263->regmap, reg,
 277 +                                 PCF85263_REG_INTx_CTL_A1E,
 278 +                                 enable ? PCF85263_REG_INTx_CTL_A1E : 0);
 279 +}
 280 +
 281 +static int pcf85263_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 282 +{
 283 +       struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
 284 +       struct rtc_time *tm = &alarm->time;
 285 +       const int first = PCF85263_REG_ALM1_SC;
 286 +       const int last = PCF85263_REG_ALM1_MO;
 287 +       const int len = last - first + 1;
 288 +       u8 regs[len];
 289 +       u8 hr_reg;
 290 +       unsigned int regval;
 291 +       int ret;
 292 +
 293 +       ret = regmap_bulk_read(pcf85263->regmap, first, regs, len);
 294 +       if (ret)
 295 +               return ret;
 296 +
 297 +       tm->tm_sec = bcd2bin(regs[PCF85263_REG_ALM1_SC - first] & 0x7f);
 298 +       tm->tm_min = bcd2bin(regs[PCF85263_REG_ALM1_MN - first] & 0x7f);
 299 +
 300 +       hr_reg = regs[PCF85263_REG_ALM1_HR - first];
 301 +       if (pcf85263->mode_12h)
 302 +               tm->tm_hour = pcf85263_bcd12h_to_bin24h(hr_reg);
 303 +       else
 304 +               tm->tm_hour = bcd2bin(hr_reg & 0x3f);
 305 +
 306 +       tm->tm_mday = bcd2bin(regs[PCF85263_REG_ALM1_DT - first]);
 307 +       tm->tm_mon  = bcd2bin(regs[PCF85263_REG_ALM1_MO - first]) - 1;
 308 +       tm->tm_year = -1;
 309 +       tm->tm_wday = -1;
 310 +
 311 +       ret = regmap_read(pcf85263->regmap, PCF85263_REG_ALM_CTL, &regval);
 312 +       if (ret)
 313 +               return ret;
 314 +       alarm->enabled = !!(regval & PCF85263_REG_ALM_CTL_ALL_A1E);
 315 +
 316 +       ret = regmap_read(pcf85263->regmap, PCF85263_REG_FLAGS, &regval);
 317 +       if (ret)
 318 +               return ret;
 319 +       alarm->pending = !!(regval & PCF85263_REG_FLAGS_A1F);
 320 +
 321 +       return 0;
 322 +}
 323 +
 324 +static int pcf85263_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 325 +{
 326 +       struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
 327 +       struct rtc_time *tm = &alarm->time;
 328 +       const int first = PCF85263_REG_ALM1_SC;
 329 +       const int last = PCF85263_REG_ALM1_MO;
 330 +       const int len = last - first + 1;
 331 +       u8 regs[len];
 332 +       int ret;
 333 +
 334 +       /* Disable alarm comparison during update */
 335 +       ret = pcf85263_enable_alarm(pcf85263, false);
 336 +       if (ret)
 337 +               return ret;
 338 +
 339 +       /* Clear any pending alarm (write 0=>clr, 1=>no change) */
 340 +       ret = regmap_write(pcf85263->regmap, PCF85263_REG_FLAGS,
 341 +                          (unsigned int)(~PCF85263_REG_FLAGS_A1F));
 342 +       if (ret)
 343 +               return ret;
 344 +
 345 +       /* Set the alarm time registers */
 346 +       regs[PCF85263_REG_ALM1_SC - first] = bin2bcd(tm->tm_sec);
 347 +       regs[PCF85263_REG_ALM1_MN - first] = bin2bcd(tm->tm_min);
 348 +       regs[PCF85263_REG_ALM1_HR - first] = pcf85263->mode_12h ?
 349 +                       pcf85263_bin24h_to_bcd12h(tm->tm_hour) :
 350 +                       bin2bcd(tm->tm_hour);
 351 +       regs[PCF85263_REG_ALM1_DT - first] = bin2bcd(tm->tm_mday);
 352 +       regs[PCF85263_REG_ALM1_MO - first] = bin2bcd(tm->tm_mon + 1);
 353 +
 354 +       ret = regmap_bulk_write(pcf85263->regmap, first, regs, sizeof(regs));
 355 +       if (ret)
 356 +               return ret;
 357 +
 358 +       if (alarm->enabled)
 359 +               ret = pcf85263_enable_alarm(pcf85263, true);
 360 +
 361 +       return ret;
 362 +}
 363 +
 364 +static int pcf85263_alarm_irq_enable(struct device *dev, unsigned int enable)
 365 +{
 366 +       struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
 367 +
 368 +       return pcf85263_enable_alarm(pcf85263, !!enable);
 369 +}
 370 +
 371 +static irqreturn_t pcf85263_irq(int irq, void *data)
 372 +{
 373 +       struct pcf85263 *pcf85263 = data;
 374 +       unsigned int regval;
 375 +       int ret;
 376 +
 377 +       ret = regmap_read(pcf85263->regmap, PCF85263_REG_FLAGS, &regval);
 378 +       if (ret)
 379 +               return IRQ_NONE;
 380 +
 381 +       if (regval & PCF85263_REG_FLAGS_A1F) {
 382 +               regmap_write(pcf85263->regmap, PCF85263_REG_FLAGS,
 383 +                            (unsigned int)(~PCF85263_REG_FLAGS_A1F));
 384 +
 385 +               rtc_update_irq(pcf85263->rtc, 1, RTC_IRQF | RTC_AF);
 386 +
 387 +               return IRQ_HANDLED;
 388 +       }
 389 +
 390 +       return IRQ_NONE;
 391 +}
 392 +
 393 +static int pcf85263_check_osc_stopped(struct pcf85263 *pcf85263)
 394 +{
 395 +       unsigned int regval;
 396 +       int ret;
 397 +
 398 +       ret = regmap_read(pcf85263->regmap, PCF85263_REG_RTC_SC, &regval);
 399 +       if (ret)
 400 +               return ret;
 401 +
 402 +       ret = regval & PCF85263_REG_RTC_SC_OS ? 1 : 0;
 403 +       if (ret)
 404 +               dev_warn(pcf85263->dev, "Oscillator stop detected, date/time is not reliable.\n");
 405 +
 406 +       return ret;
 407 +}
 408 +
 409 +#ifdef CONFIG_RTC_INTF_DEV
 410 +static int pcf85263_ioctl(struct device *dev,
 411 +                         unsigned int cmd, unsigned long arg)
 412 +{
 413 +       struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
 414 +       int ret;
 415 +
 416 +       switch (cmd) {
 417 +       case RTC_VL_READ:
 418 +               ret = pcf85263_check_osc_stopped(pcf85263);
 419 +               if (ret < 0)
 420 +                       return ret;
 421 +
 422 +               if (copy_to_user((void __user *)arg, &ret, sizeof(int)))
 423 +                       return -EFAULT;
 424 +               return 0;
 425 +
 426 +       case RTC_VL_CLR:
 427 +               return regmap_update_bits(pcf85263->regmap,
 428 +                                         PCF85263_REG_RTC_SC,
 429 +                                         PCF85263_REG_RTC_SC_OS, 0);
 430 +       default:
 431 +               return -ENOIOCTLCMD;
 432 +       }
 433 +}
 434 +#else
 435 +#define pcf85263_ioctl NULL
 436 +#endif
 437 +
 438 +static int pcf85263_init_hw(struct pcf85263 *pcf85263)
 439 +{
 440 +       struct device_node *np = pcf85263->dev->of_node;
 441 +       unsigned int regval;
 442 +       u32 propval;
 443 +       int ret;
 444 +
 445 +       /* Determine if oscilator has been stopped (probably low power) */
 446 +       ret = pcf85263_check_osc_stopped(pcf85263);
 447 +       if (ret < 0) {
 448 +               /* Log here since this is the first hw access on probe */
 449 +               dev_err(pcf85263->dev, "Unable to read register\n");
 450 +
 451 +               return ret;
 452 +       }
 453 +
 454 +       /* Determine 12/24H mode */
 455 +       ret = regmap_read(pcf85263->regmap, PCF85263_REG_OSC, &regval);
 456 +       if (ret)
 457 +               return ret;
 458 +       pcf85263->mode_12h = !!(regval & PCF85263_REG_OSC_12H);
 459 +
 460 +       /* Set oscilator register */
 461 +       regval &= ~PCF85263_REG_OSC_12H; /* keep current 12/24 h setting */
 462 +
 463 +       propval = PCF85263_QUARTZCAP_12p5pF;
 464 +       of_property_read_u32(np, "quartz-load-capacitance", &propval);
 465 +       regval |= ((propval << PCF85263_REG_OSC_CL_SHIFT)
 466 +                   & PCF85263_REG_OSC_CL_MASK);
 467 +
 468 +       propval = PCF85263_QUARTZDRIVE_NORMAL;
 469 +       of_property_read_u32(np, "quartz-drive-strength", &propval);
 470 +       regval |= ((propval << PCF85263_REG_OSC_OSCD_SHIFT)
 471 +                   & PCF85263_REG_OSC_OSCD_MASK);
 472 +
 473 +       if (of_property_read_bool(np, "quartz-low-jitter"))
 474 +               regval |= PCF85263_REG_OSC_LOWJ;
 475 +
 476 +       ret = regmap_write(pcf85263->regmap, PCF85263_REG_OSC, regval);
 477 +       if (ret)
 478 +               return ret;
 479 +
 480 +       /* Set function register (RTC mode, 1s tick, clock output static) */
 481 +       ret = regmap_write(pcf85263->regmap, PCF85263_REG_FUNCTION,
 482 +                          PCF85263_REG_FUNCTION_COF_OFF);
 483 +       if (ret)
 484 +               return ret;
 485 +
 486 +       /* Set all interrupts to disabled, level mode */
 487 +       ret = regmap_write(pcf85263->regmap, PCF85263_REG_INTA_CTL,
 488 +                          PCF85263_REG_INTx_CTL_ILP);
 489 +       if (ret)
 490 +               return ret;
 491 +       ret = regmap_write(pcf85263->regmap, PCF85263_REG_INTB_CTL,
 492 +                          PCF85263_REG_INTx_CTL_ILP);
 493 +       if (ret)
 494 +               return ret;
 495 +
 496 +       /* Setup IO pin config register */
 497 +       regval = PCF85263_REG_PINIO_CLKDISABLE;
 498 +       switch (pcf85263->irq_pin) {
 499 +       case PCF85263_IRQPIN_INTA:
 500 +               regval |= (PCF85263_INTAPM_INTA | PCF85263_TSPM_DISABLED);
 501 +               break;
 502 +       case PCF85263_IRQPIN_INTB:
 503 +               regval |= (PCF85263_INTAPM_HIGHZ | PCF85263_TSPM_INTB);
 504 +               break;
 505 +       case PCF85263_IRQPIN_NONE:
 506 +               regval |= (PCF85263_INTAPM_HIGHZ | PCF85263_TSPM_DISABLED);
 507 +               break;
 508 +       }
 509 +       ret = regmap_write(pcf85263->regmap, PCF85263_REG_PINIO, regval);
 510 +
 511 +       return ret;
 512 +}
 513 +
 514 +static const struct rtc_class_ops rtc_ops = {
 515 +       .ioctl = pcf85263_ioctl,
 516 +       .read_time = pcf85263_read_time,
 517 +       .set_time = pcf85263_set_time,
 518 +       .read_alarm = pcf85263_read_alarm,
 519 +       .set_alarm = pcf85263_set_alarm,
 520 +       .alarm_irq_enable = pcf85263_alarm_irq_enable,
 521 +};
 522 +
 523 +static const struct regmap_config pcf85263_regmap_cfg = {
 524 +       .reg_bits = 8,
 525 +       .val_bits = 8,
 526 +       .max_register = PCF85263_MAX_REG,
 527 +};
 528 +
 529 +/*
 530 + * On some boards the interrupt line may not be wired to the CPU but only to
 531 + * a power supply circuit.
 532 + * In that case no interrupt will be specified in the device tree but the
 533 + * wakeup-source DT property may be used to enable wakeup programming in
 534 + * sysfs
 535 + */
 536 +static bool pcf85263_can_wakeup_machine(struct pcf85263 *pcf85263)
 537 +{
 538 +       return pcf85263->irq ||
 539 +               of_property_read_bool(pcf85263->dev->of_node, "wakeup-source");
 540 +}
 541 +
 542 +static int pcf85263_probe(struct i2c_client *client,
 543 +                               const struct i2c_device_id *id)
 544 +{
 545 +       struct device *dev = &client->dev;
 546 +       struct pcf85263 *pcf85263;
 547 +       int ret;
 548 +
 549 +       if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
 550 +                                    I2C_FUNC_SMBUS_BYTE_DATA |
 551 +                                    I2C_FUNC_SMBUS_I2C_BLOCK))
 552 +               return -ENODEV;
 553 +
 554 +       pcf85263 = devm_kzalloc(dev, sizeof(*pcf85263), GFP_KERNEL);
 555 +       if (!pcf85263)
 556 +               return -ENOMEM;
 557 +
 558 +       pcf85263->dev = dev;
 559 +       pcf85263->irq = client->irq;
 560 +       dev_set_drvdata(dev, pcf85263);
 561 +
 562 +       pcf85263->regmap = devm_regmap_init_i2c(client, &pcf85263_regmap_cfg);
 563 +       if (IS_ERR(pcf85263->regmap)) {
 564 +               ret = PTR_ERR(pcf85263->regmap);
 565 +               dev_err(dev, "regmap allocation failed (%d)\n", ret);
 566 +
 567 +               return ret;
 568 +       }
 569 +
 570 +       /* Determine which interrupt pin the board uses */
 571 +       if (pcf85263_can_wakeup_machine(pcf85263)) {
 572 +               if (of_property_match_string(dev->of_node,
 573 +                                            "interrupt-names", "INTB") >= 0)
 574 +                       pcf85263->irq_pin = PCF85263_IRQPIN_INTB;
 575 +               else
 576 +                       pcf85263->irq_pin = PCF85263_IRQPIN_INTA;
 577 +       } else {
 578 +               pcf85263->irq_pin = PCF85263_IRQPIN_NONE;
 579 +       }
 580 +
 581 +       ret = pcf85263_init_hw(pcf85263);
 582 +       if (ret)
 583 +               return ret;
 584 +
 585 +       if (pcf85263->irq) {
 586 +               ret = devm_request_threaded_irq(dev, pcf85263->irq, NULL,
 587 +                                               pcf85263_irq,
 588 +                                               IRQF_ONESHOT,
 589 +                                               dev->driver->name, pcf85263);
 590 +               if (ret) {
 591 +                       dev_err(dev, "irq %d unavailable (%d)\n",
 592 +                               pcf85263->irq, ret);
 593 +                       pcf85263->irq = 0;
 594 +               }
 595 +       }
 596 +
 597 +       if (pcf85263_can_wakeup_machine(pcf85263))
 598 +               device_init_wakeup(dev, true);
 599 +
 600 +       pcf85263->rtc = devm_rtc_device_register(dev, dev->driver->name,
 601 +                                                &rtc_ops, THIS_MODULE);
 602 +       ret = PTR_ERR_OR_ZERO(pcf85263->rtc);
 603 +       if (ret)
 604 +               return ret;
 605 +
 606 +       /* We cannot support UIE mode if we do not have an IRQ line */
 607 +       if (!pcf85263->irq)
 608 +               pcf85263->rtc->uie_unsupported = 1;
 609 +
 610 +       dev_info(pcf85263->dev,
 611 +                "PCF85263 RTC (irqpin=%s irq=%d)\n",
 612 +                pcf85263_irqpin_names[pcf85263->irq_pin],
 613 +                pcf85263->irq);
 614 +
 615 +       return 0;
 616 +}
 617 +
 618 +static int pcf85263_remove(struct i2c_client *client)
 619 +{
 620 +       struct pcf85263 *pcf85263 = i2c_get_clientdata(client);
 621 +
 622 +       if (pcf85263_can_wakeup_machine(pcf85263))
 623 +               device_init_wakeup(pcf85263->dev, false);
 624 +
 625 +       return 0;
 626 +}
 627 +
 628 +#ifdef CONFIG_PM_SLEEP
 629 +static int pcf85263_suspend(struct device *dev)
 630 +{
 631 +       struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
 632 +       int ret = 0;
 633 +
 634 +       if (device_may_wakeup(dev))
 635 +               ret = enable_irq_wake(pcf85263->irq);
 636 +
 637 +       return ret;
 638 +}
 639 +
 640 +static int pcf85263_resume(struct device *dev)
 641 +{
 642 +       struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
 643 +       int ret = 0;
 644 +
 645 +       if (device_may_wakeup(dev))
 646 +               ret = disable_irq_wake(pcf85263->irq);
 647 +
 648 +       return ret;
 649 +}
 650 +
 651 +#endif
 652 +
 653 +static const struct i2c_device_id pcf85263_id[] = {
 654 +       { "pcf85263", 0 },
 655 +       { }
 656 +};
 657 +MODULE_DEVICE_TABLE(i2c, pcf85263_id);
 658 +
 659 +#ifdef CONFIG_OF
 660 +static const struct of_device_id pcf85263_of_match[] = {
 661 +       { .compatible = "nxp,pcf85263" },
 662 +       {}
 663 +};
 664 +MODULE_DEVICE_TABLE(of, pcf85263_of_match);
 665 +#endif
 666 +
 667 +static SIMPLE_DEV_PM_OPS(pcf85263_pm_ops, pcf85263_suspend,  pcf85263_resume);
 668 +
 669 +static struct i2c_driver pcf85263_driver = {
 670 +       .driver         = {
 671 +               .name   = "rtc-pcf85263",
 672 +               .of_match_table = of_match_ptr(pcf85263_of_match),
 673 +               .pm = &pcf85263_pm_ops,
 674 +       },
 675 +       .probe          = pcf85263_probe,
 676 +       .remove         = pcf85263_remove,
 677 +       .id_table       = pcf85263_id,
 678 +};
 679 +
 680 +module_i2c_driver(pcf85263_driver);
 681 +
 682 +MODULE_AUTHOR("Martin Fuzzey <mfuzzey@parkeon.com>");
 683 +MODULE_DESCRIPTION("PCF85263 RTC Driver");
 684 +MODULE_LICENSE("GPL");
 685 +
 686 --
 687 2.14.1
 688