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[openwrt/staging/hauke.git] / target / linux / layerscape / patches-4.9 / 813-qe-support-layerscape.patch
1 From adb377019768396f339010ebb9e80fa8384992f7 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 12:20:30 +0800
4 Subject: [PATCH] qe: support layerscape
5
6 This is a integrated patch for layerscape qe support.
7
8 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
9 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
10 ---
11 drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 389 +++++++++++++--------
12 drivers/net/wan/fsl_ucc_hdlc.c | 4 +-
13 drivers/soc/fsl/qe/Kconfig | 2 +-
14 drivers/soc/fsl/qe/Makefile | 2 +-
15 drivers/soc/fsl/qe/qe.c | 80 +++--
16 drivers/soc/fsl/qe/qe_ic.h | 103 ------
17 drivers/soc/fsl/qe/qe_io.c | 42 +--
18 drivers/soc/fsl/qe/qe_tdm.c | 8 +-
19 drivers/soc/fsl/qe/ucc.c | 10 +-
20 drivers/soc/fsl/qe/ucc_fast.c | 74 ++--
21 drivers/tty/serial/ucc_uart.c | 1 +
22 include/soc/fsl/qe/qe.h | 1 -
23 include/soc/fsl/qe/qe_ic.h | 139 --------
24 13 files changed, 359 insertions(+), 496 deletions(-)
25 rename drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (54%)
26 delete mode 100644 drivers/soc/fsl/qe/qe_ic.h
27 delete mode 100644 include/soc/fsl/qe/qe_ic.h
28
29 diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/irqchip/irq-qeic.c
30 similarity index 54%
31 rename from drivers/soc/fsl/qe/qe_ic.c
32 rename to drivers/irqchip/irq-qeic.c
33 index ec2ca864..21e3b43c 100644
34 --- a/drivers/soc/fsl/qe/qe_ic.c
35 +++ b/drivers/irqchip/irq-qeic.c
36 @@ -1,7 +1,7 @@
37 /*
38 - * arch/powerpc/sysdev/qe_lib/qe_ic.c
39 + * drivers/irqchip/irq-qeic.c
40 *
41 - * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
42 + * Copyright (C) 2016 Freescale Semiconductor, Inc. All rights reserved.
43 *
44 * Author: Li Yang <leoli@freescale.com>
45 * Based on code from Shlomi Gridish <gridish@freescale.com>
46 @@ -18,7 +18,11 @@
47 #include <linux/of_address.h>
48 #include <linux/kernel.h>
49 #include <linux/init.h>
50 +#include <linux/irqdomain.h>
51 +#include <linux/irqchip.h>
52 #include <linux/errno.h>
53 +#include <linux/of_address.h>
54 +#include <linux/of_irq.h>
55 #include <linux/reboot.h>
56 #include <linux/slab.h>
57 #include <linux/stddef.h>
58 @@ -26,11 +30,136 @@
59 #include <linux/signal.h>
60 #include <linux/device.h>
61 #include <linux/spinlock.h>
62 -#include <asm/irq.h>
63 +#include <linux/irq.h>
64 #include <asm/io.h>
65 -#include <soc/fsl/qe/qe_ic.h>
66
67 -#include "qe_ic.h"
68 +#define NR_QE_IC_INTS 64
69 +
70 +/* QE IC registers offset */
71 +#define QEIC_CICR 0x00
72 +#define QEIC_CIVEC 0x04
73 +#define QEIC_CRIPNR 0x08
74 +#define QEIC_CIPNR 0x0c
75 +#define QEIC_CIPXCC 0x10
76 +#define QEIC_CIPYCC 0x14
77 +#define QEIC_CIPWCC 0x18
78 +#define QEIC_CIPZCC 0x1c
79 +#define QEIC_CIMR 0x20
80 +#define QEIC_CRIMR 0x24
81 +#define QEIC_CICNR 0x28
82 +#define QEIC_CIPRTA 0x30
83 +#define QEIC_CIPRTB 0x34
84 +#define QEIC_CRICR 0x3c
85 +#define QEIC_CHIVEC 0x60
86 +
87 +/* Interrupt priority registers */
88 +#define CIPCC_SHIFT_PRI0 29
89 +#define CIPCC_SHIFT_PRI1 26
90 +#define CIPCC_SHIFT_PRI2 23
91 +#define CIPCC_SHIFT_PRI3 20
92 +#define CIPCC_SHIFT_PRI4 13
93 +#define CIPCC_SHIFT_PRI5 10
94 +#define CIPCC_SHIFT_PRI6 7
95 +#define CIPCC_SHIFT_PRI7 4
96 +
97 +/* CICR priority modes */
98 +#define CICR_GWCC 0x00040000
99 +#define CICR_GXCC 0x00020000
100 +#define CICR_GYCC 0x00010000
101 +#define CICR_GZCC 0x00080000
102 +#define CICR_GRTA 0x00200000
103 +#define CICR_GRTB 0x00400000
104 +#define CICR_HPIT_SHIFT 8
105 +#define CICR_HPIT_MASK 0x00000300
106 +#define CICR_HP_SHIFT 24
107 +#define CICR_HP_MASK 0x3f000000
108 +
109 +/* CICNR */
110 +#define CICNR_WCC1T_SHIFT 20
111 +#define CICNR_ZCC1T_SHIFT 28
112 +#define CICNR_YCC1T_SHIFT 12
113 +#define CICNR_XCC1T_SHIFT 4
114 +
115 +/* CRICR */
116 +#define CRICR_RTA1T_SHIFT 20
117 +#define CRICR_RTB1T_SHIFT 28
118 +
119 +/* Signal indicator */
120 +#define SIGNAL_MASK 3
121 +#define SIGNAL_HIGH 2
122 +#define SIGNAL_LOW 0
123 +
124 +#define NUM_OF_QE_IC_GROUPS 6
125 +
126 +/* Flags when we init the QE IC */
127 +#define QE_IC_SPREADMODE_GRP_W 0x00000001
128 +#define QE_IC_SPREADMODE_GRP_X 0x00000002
129 +#define QE_IC_SPREADMODE_GRP_Y 0x00000004
130 +#define QE_IC_SPREADMODE_GRP_Z 0x00000008
131 +#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
132 +#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
133 +
134 +#define QE_IC_LOW_SIGNAL 0x00000100
135 +#define QE_IC_HIGH_SIGNAL 0x00000200
136 +
137 +#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
138 +#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
139 +#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
140 +#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
141 +#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
142 +#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
143 +#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
144 +#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
145 +#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
146 +#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
147 +#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
148 +#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
149 +#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
150 +
151 +/* QE interrupt sources groups */
152 +enum qe_ic_grp_id {
153 + QE_IC_GRP_W = 0, /* QE interrupt controller group W */
154 + QE_IC_GRP_X, /* QE interrupt controller group X */
155 + QE_IC_GRP_Y, /* QE interrupt controller group Y */
156 + QE_IC_GRP_Z, /* QE interrupt controller group Z */
157 + QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
158 + QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
159 +};
160 +
161 +struct qe_ic {
162 + /* Control registers offset */
163 + u32 __iomem *regs;
164 +
165 + /* The remapper for this QEIC */
166 + struct irq_domain *irqhost;
167 +
168 + /* The "linux" controller struct */
169 + struct irq_chip hc_irq;
170 +
171 + /* VIRQ numbers of QE high/low irqs */
172 + unsigned int virq_high;
173 + unsigned int virq_low;
174 +};
175 +
176 +/*
177 + * QE interrupt controller internal structure
178 + */
179 +struct qe_ic_info {
180 + /* location of this source at the QIMR register. */
181 + u32 mask;
182 +
183 + /* Mask register offset */
184 + u32 mask_reg;
185 +
186 + /*
187 + * for grouped interrupts sources - the interrupt
188 + * code as appears at the group priority register
189 + */
190 + u8 pri_code;
191 +
192 + /* Group priority register offset */
193 + u32 pri_reg;
194 +};
195
196 static DEFINE_RAW_SPINLOCK(qe_ic_lock);
197
198 @@ -175,15 +304,15 @@ static struct qe_ic_info qe_ic_info[] = {
199 },
200 };
201
202 -static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)
203 +static inline u32 qe_ic_read(__be32 __iomem *base, unsigned int reg)
204 {
205 - return in_be32(base + (reg >> 2));
206 + return ioread32be(base + (reg >> 2));
207 }
208
209 -static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg,
210 +static inline void qe_ic_write(__be32 __iomem *base, unsigned int reg,
211 u32 value)
212 {
213 - out_be32(base + (reg >> 2), value);
214 + iowrite32be(value, base + (reg >> 2));
215 }
216
217 static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
218 @@ -285,8 +414,8 @@ static const struct irq_domain_ops qe_ic_host_ops = {
219 .xlate = irq_domain_xlate_onetwocell,
220 };
221
222 -/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
223 -unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
224 +/* Return an interrupt vector or 0 if no interrupt is pending. */
225 +static unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
226 {
227 int irq;
228
229 @@ -296,13 +425,13 @@ unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
230 irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
231
232 if (irq == 0)
233 - return NO_IRQ;
234 + return 0;
235
236 return irq_linear_revmap(qe_ic->irqhost, irq);
237 }
238
239 -/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
240 -unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
241 +/* Return an interrupt vector or 0 if no interrupt is pending. */
242 +static unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
243 {
244 int irq;
245
246 @@ -312,32 +441,96 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
247 irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
248
249 if (irq == 0)
250 - return NO_IRQ;
251 + return 0;
252
253 return irq_linear_revmap(qe_ic->irqhost, irq);
254 }
255
256 -void __init qe_ic_init(struct device_node *node, unsigned int flags,
257 - void (*low_handler)(struct irq_desc *desc),
258 - void (*high_handler)(struct irq_desc *desc))
259 +static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
260 +{
261 + struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
262 + unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
263 +
264 + if (cascade_irq != 0)
265 + generic_handle_irq(cascade_irq);
266 +}
267 +
268 +static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
269 +{
270 + struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
271 + unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
272 +
273 + if (cascade_irq != 0)
274 + generic_handle_irq(cascade_irq);
275 +}
276 +
277 +static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
278 +{
279 + struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
280 + unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
281 + struct irq_chip *chip = irq_desc_get_chip(desc);
282 +
283 + if (cascade_irq != 0)
284 + generic_handle_irq(cascade_irq);
285 +
286 + chip->irq_eoi(&desc->irq_data);
287 +}
288 +
289 +static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
290 +{
291 + struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
292 + unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
293 + struct irq_chip *chip = irq_desc_get_chip(desc);
294 +
295 + if (cascade_irq != 0)
296 + generic_handle_irq(cascade_irq);
297 +
298 + chip->irq_eoi(&desc->irq_data);
299 +}
300 +
301 +static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
302 +{
303 + struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
304 + unsigned int cascade_irq;
305 + struct irq_chip *chip = irq_desc_get_chip(desc);
306 +
307 + cascade_irq = qe_ic_get_high_irq(qe_ic);
308 + if (cascade_irq == 0)
309 + cascade_irq = qe_ic_get_low_irq(qe_ic);
310 +
311 + if (cascade_irq != 0)
312 + generic_handle_irq(cascade_irq);
313 +
314 + chip->irq_eoi(&desc->irq_data);
315 +}
316 +
317 +static int __init qe_ic_init(struct device_node *node, unsigned int flags)
318 {
319 struct qe_ic *qe_ic;
320 struct resource res;
321 - u32 temp = 0, ret, high_active = 0;
322 + u32 temp = 0, high_active = 0;
323 + int ret = 0;
324 +
325 + if (!node)
326 + return -ENODEV;
327
328 ret = of_address_to_resource(node, 0, &res);
329 - if (ret)
330 - return;
331 + if (ret) {
332 + ret = -ENODEV;
333 + goto err_put_node;
334 + }
335
336 qe_ic = kzalloc(sizeof(*qe_ic), GFP_KERNEL);
337 - if (qe_ic == NULL)
338 - return;
339 + if (qe_ic == NULL) {
340 + ret = -ENOMEM;
341 + goto err_put_node;
342 + }
343
344 qe_ic->irqhost = irq_domain_add_linear(node, NR_QE_IC_INTS,
345 &qe_ic_host_ops, qe_ic);
346 if (qe_ic->irqhost == NULL) {
347 - kfree(qe_ic);
348 - return;
349 + ret = -ENOMEM;
350 + goto err_free_qe_ic;
351 }
352
353 qe_ic->regs = ioremap(res.start, resource_size(&res));
354 @@ -347,10 +540,10 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
355 qe_ic->virq_high = irq_of_parse_and_map(node, 0);
356 qe_ic->virq_low = irq_of_parse_and_map(node, 1);
357
358 - if (qe_ic->virq_low == NO_IRQ) {
359 - printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
360 - kfree(qe_ic);
361 - return;
362 + if (qe_ic->virq_low == 0) {
363 + pr_err("Failed to map QE_IC low IRQ\n");
364 + ret = -ENOMEM;
365 + goto err_domain_remove;
366 }
367
368 /* default priority scheme is grouped. If spread mode is */
369 @@ -377,136 +570,36 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
370 qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
371
372 irq_set_handler_data(qe_ic->virq_low, qe_ic);
373 - irq_set_chained_handler(qe_ic->virq_low, low_handler);
374 + irq_set_chained_handler(qe_ic->virq_low, qe_ic_cascade_low_mpic);
375
376 - if (qe_ic->virq_high != NO_IRQ &&
377 + if (qe_ic->virq_high != 0 &&
378 qe_ic->virq_high != qe_ic->virq_low) {
379 irq_set_handler_data(qe_ic->virq_high, qe_ic);
380 - irq_set_chained_handler(qe_ic->virq_high, high_handler);
381 - }
382 -}
383 -
384 -void qe_ic_set_highest_priority(unsigned int virq, int high)
385 -{
386 - struct qe_ic *qe_ic = qe_ic_from_irq(virq);
387 - unsigned int src = virq_to_hw(virq);
388 - u32 temp = 0;
389 -
390 - temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
391 -
392 - temp &= ~CICR_HP_MASK;
393 - temp |= src << CICR_HP_SHIFT;
394 -
395 - temp &= ~CICR_HPIT_MASK;
396 - temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
397 -
398 - qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
399 -}
400 -
401 -/* Set Priority level within its group, from 1 to 8 */
402 -int qe_ic_set_priority(unsigned int virq, unsigned int priority)
403 -{
404 - struct qe_ic *qe_ic = qe_ic_from_irq(virq);
405 - unsigned int src = virq_to_hw(virq);
406 - u32 temp;
407 -
408 - if (priority > 8 || priority == 0)
409 - return -EINVAL;
410 - if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
411 - "%s: Invalid hw irq number for QEIC\n", __func__))
412 - return -EINVAL;
413 - if (qe_ic_info[src].pri_reg == 0)
414 - return -EINVAL;
415 -
416 - temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
417 -
418 - if (priority < 4) {
419 - temp &= ~(0x7 << (32 - priority * 3));
420 - temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
421 - } else {
422 - temp &= ~(0x7 << (24 - priority * 3));
423 - temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
424 + irq_set_chained_handler(qe_ic->virq_high,
425 + qe_ic_cascade_high_mpic);
426 }
427 -
428 - qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
429 -
430 + of_node_put(node);
431 return 0;
432 -}
433 -
434 -/* Set a QE priority to use high irq, only priority 1~2 can use high irq */
435 -int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
436 -{
437 - struct qe_ic *qe_ic = qe_ic_from_irq(virq);
438 - unsigned int src = virq_to_hw(virq);
439 - u32 temp, control_reg = QEIC_CICNR, shift = 0;
440 -
441 - if (priority > 2 || priority == 0)
442 - return -EINVAL;
443 - if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
444 - "%s: Invalid hw irq number for QEIC\n", __func__))
445 - return -EINVAL;
446 -
447 - switch (qe_ic_info[src].pri_reg) {
448 - case QEIC_CIPZCC:
449 - shift = CICNR_ZCC1T_SHIFT;
450 - break;
451 - case QEIC_CIPWCC:
452 - shift = CICNR_WCC1T_SHIFT;
453 - break;
454 - case QEIC_CIPYCC:
455 - shift = CICNR_YCC1T_SHIFT;
456 - break;
457 - case QEIC_CIPXCC:
458 - shift = CICNR_XCC1T_SHIFT;
459 - break;
460 - case QEIC_CIPRTA:
461 - shift = CRICR_RTA1T_SHIFT;
462 - control_reg = QEIC_CRICR;
463 - break;
464 - case QEIC_CIPRTB:
465 - shift = CRICR_RTB1T_SHIFT;
466 - control_reg = QEIC_CRICR;
467 - break;
468 - default:
469 - return -EINVAL;
470 - }
471 -
472 - shift += (2 - priority) * 2;
473 - temp = qe_ic_read(qe_ic->regs, control_reg);
474 - temp &= ~(SIGNAL_MASK << shift);
475 - temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
476 - qe_ic_write(qe_ic->regs, control_reg, temp);
477
478 - return 0;
479 +err_domain_remove:
480 + irq_domain_remove(qe_ic->irqhost);
481 +err_free_qe_ic:
482 + kfree(qe_ic);
483 +err_put_node:
484 + of_node_put(node);
485 + return ret;
486 }
487
488 -static struct bus_type qe_ic_subsys = {
489 - .name = "qe_ic",
490 - .dev_name = "qe_ic",
491 -};
492 -
493 -static struct device device_qe_ic = {
494 - .id = 0,
495 - .bus = &qe_ic_subsys,
496 -};
497 -
498 -static int __init init_qe_ic_sysfs(void)
499 +static int __init init_qe_ic(struct device_node *node,
500 + struct device_node *parent)
501 {
502 - int rc;
503 + int ret;
504
505 - printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
506 + ret = qe_ic_init(node, 0);
507 + if (ret)
508 + return ret;
509
510 - rc = subsys_system_register(&qe_ic_subsys, NULL);
511 - if (rc) {
512 - printk(KERN_ERR "Failed registering qe_ic sys class\n");
513 - return -ENODEV;
514 - }
515 - rc = device_register(&device_qe_ic);
516 - if (rc) {
517 - printk(KERN_ERR "Failed registering qe_ic sys device\n");
518 - return -ENODEV;
519 - }
520 return 0;
521 }
522
523 -subsys_initcall(init_qe_ic_sysfs);
524 +IRQCHIP_DECLARE(qeic, "fsl,qe-ic", init_qe_ic);
525 diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c
526 index 65647533..27e11404 100644
527 --- a/drivers/net/wan/fsl_ucc_hdlc.c
528 +++ b/drivers/net/wan/fsl_ucc_hdlc.c
529 @@ -381,8 +381,8 @@ static netdev_tx_t ucc_hdlc_tx(struct sk_buff *skb, struct net_device *dev)
530 /* set bd status and length */
531 bd_status = (bd_status & T_W_S) | T_R_S | T_I_S | T_L_S | T_TC_S;
532
533 - iowrite16be(bd_status, &bd->status);
534 iowrite16be(skb->len, &bd->length);
535 + iowrite16be(bd_status, &bd->status);
536
537 /* Move to next BD in the ring */
538 if (!(bd_status & T_W_S))
539 @@ -457,7 +457,7 @@ static int hdlc_rx_done(struct ucc_hdlc_private *priv, int rx_work_limit)
540 struct sk_buff *skb;
541 hdlc_device *hdlc = dev_to_hdlc(dev);
542 struct qe_bd *bd;
543 - u32 bd_status;
544 + u16 bd_status;
545 u16 length, howmany = 0;
546 u8 *bdbuffer;
547 int i;
548 diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig
549 index 73a2e08b..b26b6431 100644
550 --- a/drivers/soc/fsl/qe/Kconfig
551 +++ b/drivers/soc/fsl/qe/Kconfig
552 @@ -4,7 +4,7 @@
553
554 config QUICC_ENGINE
555 bool "Freescale QUICC Engine (QE) Support"
556 - depends on FSL_SOC && PPC32
557 + depends on OF && HAS_IOMEM
558 select GENERIC_ALLOCATOR
559 select CRC32
560 help
561 diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile
562 index 2031d385..51e47264 100644
563 --- a/drivers/soc/fsl/qe/Makefile
564 +++ b/drivers/soc/fsl/qe/Makefile
565 @@ -1,7 +1,7 @@
566 #
567 # Makefile for the linux ppc-specific parts of QE
568 #
569 -obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o
570 +obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_io.o
571 obj-$(CONFIG_CPM) += qe_common.o
572 obj-$(CONFIG_UCC) += ucc.o
573 obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
574 diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
575 index 2707a827..2b53e852 100644
576 --- a/drivers/soc/fsl/qe/qe.c
577 +++ b/drivers/soc/fsl/qe/qe.c
578 @@ -33,8 +33,6 @@
579 #include <asm/pgtable.h>
580 #include <soc/fsl/qe/immap_qe.h>
581 #include <soc/fsl/qe/qe.h>
582 -#include <asm/prom.h>
583 -#include <asm/rheap.h>
584
585 static void qe_snums_init(void);
586 static int qe_sdma_init(void);
587 @@ -109,15 +107,27 @@ void qe_reset(void)
588 panic("sdma init failed!");
589 }
590
591 +/* issue commands to QE, return 0 on success while -EIO on error
592 + *
593 + * @cmd: the command code, should be QE_INIT_TX_RX, QE_STOP_TX and so on
594 + * @device: which sub-block will run the command, QE_CR_SUBBLOCK_UCCFAST1 - 8
595 + * , QE_CR_SUBBLOCK_UCCSLOW1 - 8, QE_CR_SUBBLOCK_MCC1 - 3,
596 + * QE_CR_SUBBLOCK_IDMA1 - 4 and such on.
597 + * @mcn_protocol: specifies mode for the command for non-MCC, should be
598 + * QE_CR_PROTOCOL_HDLC_TRANSPARENT, QE_CR_PROTOCOL_QMC, QE_CR_PROTOCOL_UART
599 + * and such on.
600 + * @cmd_input: command related data.
601 + */
602 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
603 {
604 unsigned long flags;
605 u8 mcn_shift = 0, dev_shift = 0;
606 - u32 ret;
607 + int ret;
608 + int i;
609
610 spin_lock_irqsave(&qe_lock, flags);
611 if (cmd == QE_RESET) {
612 - out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
613 + iowrite32be((cmd | QE_CR_FLG), &qe_immr->cp.cecr);
614 } else {
615 if (cmd == QE_ASSIGN_PAGE) {
616 /* Here device is the SNUM, not sub-block */
617 @@ -134,20 +144,26 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
618 mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
619 }
620
621 - out_be32(&qe_immr->cp.cecdr, cmd_input);
622 - out_be32(&qe_immr->cp.cecr,
623 - (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
624 - mcn_protocol << mcn_shift));
625 + iowrite32be(cmd_input, &qe_immr->cp.cecdr);
626 + iowrite32be((cmd | QE_CR_FLG | ((u32)device << dev_shift) |
627 + (u32)mcn_protocol << mcn_shift), &qe_immr->cp.cecr);
628 }
629
630 /* wait for the QE_CR_FLG to clear */
631 - ret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
632 - 100, 0);
633 + ret = -EIO;
634 + for (i = 0; i < 100; i++) {
635 + if ((ioread32be(&qe_immr->cp.cecr) & QE_CR_FLG) == 0) {
636 + ret = 0;
637 + break;
638 + }
639 + udelay(1);
640 + }
641 +
642 /* On timeout (e.g. failure), the expression will be false (ret == 0),
643 otherwise it will be true (ret == 1). */
644 spin_unlock_irqrestore(&qe_lock, flags);
645
646 - return ret == 1;
647 + return ret;
648 }
649 EXPORT_SYMBOL(qe_issue_cmd);
650
651 @@ -166,8 +182,8 @@ static unsigned int brg_clk = 0;
652 unsigned int qe_get_brg_clk(void)
653 {
654 struct device_node *qe;
655 - int size;
656 - const u32 *prop;
657 + u32 val;
658 + int ret;
659
660 if (brg_clk)
661 return brg_clk;
662 @@ -179,9 +195,9 @@ unsigned int qe_get_brg_clk(void)
663 return brg_clk;
664 }
665
666 - prop = of_get_property(qe, "brg-frequency", &size);
667 - if (prop && size == sizeof(*prop))
668 - brg_clk = *prop;
669 + ret = of_property_read_u32(qe, "brg-frequency", &val);
670 + if (!ret)
671 + brg_clk = val;
672
673 of_node_put(qe);
674
675 @@ -221,7 +237,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
676 tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
677 QE_BRGC_ENABLE | div16;
678
679 - out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);
680 + iowrite32be(tempval, &qe_immr->brg.brgc[brg - QE_BRG1]);
681
682 return 0;
683 }
684 @@ -355,9 +371,9 @@ static int qe_sdma_init(void)
685 return -ENOMEM;
686 }
687
688 - out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
689 - out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
690 - (0x1 << QE_SDMR_CEN_SHIFT)));
691 + iowrite32be((u32)sdma_buf_offset & QE_SDEBCR_BA_MASK, &sdma->sdebcr);
692 + iowrite32be((QE_SDMR_GLB_1_MSK | (0x1 << QE_SDMR_CEN_SHIFT)),
693 + &sdma->sdmr);
694
695 return 0;
696 }
697 @@ -395,14 +411,14 @@ static void qe_upload_microcode(const void *base,
698 "uploading microcode '%s'\n", ucode->id);
699
700 /* Use auto-increment */
701 - out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
702 - QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
703 + iowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE |
704 + QE_IRAM_IADD_BADDR, &qe_immr->iram.iadd);
705
706 for (i = 0; i < be32_to_cpu(ucode->count); i++)
707 - out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
708 + iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);
709
710 /* Set I-RAM Ready Register */
711 - out_be32(&qe_immr->iram.iready, be32_to_cpu(QE_IRAM_READY));
712 + iowrite32be(be32_to_cpu(QE_IRAM_READY), &qe_immr->iram.iready);
713 }
714
715 /*
716 @@ -487,7 +503,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
717 * If the microcode calls for it, split the I-RAM.
718 */
719 if (!firmware->split)
720 - setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
721 + qe_setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
722
723 if (firmware->soc.model)
724 printk(KERN_INFO
725 @@ -521,11 +537,11 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
726 u32 trap = be32_to_cpu(ucode->traps[j]);
727
728 if (trap)
729 - out_be32(&qe_immr->rsp[i].tibcr[j], trap);
730 + iowrite32be(trap, &qe_immr->rsp[i].tibcr[j]);
731 }
732
733 /* Enable traps */
734 - out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
735 + iowrite32be(be32_to_cpu(ucode->eccr), &qe_immr->rsp[i].eccr);
736 }
737
738 qe_firmware_uploaded = 1;
739 @@ -644,9 +660,9 @@ EXPORT_SYMBOL(qe_get_num_of_risc);
740 unsigned int qe_get_num_of_snums(void)
741 {
742 struct device_node *qe;
743 - int size;
744 unsigned int num_of_snums;
745 - const u32 *prop;
746 + u32 val;
747 + int ret;
748
749 num_of_snums = 28; /* The default number of snum for threads is 28 */
750 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
751 @@ -660,9 +676,9 @@ unsigned int qe_get_num_of_snums(void)
752 return num_of_snums;
753 }
754
755 - prop = of_get_property(qe, "fsl,qe-num-snums", &size);
756 - if (prop && size == sizeof(*prop)) {
757 - num_of_snums = *prop;
758 + ret = of_property_read_u32(qe, "fsl,qe-num-snums", &val);
759 + if (!ret) {
760 + num_of_snums = val;
761 if ((num_of_snums < 28) || (num_of_snums > QE_NUM_OF_SNUM)) {
762 /* No QE ever has fewer than 28 SNUMs */
763 pr_err("QE: number of snum is invalid\n");
764 diff --git a/drivers/soc/fsl/qe/qe_ic.h b/drivers/soc/fsl/qe/qe_ic.h
765 deleted file mode 100644
766 index 926a2ed4..00000000
767 --- a/drivers/soc/fsl/qe/qe_ic.h
768 +++ /dev/null
769 @@ -1,103 +0,0 @@
770 -/*
771 - * drivers/soc/fsl/qe/qe_ic.h
772 - *
773 - * QUICC ENGINE Interrupt Controller Header
774 - *
775 - * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
776 - *
777 - * Author: Li Yang <leoli@freescale.com>
778 - * Based on code from Shlomi Gridish <gridish@freescale.com>
779 - *
780 - * This program is free software; you can redistribute it and/or modify it
781 - * under the terms of the GNU General Public License as published by the
782 - * Free Software Foundation; either version 2 of the License, or (at your
783 - * option) any later version.
784 - */
785 -#ifndef _POWERPC_SYSDEV_QE_IC_H
786 -#define _POWERPC_SYSDEV_QE_IC_H
787 -
788 -#include <soc/fsl/qe/qe_ic.h>
789 -
790 -#define NR_QE_IC_INTS 64
791 -
792 -/* QE IC registers offset */
793 -#define QEIC_CICR 0x00
794 -#define QEIC_CIVEC 0x04
795 -#define QEIC_CRIPNR 0x08
796 -#define QEIC_CIPNR 0x0c
797 -#define QEIC_CIPXCC 0x10
798 -#define QEIC_CIPYCC 0x14
799 -#define QEIC_CIPWCC 0x18
800 -#define QEIC_CIPZCC 0x1c
801 -#define QEIC_CIMR 0x20
802 -#define QEIC_CRIMR 0x24
803 -#define QEIC_CICNR 0x28
804 -#define QEIC_CIPRTA 0x30
805 -#define QEIC_CIPRTB 0x34
806 -#define QEIC_CRICR 0x3c
807 -#define QEIC_CHIVEC 0x60
808 -
809 -/* Interrupt priority registers */
810 -#define CIPCC_SHIFT_PRI0 29
811 -#define CIPCC_SHIFT_PRI1 26
812 -#define CIPCC_SHIFT_PRI2 23
813 -#define CIPCC_SHIFT_PRI3 20
814 -#define CIPCC_SHIFT_PRI4 13
815 -#define CIPCC_SHIFT_PRI5 10
816 -#define CIPCC_SHIFT_PRI6 7
817 -#define CIPCC_SHIFT_PRI7 4
818 -
819 -/* CICR priority modes */
820 -#define CICR_GWCC 0x00040000
821 -#define CICR_GXCC 0x00020000
822 -#define CICR_GYCC 0x00010000
823 -#define CICR_GZCC 0x00080000
824 -#define CICR_GRTA 0x00200000
825 -#define CICR_GRTB 0x00400000
826 -#define CICR_HPIT_SHIFT 8
827 -#define CICR_HPIT_MASK 0x00000300
828 -#define CICR_HP_SHIFT 24
829 -#define CICR_HP_MASK 0x3f000000
830 -
831 -/* CICNR */
832 -#define CICNR_WCC1T_SHIFT 20
833 -#define CICNR_ZCC1T_SHIFT 28
834 -#define CICNR_YCC1T_SHIFT 12
835 -#define CICNR_XCC1T_SHIFT 4
836 -
837 -/* CRICR */
838 -#define CRICR_RTA1T_SHIFT 20
839 -#define CRICR_RTB1T_SHIFT 28
840 -
841 -/* Signal indicator */
842 -#define SIGNAL_MASK 3
843 -#define SIGNAL_HIGH 2
844 -#define SIGNAL_LOW 0
845 -
846 -struct qe_ic {
847 - /* Control registers offset */
848 - volatile u32 __iomem *regs;
849 -
850 - /* The remapper for this QEIC */
851 - struct irq_domain *irqhost;
852 -
853 - /* The "linux" controller struct */
854 - struct irq_chip hc_irq;
855 -
856 - /* VIRQ numbers of QE high/low irqs */
857 - unsigned int virq_high;
858 - unsigned int virq_low;
859 -};
860 -
861 -/*
862 - * QE interrupt controller internal structure
863 - */
864 -struct qe_ic_info {
865 - u32 mask; /* location of this source at the QIMR register. */
866 - u32 mask_reg; /* Mask register offset */
867 - u8 pri_code; /* for grouped interrupts sources - the interrupt
868 - code as appears at the group priority register */
869 - u32 pri_reg; /* Group priority register offset */
870 -};
871 -
872 -#endif /* _POWERPC_SYSDEV_QE_IC_H */
873 diff --git a/drivers/soc/fsl/qe/qe_io.c b/drivers/soc/fsl/qe/qe_io.c
874 index 7ae59abc..8966e8b6 100644
875 --- a/drivers/soc/fsl/qe/qe_io.c
876 +++ b/drivers/soc/fsl/qe/qe_io.c
877 @@ -22,8 +22,6 @@
878
879 #include <asm/io.h>
880 #include <soc/fsl/qe/qe.h>
881 -#include <asm/prom.h>
882 -#include <sysdev/fsl_soc.h>
883
884 #undef DEBUG
885
886 @@ -61,16 +59,16 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,
887 pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1)));
888
889 /* Set open drain, if required */
890 - tmp_val = in_be32(&par_io->cpodr);
891 + tmp_val = ioread32be(&par_io->cpodr);
892 if (open_drain)
893 - out_be32(&par_io->cpodr, pin_mask1bit | tmp_val);
894 + iowrite32be(pin_mask1bit | tmp_val, &par_io->cpodr);
895 else
896 - out_be32(&par_io->cpodr, ~pin_mask1bit & tmp_val);
897 + iowrite32be(~pin_mask1bit & tmp_val, &par_io->cpodr);
898
899 /* define direction */
900 tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
901 - in_be32(&par_io->cpdir2) :
902 - in_be32(&par_io->cpdir1);
903 + ioread32be(&par_io->cpdir2) :
904 + ioread32be(&par_io->cpdir1);
905
906 /* get all bits mask for 2 bit per port */
907 pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS -
908 @@ -82,34 +80,30 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,
909
910 /* clear and set 2 bits mask */
911 if (pin > (QE_PIO_PINS / 2) - 1) {
912 - out_be32(&par_io->cpdir2,
913 - ~pin_mask2bits & tmp_val);
914 + iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir2);
915 tmp_val &= ~pin_mask2bits;
916 - out_be32(&par_io->cpdir2, new_mask2bits | tmp_val);
917 + iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir2);
918 } else {
919 - out_be32(&par_io->cpdir1,
920 - ~pin_mask2bits & tmp_val);
921 + iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir1);
922 tmp_val &= ~pin_mask2bits;
923 - out_be32(&par_io->cpdir1, new_mask2bits | tmp_val);
924 + iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir1);
925 }
926 /* define pin assignment */
927 tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
928 - in_be32(&par_io->cppar2) :
929 - in_be32(&par_io->cppar1);
930 + ioread32be(&par_io->cppar2) :
931 + ioread32be(&par_io->cppar1);
932
933 new_mask2bits = (u32) (assignment << (QE_PIO_PINS -
934 (pin % (QE_PIO_PINS / 2) + 1) * 2));
935 /* clear and set 2 bits mask */
936 if (pin > (QE_PIO_PINS / 2) - 1) {
937 - out_be32(&par_io->cppar2,
938 - ~pin_mask2bits & tmp_val);
939 + iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar2);
940 tmp_val &= ~pin_mask2bits;
941 - out_be32(&par_io->cppar2, new_mask2bits | tmp_val);
942 + iowrite32be(new_mask2bits | tmp_val, &par_io->cppar2);
943 } else {
944 - out_be32(&par_io->cppar1,
945 - ~pin_mask2bits & tmp_val);
946 + iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar1);
947 tmp_val &= ~pin_mask2bits;
948 - out_be32(&par_io->cppar1, new_mask2bits | tmp_val);
949 + iowrite32be(new_mask2bits | tmp_val, &par_io->cppar1);
950 }
951 }
952 EXPORT_SYMBOL(__par_io_config_pin);
953 @@ -137,12 +131,12 @@ int par_io_data_set(u8 port, u8 pin, u8 val)
954 /* calculate pin location */
955 pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin));
956
957 - tmp_val = in_be32(&par_io[port].cpdata);
958 + tmp_val = ioread32be(&par_io[port].cpdata);
959
960 if (val == 0) /* clear */
961 - out_be32(&par_io[port].cpdata, ~pin_mask & tmp_val);
962 + iowrite32be(~pin_mask & tmp_val, &par_io[port].cpdata);
963 else /* set */
964 - out_be32(&par_io[port].cpdata, pin_mask | tmp_val);
965 + iowrite32be(pin_mask | tmp_val, &par_io[port].cpdata);
966
967 return 0;
968 }
969 diff --git a/drivers/soc/fsl/qe/qe_tdm.c b/drivers/soc/fsl/qe/qe_tdm.c
970 index a1048b44..818e6798 100644
971 --- a/drivers/soc/fsl/qe/qe_tdm.c
972 +++ b/drivers/soc/fsl/qe/qe_tdm.c
973 @@ -227,10 +227,10 @@ void ucc_tdm_init(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info)
974 &siram[siram_entry_id * 32 + 0x200 + i]);
975 }
976
977 - setbits16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],
978 - SIR_LAST);
979 - setbits16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)],
980 - SIR_LAST);
981 + qe_setbits16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],
982 + SIR_LAST);
983 + qe_setbits16(&siram[(siram_entry_id * 32) + 0x200 +
984 + (utdm->num_of_ts - 1)], SIR_LAST);
985
986 /* Set SIxMR register */
987 sixmr = SIMR_SAD(siram_entry_id);
988 diff --git a/drivers/soc/fsl/qe/ucc.c b/drivers/soc/fsl/qe/ucc.c
989 index c646d871..bc64b834 100644
990 --- a/drivers/soc/fsl/qe/ucc.c
991 +++ b/drivers/soc/fsl/qe/ucc.c
992 @@ -39,7 +39,7 @@ int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
993 return -EINVAL;
994
995 spin_lock_irqsave(&cmxgcr_lock, flags);
996 - clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
997 + qe_clrsetbits32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
998 ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
999 spin_unlock_irqrestore(&cmxgcr_lock, flags);
1000
1001 @@ -84,7 +84,7 @@ int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed)
1002 return -EINVAL;
1003 }
1004
1005 - clrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,
1006 + qe_clrsetbits8(guemr, UCC_GUEMR_MODE_MASK,
1007 UCC_GUEMR_SET_RESERVED3 | speed);
1008
1009 return 0;
1010 @@ -113,9 +113,9 @@ int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask)
1011 get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift);
1012
1013 if (set)
1014 - setbits32(cmxucr, mask << shift);
1015 + qe_setbits32(cmxucr, mask << shift);
1016 else
1017 - clrbits32(cmxucr, mask << shift);
1018 + qe_clrbits32(cmxucr, mask << shift);
1019
1020 return 0;
1021 }
1022 @@ -211,7 +211,7 @@ int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
1023 if (mode == COMM_DIR_RX)
1024 shift += 4;
1025
1026 - clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
1027 + qe_clrsetbits32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
1028 clock_bits << shift);
1029
1030 return 0;
1031 diff --git a/drivers/soc/fsl/qe/ucc_fast.c b/drivers/soc/fsl/qe/ucc_fast.c
1032 index 83d8d16e..5115e935 100644
1033 --- a/drivers/soc/fsl/qe/ucc_fast.c
1034 +++ b/drivers/soc/fsl/qe/ucc_fast.c
1035 @@ -33,41 +33,41 @@ void ucc_fast_dump_regs(struct ucc_fast_private * uccf)
1036 printk(KERN_INFO "Base address: 0x%p\n", uccf->uf_regs);
1037
1038 printk(KERN_INFO "gumr : addr=0x%p, val=0x%08x\n",
1039 - &uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr));
1040 + &uccf->uf_regs->gumr, ioread32be(&uccf->uf_regs->gumr));
1041 printk(KERN_INFO "upsmr : addr=0x%p, val=0x%08x\n",
1042 - &uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr));
1043 + &uccf->uf_regs->upsmr, ioread32be(&uccf->uf_regs->upsmr));
1044 printk(KERN_INFO "utodr : addr=0x%p, val=0x%04x\n",
1045 - &uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr));
1046 + &uccf->uf_regs->utodr, ioread16be(&uccf->uf_regs->utodr));
1047 printk(KERN_INFO "udsr : addr=0x%p, val=0x%04x\n",
1048 - &uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr));
1049 + &uccf->uf_regs->udsr, ioread16be(&uccf->uf_regs->udsr));
1050 printk(KERN_INFO "ucce : addr=0x%p, val=0x%08x\n",
1051 - &uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce));
1052 + &uccf->uf_regs->ucce, ioread32be(&uccf->uf_regs->ucce));
1053 printk(KERN_INFO "uccm : addr=0x%p, val=0x%08x\n",
1054 - &uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));
1055 + &uccf->uf_regs->uccm, ioread32be(&uccf->uf_regs->uccm));
1056 printk(KERN_INFO "uccs : addr=0x%p, val=0x%02x\n",
1057 - &uccf->uf_regs->uccs, in_8(&uccf->uf_regs->uccs));
1058 + &uccf->uf_regs->uccs, ioread8(&uccf->uf_regs->uccs));
1059 printk(KERN_INFO "urfb : addr=0x%p, val=0x%08x\n",
1060 - &uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));
1061 + &uccf->uf_regs->urfb, ioread32be(&uccf->uf_regs->urfb));
1062 printk(KERN_INFO "urfs : addr=0x%p, val=0x%04x\n",
1063 - &uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs));
1064 + &uccf->uf_regs->urfs, ioread16be(&uccf->uf_regs->urfs));
1065 printk(KERN_INFO "urfet : addr=0x%p, val=0x%04x\n",
1066 - &uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet));
1067 + &uccf->uf_regs->urfet, ioread16be(&uccf->uf_regs->urfet));
1068 printk(KERN_INFO "urfset: addr=0x%p, val=0x%04x\n",
1069 - &uccf->uf_regs->urfset, in_be16(&uccf->uf_regs->urfset));
1070 + &uccf->uf_regs->urfset, ioread16be(&uccf->uf_regs->urfset));
1071 printk(KERN_INFO "utfb : addr=0x%p, val=0x%08x\n",
1072 - &uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb));
1073 + &uccf->uf_regs->utfb, ioread32be(&uccf->uf_regs->utfb));
1074 printk(KERN_INFO "utfs : addr=0x%p, val=0x%04x\n",
1075 - &uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs));
1076 + &uccf->uf_regs->utfs, ioread16be(&uccf->uf_regs->utfs));
1077 printk(KERN_INFO "utfet : addr=0x%p, val=0x%04x\n",
1078 - &uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet));
1079 + &uccf->uf_regs->utfet, ioread16be(&uccf->uf_regs->utfet));
1080 printk(KERN_INFO "utftt : addr=0x%p, val=0x%04x\n",
1081 - &uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt));
1082 + &uccf->uf_regs->utftt, ioread16be(&uccf->uf_regs->utftt));
1083 printk(KERN_INFO "utpt : addr=0x%p, val=0x%04x\n",
1084 - &uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt));
1085 + &uccf->uf_regs->utpt, ioread16be(&uccf->uf_regs->utpt));
1086 printk(KERN_INFO "urtry : addr=0x%p, val=0x%08x\n",
1087 - &uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));
1088 + &uccf->uf_regs->urtry, ioread32be(&uccf->uf_regs->urtry));
1089 printk(KERN_INFO "guemr : addr=0x%p, val=0x%02x\n",
1090 - &uccf->uf_regs->guemr, in_8(&uccf->uf_regs->guemr));
1091 + &uccf->uf_regs->guemr, ioread8(&uccf->uf_regs->guemr));
1092 }
1093 EXPORT_SYMBOL(ucc_fast_dump_regs);
1094
1095 @@ -89,7 +89,7 @@ EXPORT_SYMBOL(ucc_fast_get_qe_cr_subblock);
1096
1097 void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf)
1098 {
1099 - out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
1100 + iowrite16be(UCC_FAST_TOD, &uccf->uf_regs->utodr);
1101 }
1102 EXPORT_SYMBOL(ucc_fast_transmit_on_demand);
1103
1104 @@ -101,7 +101,7 @@ void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
1105 uf_regs = uccf->uf_regs;
1106
1107 /* Enable reception and/or transmission on this UCC. */
1108 - gumr = in_be32(&uf_regs->gumr);
1109 + gumr = ioread32be(&uf_regs->gumr);
1110 if (mode & COMM_DIR_TX) {
1111 gumr |= UCC_FAST_GUMR_ENT;
1112 uccf->enabled_tx = 1;
1113 @@ -110,7 +110,7 @@ void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
1114 gumr |= UCC_FAST_GUMR_ENR;
1115 uccf->enabled_rx = 1;
1116 }
1117 - out_be32(&uf_regs->gumr, gumr);
1118 + iowrite32be(gumr, &uf_regs->gumr);
1119 }
1120 EXPORT_SYMBOL(ucc_fast_enable);
1121
1122 @@ -122,7 +122,7 @@ void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
1123 uf_regs = uccf->uf_regs;
1124
1125 /* Disable reception and/or transmission on this UCC. */
1126 - gumr = in_be32(&uf_regs->gumr);
1127 + gumr = ioread32be(&uf_regs->gumr);
1128 if (mode & COMM_DIR_TX) {
1129 gumr &= ~UCC_FAST_GUMR_ENT;
1130 uccf->enabled_tx = 0;
1131 @@ -131,7 +131,7 @@ void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
1132 gumr &= ~UCC_FAST_GUMR_ENR;
1133 uccf->enabled_rx = 0;
1134 }
1135 - out_be32(&uf_regs->gumr, gumr);
1136 + iowrite32be(gumr, &uf_regs->gumr);
1137 }
1138 EXPORT_SYMBOL(ucc_fast_disable);
1139
1140 @@ -263,12 +263,13 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
1141 gumr |= uf_info->tenc;
1142 gumr |= uf_info->tcrc;
1143 gumr |= uf_info->mode;
1144 - out_be32(&uf_regs->gumr, gumr);
1145 + iowrite32be(gumr, &uf_regs->gumr);
1146
1147 /* Allocate memory for Tx Virtual Fifo */
1148 uccf->ucc_fast_tx_virtual_fifo_base_offset =
1149 qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
1150 - if (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {
1151 + if (IS_ERR_VALUE((unsigned long)uccf->
1152 + ucc_fast_tx_virtual_fifo_base_offset)) {
1153 printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO\n",
1154 __func__);
1155 uccf->ucc_fast_tx_virtual_fifo_base_offset = 0;
1156 @@ -281,7 +282,8 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
1157 qe_muram_alloc(uf_info->urfs +
1158 UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR,
1159 UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
1160 - if (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) {
1161 + if (IS_ERR_VALUE((unsigned long)uccf->
1162 + ucc_fast_rx_virtual_fifo_base_offset)) {
1163 printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO\n",
1164 __func__);
1165 uccf->ucc_fast_rx_virtual_fifo_base_offset = 0;
1166 @@ -290,15 +292,15 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
1167 }
1168
1169 /* Set Virtual Fifo registers */
1170 - out_be16(&uf_regs->urfs, uf_info->urfs);
1171 - out_be16(&uf_regs->urfet, uf_info->urfet);
1172 - out_be16(&uf_regs->urfset, uf_info->urfset);
1173 - out_be16(&uf_regs->utfs, uf_info->utfs);
1174 - out_be16(&uf_regs->utfet, uf_info->utfet);
1175 - out_be16(&uf_regs->utftt, uf_info->utftt);
1176 + iowrite16be(uf_info->urfs, &uf_regs->urfs);
1177 + iowrite16be(uf_info->urfet, &uf_regs->urfet);
1178 + iowrite16be(uf_info->urfset, &uf_regs->urfset);
1179 + iowrite16be(uf_info->utfs, &uf_regs->utfs);
1180 + iowrite16be(uf_info->utfet, &uf_regs->utfet);
1181 + iowrite16be(uf_info->utftt, &uf_regs->utftt);
1182 /* utfb, urfb are offsets from MURAM base */
1183 - out_be32(&uf_regs->utfb, uccf->ucc_fast_tx_virtual_fifo_base_offset);
1184 - out_be32(&uf_regs->urfb, uccf->ucc_fast_rx_virtual_fifo_base_offset);
1185 + iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset, &uf_regs->utfb);
1186 + iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset, &uf_regs->urfb);
1187
1188 /* Mux clocking */
1189 /* Grant Support */
1190 @@ -366,14 +368,14 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
1191 }
1192
1193 /* Set interrupt mask register at UCC level. */
1194 - out_be32(&uf_regs->uccm, uf_info->uccm_mask);
1195 + iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);
1196
1197 /* First, clear anything pending at UCC level,
1198 * otherwise, old garbage may come through
1199 * as soon as the dam is opened. */
1200
1201 /* Writing '1' clears */
1202 - out_be32(&uf_regs->ucce, 0xffffffff);
1203 + iowrite32be(0xffffffff, &uf_regs->ucce);
1204
1205 *uccf_ret = uccf;
1206 return 0;
1207 diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
1208 index 481eb298..ee409fdf 100644
1209 --- a/drivers/tty/serial/ucc_uart.c
1210 +++ b/drivers/tty/serial/ucc_uart.c
1211 @@ -34,6 +34,7 @@
1212 #include <soc/fsl/qe/ucc_slow.h>
1213
1214 #include <linux/firmware.h>
1215 +#include <asm/cpm.h>
1216 #include <asm/reg.h>
1217
1218 /*
1219 diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
1220 index 70339d79..f7a14f2d 100644
1221 --- a/include/soc/fsl/qe/qe.h
1222 +++ b/include/soc/fsl/qe/qe.h
1223 @@ -21,7 +21,6 @@
1224 #include <linux/spinlock.h>
1225 #include <linux/errno.h>
1226 #include <linux/err.h>
1227 -#include <asm/cpm.h>
1228 #include <soc/fsl/qe/immap_qe.h>
1229 #include <linux/of.h>
1230 #include <linux/of_address.h>
1231 diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
1232 deleted file mode 100644
1233 index 1e155ca6..00000000
1234 --- a/include/soc/fsl/qe/qe_ic.h
1235 +++ /dev/null
1236 @@ -1,139 +0,0 @@
1237 -/*
1238 - * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
1239 - *
1240 - * Authors: Shlomi Gridish <gridish@freescale.com>
1241 - * Li Yang <leoli@freescale.com>
1242 - *
1243 - * Description:
1244 - * QE IC external definitions and structure.
1245 - *
1246 - * This program is free software; you can redistribute it and/or modify it
1247 - * under the terms of the GNU General Public License as published by the
1248 - * Free Software Foundation; either version 2 of the License, or (at your
1249 - * option) any later version.
1250 - */
1251 -#ifndef _ASM_POWERPC_QE_IC_H
1252 -#define _ASM_POWERPC_QE_IC_H
1253 -
1254 -#include <linux/irq.h>
1255 -
1256 -struct device_node;
1257 -struct qe_ic;
1258 -
1259 -#define NUM_OF_QE_IC_GROUPS 6
1260 -
1261 -/* Flags when we init the QE IC */
1262 -#define QE_IC_SPREADMODE_GRP_W 0x00000001
1263 -#define QE_IC_SPREADMODE_GRP_X 0x00000002
1264 -#define QE_IC_SPREADMODE_GRP_Y 0x00000004
1265 -#define QE_IC_SPREADMODE_GRP_Z 0x00000008
1266 -#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
1267 -#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
1268 -
1269 -#define QE_IC_LOW_SIGNAL 0x00000100
1270 -#define QE_IC_HIGH_SIGNAL 0x00000200
1271 -
1272 -#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
1273 -#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
1274 -#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
1275 -#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
1276 -#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
1277 -#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
1278 -#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
1279 -#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
1280 -#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
1281 -#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
1282 -#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
1283 -#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
1284 -#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
1285 -
1286 -/* QE interrupt sources groups */
1287 -enum qe_ic_grp_id {
1288 - QE_IC_GRP_W = 0, /* QE interrupt controller group W */
1289 - QE_IC_GRP_X, /* QE interrupt controller group X */
1290 - QE_IC_GRP_Y, /* QE interrupt controller group Y */
1291 - QE_IC_GRP_Z, /* QE interrupt controller group Z */
1292 - QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
1293 - QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
1294 -};
1295 -
1296 -#ifdef CONFIG_QUICC_ENGINE
1297 -void qe_ic_init(struct device_node *node, unsigned int flags,
1298 - void (*low_handler)(struct irq_desc *desc),
1299 - void (*high_handler)(struct irq_desc *desc));
1300 -unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
1301 -unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
1302 -#else
1303 -static inline void qe_ic_init(struct device_node *node, unsigned int flags,
1304 - void (*low_handler)(struct irq_desc *desc),
1305 - void (*high_handler)(struct irq_desc *desc))
1306 -{}
1307 -static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
1308 -{ return 0; }
1309 -static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
1310 -{ return 0; }
1311 -#endif /* CONFIG_QUICC_ENGINE */
1312 -
1313 -void qe_ic_set_highest_priority(unsigned int virq, int high);
1314 -int qe_ic_set_priority(unsigned int virq, unsigned int priority);
1315 -int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
1316 -
1317 -static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
1318 -{
1319 - struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
1320 - unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
1321 -
1322 - if (cascade_irq != NO_IRQ)
1323 - generic_handle_irq(cascade_irq);
1324 -}
1325 -
1326 -static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
1327 -{
1328 - struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
1329 - unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
1330 -
1331 - if (cascade_irq != NO_IRQ)
1332 - generic_handle_irq(cascade_irq);
1333 -}
1334 -
1335 -static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
1336 -{
1337 - struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
1338 - unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
1339 - struct irq_chip *chip = irq_desc_get_chip(desc);
1340 -
1341 - if (cascade_irq != NO_IRQ)
1342 - generic_handle_irq(cascade_irq);
1343 -
1344 - chip->irq_eoi(&desc->irq_data);
1345 -}
1346 -
1347 -static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
1348 -{
1349 - struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
1350 - unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
1351 - struct irq_chip *chip = irq_desc_get_chip(desc);
1352 -
1353 - if (cascade_irq != NO_IRQ)
1354 - generic_handle_irq(cascade_irq);
1355 -
1356 - chip->irq_eoi(&desc->irq_data);
1357 -}
1358 -
1359 -static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
1360 -{
1361 - struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
1362 - unsigned int cascade_irq;
1363 - struct irq_chip *chip = irq_desc_get_chip(desc);
1364 -
1365 - cascade_irq = qe_ic_get_high_irq(qe_ic);
1366 - if (cascade_irq == NO_IRQ)
1367 - cascade_irq = qe_ic_get_low_irq(qe_ic);
1368 -
1369 - if (cascade_irq != NO_IRQ)
1370 - generic_handle_irq(cascade_irq);
1371 -
1372 - chip->irq_eoi(&desc->irq_data);
1373 -}
1374 -
1375 -#endif /* _ASM_POWERPC_QE_IC_H */
1376 --
1377 2.14.1
1378
Hauke Mehrtens staging tree