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[openwrt/staging/hauke.git] / target / linux / layerscape / patches-4.9 / 808-guts-support-layerscape.patch
1 From d51e307e4ecf51832c9e3bc30acb5dbd559d5f4d Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 12:19:34 +0800
4 Subject: [PATCH] guts: support layerscape
5
6 This is a integrated patch for layerscape guts support.
7
8 Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
9 Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
10 Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
11 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
12 ---
13 drivers/base/soc.c | 12 ++-
14 drivers/soc/fsl/guts.c | 238 +++++++++++++++++++++++++++++++++++++++++++++++
15 include/linux/fsl/guts.h | 125 +++++++++++++++----------
16 3 files changed, 323 insertions(+), 52 deletions(-)
17 create mode 100644 drivers/soc/fsl/guts.c
18
19 diff --git a/drivers/base/soc.c b/drivers/base/soc.c
20 index 0c5cf872..0e701e22 100644
21 --- a/drivers/base/soc.c
22 +++ b/drivers/base/soc.c
23 @@ -167,19 +167,23 @@ static int soc_device_match_one(struct device *dev, void *arg)
24 const struct soc_device_attribute *match = arg;
25
26 if (match->machine &&
27 - !glob_match(match->machine, soc_dev->attr->machine))
28 + (!soc_dev->attr->machine ||
29 + !glob_match(match->machine, soc_dev->attr->machine)))
30 return 0;
31
32 if (match->family &&
33 - !glob_match(match->family, soc_dev->attr->family))
34 + (!soc_dev->attr->family ||
35 + !glob_match(match->family, soc_dev->attr->family)))
36 return 0;
37
38 if (match->revision &&
39 - !glob_match(match->revision, soc_dev->attr->revision))
40 + (!soc_dev->attr->revision ||
41 + !glob_match(match->revision, soc_dev->attr->revision)))
42 return 0;
43
44 if (match->soc_id &&
45 - !glob_match(match->soc_id, soc_dev->attr->soc_id))
46 + (!soc_dev->attr->soc_id ||
47 + !glob_match(match->soc_id, soc_dev->attr->soc_id)))
48 return 0;
49
50 return 1;
51 diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c
52 new file mode 100644
53 index 00000000..7d28784a
54 --- /dev/null
55 +++ b/drivers/soc/fsl/guts.c
56 @@ -0,0 +1,238 @@
57 +/*
58 + * Freescale QorIQ Platforms GUTS Driver
59 + *
60 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
61 + *
62 + * This program is free software; you can redistribute it and/or modify
63 + * it under the terms of the GNU General Public License as published by
64 + * the Free Software Foundation; either version 2 of the License, or
65 + * (at your option) any later version.
66 + */
67 +
68 +#include <linux/io.h>
69 +#include <linux/slab.h>
70 +#include <linux/module.h>
71 +#include <linux/of_fdt.h>
72 +#include <linux/sys_soc.h>
73 +#include <linux/of_address.h>
74 +#include <linux/platform_device.h>
75 +#include <linux/fsl/guts.h>
76 +
77 +struct guts {
78 + struct ccsr_guts __iomem *regs;
79 + bool little_endian;
80 +};
81 +
82 +struct fsl_soc_die_attr {
83 + char *die;
84 + u32 svr;
85 + u32 mask;
86 +};
87 +
88 +static struct guts *guts;
89 +static struct soc_device_attribute soc_dev_attr;
90 +static struct soc_device *soc_dev;
91 +
92 +
93 +/* SoC die attribute definition for QorIQ platform */
94 +static const struct fsl_soc_die_attr fsl_soc_die[] = {
95 + /*
96 + * Power Architecture-based SoCs T Series
97 + */
98 +
99 + /* Die: T4240, SoC: T4240/T4160/T4080 */
100 + { .die = "T4240",
101 + .svr = 0x82400000,
102 + .mask = 0xfff00000,
103 + },
104 + /* Die: T1040, SoC: T1040/T1020/T1042/T1022 */
105 + { .die = "T1040",
106 + .svr = 0x85200000,
107 + .mask = 0xfff00000,
108 + },
109 + /* Die: T2080, SoC: T2080/T2081 */
110 + { .die = "T2080",
111 + .svr = 0x85300000,
112 + .mask = 0xfff00000,
113 + },
114 + /* Die: T1024, SoC: T1024/T1014/T1023/T1013 */
115 + { .die = "T1024",
116 + .svr = 0x85400000,
117 + .mask = 0xfff00000,
118 + },
119 +
120 + /*
121 + * ARM-based SoCs LS Series
122 + */
123 +
124 + /* Die: LS1043A, SoC: LS1043A/LS1023A */
125 + { .die = "LS1043A",
126 + .svr = 0x87920000,
127 + .mask = 0xffff0000,
128 + },
129 + /* Die: LS2080A, SoC: LS2080A/LS2040A/LS2085A */
130 + { .die = "LS2080A",
131 + .svr = 0x87010000,
132 + .mask = 0xff3f0000,
133 + },
134 + /* Die: LS1088A, SoC: LS1088A/LS1048A/LS1084A/LS1044A */
135 + { .die = "LS1088A",
136 + .svr = 0x87030000,
137 + .mask = 0xff3f0000,
138 + },
139 + /* Die: LS1012A, SoC: LS1012A */
140 + { .die = "LS1012A",
141 + .svr = 0x87040000,
142 + .mask = 0xffff0000,
143 + },
144 + /* Die: LS1046A, SoC: LS1046A/LS1026A */
145 + { .die = "LS1046A",
146 + .svr = 0x87070000,
147 + .mask = 0xffff0000,
148 + },
149 + /* Die: LS2088A, SoC: LS2088A/LS2048A/LS2084A/LS2044A */
150 + { .die = "LS2088A",
151 + .svr = 0x87090000,
152 + .mask = 0xff3f0000,
153 + },
154 + /* Die: LS1021A, SoC: LS1021A/LS1020A/LS1022A */
155 + { .die = "LS1021A",
156 + .svr = 0x87000000,
157 + .mask = 0xfff70000,
158 + },
159 + { },
160 +};
161 +
162 +static const struct fsl_soc_die_attr *fsl_soc_die_match(
163 + u32 svr, const struct fsl_soc_die_attr *matches)
164 +{
165 + while (matches->svr) {
166 + if (matches->svr == (svr & matches->mask))
167 + return matches;
168 + matches++;
169 + };
170 + return NULL;
171 +}
172 +
173 +u32 fsl_guts_get_svr(void)
174 +{
175 + u32 svr = 0;
176 +
177 + if (!guts || !guts->regs)
178 + return svr;
179 +
180 + if (guts->little_endian)
181 + svr = ioread32(&guts->regs->svr);
182 + else
183 + svr = ioread32be(&guts->regs->svr);
184 +
185 + return svr;
186 +}
187 +EXPORT_SYMBOL(fsl_guts_get_svr);
188 +
189 +static int fsl_guts_probe(struct platform_device *pdev)
190 +{
191 + struct device_node *np = pdev->dev.of_node;
192 + struct device *dev = &pdev->dev;
193 + struct resource *res;
194 + const struct fsl_soc_die_attr *soc_die;
195 + const char *machine;
196 + u32 svr;
197 +
198 + /* Initialize guts */
199 + guts = devm_kzalloc(dev, sizeof(*guts), GFP_KERNEL);
200 + if (!guts)
201 + return -ENOMEM;
202 +
203 + guts->little_endian = of_property_read_bool(np, "little-endian");
204 +
205 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
206 + guts->regs = devm_ioremap_resource(dev, res);
207 + if (IS_ERR(guts->regs))
208 + return PTR_ERR(guts->regs);
209 +
210 + /* Register soc device */
211 + machine = of_flat_dt_get_machine_name();
212 + if (machine)
213 + soc_dev_attr.machine = devm_kstrdup(dev, machine, GFP_KERNEL);
214 +
215 + svr = fsl_guts_get_svr();
216 + soc_die = fsl_soc_die_match(svr, fsl_soc_die);
217 + if (soc_die) {
218 + soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL,
219 + "QorIQ %s", soc_die->die);
220 + } else {
221 + soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL, "QorIQ");
222 + }
223 + soc_dev_attr.soc_id = devm_kasprintf(dev, GFP_KERNEL,
224 + "svr:0x%08x", svr);
225 + soc_dev_attr.revision = devm_kasprintf(dev, GFP_KERNEL, "%d.%d",
226 + (svr >> 4) & 0xf, svr & 0xf);
227 +
228 + soc_dev = soc_device_register(&soc_dev_attr);
229 + if (IS_ERR(soc_dev))
230 + return PTR_ERR(soc_dev);
231 +
232 + pr_info("Machine: %s\n", soc_dev_attr.machine);
233 + pr_info("SoC family: %s\n", soc_dev_attr.family);
234 + pr_info("SoC ID: %s, Revision: %s\n",
235 + soc_dev_attr.soc_id, soc_dev_attr.revision);
236 + return 0;
237 +}
238 +
239 +static int fsl_guts_remove(struct platform_device *dev)
240 +{
241 + soc_device_unregister(soc_dev);
242 + return 0;
243 +}
244 +
245 +/*
246 + * Table for matching compatible strings, for device tree
247 + * guts node, for Freescale QorIQ SOCs.
248 + */
249 +static const struct of_device_id fsl_guts_of_match[] = {
250 + { .compatible = "fsl,qoriq-device-config-1.0", },
251 + { .compatible = "fsl,qoriq-device-config-2.0", },
252 + { .compatible = "fsl,p1010-guts", },
253 + { .compatible = "fsl,p1020-guts", },
254 + { .compatible = "fsl,p1021-guts", },
255 + { .compatible = "fsl,p1022-guts", },
256 + { .compatible = "fsl,p1023-guts", },
257 + { .compatible = "fsl,p2020-guts", },
258 + { .compatible = "fsl,bsc9131-guts", },
259 + { .compatible = "fsl,bsc9132-guts", },
260 + { .compatible = "fsl,mpc8536-guts", },
261 + { .compatible = "fsl,mpc8544-guts", },
262 + { .compatible = "fsl,mpc8548-guts", },
263 + { .compatible = "fsl,mpc8568-guts", },
264 + { .compatible = "fsl,mpc8569-guts", },
265 + { .compatible = "fsl,mpc8572-guts", },
266 + { .compatible = "fsl,ls1021a-dcfg", },
267 + { .compatible = "fsl,ls1043a-dcfg", },
268 + { .compatible = "fsl,ls1046a-dcfg", },
269 + { .compatible = "fsl,ls2080a-dcfg", },
270 + { .compatible = "fsl,ls1088a-dcfg", },
271 + {}
272 +};
273 +MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
274 +
275 +static struct platform_driver fsl_guts_driver = {
276 + .driver = {
277 + .name = "fsl-guts",
278 + .of_match_table = fsl_guts_of_match,
279 + },
280 + .probe = fsl_guts_probe,
281 + .remove = fsl_guts_remove,
282 +};
283 +
284 +static int __init fsl_guts_init(void)
285 +{
286 + return platform_driver_register(&fsl_guts_driver);
287 +}
288 +core_initcall(fsl_guts_init);
289 +
290 +static void __exit fsl_guts_exit(void)
291 +{
292 + platform_driver_unregister(&fsl_guts_driver);
293 +}
294 +module_exit(fsl_guts_exit);
295 diff --git a/include/linux/fsl/guts.h b/include/linux/fsl/guts.h
296 index 649e9171..3efa3b86 100644
297 --- a/include/linux/fsl/guts.h
298 +++ b/include/linux/fsl/guts.h
299 @@ -29,83 +29,112 @@
300 * #ifdefs.
301 */
302 struct ccsr_guts {
303 - __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
304 - __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
305 - __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
306 - __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
307 - __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
308 - __be32 pordevsr2; /* 0x.0014 - POR device status register 2 */
309 + u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
310 + u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
311 + u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and
312 + * Control Register
313 + */
314 + u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
315 + u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
316 + u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
317 u8 res018[0x20 - 0x18];
318 - __be32 porcir; /* 0x.0020 - POR Configuration Information Register */
319 + u32 porcir; /* 0x.0020 - POR Configuration Information
320 + * Register
321 + */
322 u8 res024[0x30 - 0x24];
323 - __be32 gpiocr; /* 0x.0030 - GPIO Control Register */
324 + u32 gpiocr; /* 0x.0030 - GPIO Control Register */
325 u8 res034[0x40 - 0x34];
326 - __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
327 + u32 gpoutdr; /* 0x.0040 - General-Purpose Output Data
328 + * Register
329 + */
330 u8 res044[0x50 - 0x44];
331 - __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */
332 + u32 gpindr; /* 0x.0050 - General-Purpose Input Data
333 + * Register
334 + */
335 u8 res054[0x60 - 0x54];
336 - __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
337 - __be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */
338 - __be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
339 + u32 pmuxcr; /* 0x.0060 - Alternate Function Signal
340 + * Multiplex Control
341 + */
342 + u32 pmuxcr2; /* 0x.0064 - Alternate function signal
343 + * multiplex control 2
344 + */
345 + u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
346 u8 res06c[0x70 - 0x6c];
347 - __be32 devdisr; /* 0x.0070 - Device Disable Control */
348 + u32 devdisr; /* 0x.0070 - Device Disable Control */
349 #define CCSR_GUTS_DEVDISR_TB1 0x00001000
350 #define CCSR_GUTS_DEVDISR_TB0 0x00004000
351 - __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
352 + u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
353 u8 res078[0x7c - 0x78];
354 - __be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */
355 - __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
356 - __be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */
357 - __be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */
358 - __be32 pmcdr; /* 0x.008c - 4Power management clock disable register */
359 - __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
360 - __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */
361 - __be32 ectrstcr; /* 0x.0098 - Exception reset control register */
362 - __be32 autorstsr; /* 0x.009c - Automatic reset status register */
363 - __be32 pvr; /* 0x.00a0 - Processor Version Register */
364 - __be32 svr; /* 0x.00a4 - System Version Register */
365 + u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control
366 + * Register
367 + */
368 + u32 powmgtcsr; /* 0x.0080 - Power Management Status and
369 + * Control Register
370 + */
371 + u32 pmrccr; /* 0x.0084 - Power Management Reset Counter
372 + * Configuration Register
373 + */
374 + u32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter
375 + * Configuration Register
376 + */
377 + u32 pmcdr; /* 0x.008c - 4Power management clock disable
378 + * register
379 + */
380 + u32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
381 + u32 rstrscr; /* 0x.0094 - Reset Request Status and
382 + * Control Register
383 + */
384 + u32 ectrstcr; /* 0x.0098 - Exception reset control register */
385 + u32 autorstsr; /* 0x.009c - Automatic reset status register */
386 + u32 pvr; /* 0x.00a0 - Processor Version Register */
387 + u32 svr; /* 0x.00a4 - System Version Register */
388 u8 res0a8[0xb0 - 0xa8];
389 - __be32 rstcr; /* 0x.00b0 - Reset Control Register */
390 + u32 rstcr; /* 0x.00b0 - Reset Control Register */
391 u8 res0b4[0xc0 - 0xb4];
392 - __be32 iovselsr; /* 0x.00c0 - I/O voltage select status register
393 + u32 iovselsr; /* 0x.00c0 - I/O voltage select status register
394 Called 'elbcvselcr' on 86xx SOCs */
395 u8 res0c4[0x100 - 0xc4];
396 - __be32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
397 + u32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
398 There are 16 registers */
399 u8 res140[0x224 - 0x140];
400 - __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
401 - __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
402 + u32 iodelay1; /* 0x.0224 - IO delay control register 1 */
403 + u32 iodelay2; /* 0x.0228 - IO delay control register 2 */
404 u8 res22c[0x604 - 0x22c];
405 - __be32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
406 + u32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
407 u8 res608[0x800 - 0x608];
408 - __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
409 + u32 clkdvdr; /* 0x.0800 - Clock Divide Register */
410 u8 res804[0x900 - 0x804];
411 - __be32 ircr; /* 0x.0900 - Infrared Control Register */
412 + u32 ircr; /* 0x.0900 - Infrared Control Register */
413 u8 res904[0x908 - 0x904];
414 - __be32 dmacr; /* 0x.0908 - DMA Control Register */
415 + u32 dmacr; /* 0x.0908 - DMA Control Register */
416 u8 res90c[0x914 - 0x90c];
417 - __be32 elbccr; /* 0x.0914 - eLBC Control Register */
418 + u32 elbccr; /* 0x.0914 - eLBC Control Register */
419 u8 res918[0xb20 - 0x918];
420 - __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
421 - __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
422 - __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
423 + u32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
424 + u32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
425 + u32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
426 u8 resb2c[0xe00 - 0xb2c];
427 - __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */
428 + u32 clkocr; /* 0x.0e00 - Clock Out Select Register */
429 u8 rese04[0xe10 - 0xe04];
430 - __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
431 + u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
432 u8 rese14[0xe20 - 0xe14];
433 - __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
434 - __be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */
435 + u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
436 + u32 cpfor; /* 0x.0e24 - L2 charge pump fuse override
437 + * register
438 + */
439 u8 rese28[0xf04 - 0xe28];
440 - __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
441 - __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
442 + u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
443 + u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
444 u8 resf0c[0xf2c - 0xf0c];
445 - __be32 itcr; /* 0x.0f2c - Internal transaction control register */
446 + u32 itcr; /* 0x.0f2c - Internal transaction control
447 + * register
448 + */
449 u8 resf30[0xf40 - 0xf30];
450 - __be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
451 - __be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
452 + u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
453 + u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
454 } __attribute__ ((packed));
455
456 +u32 fsl_guts_get_svr(void);
457
458 /* Alternate function signal multiplex control */
459 #define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
460 --
461 2.14.1
462
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