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layerscape: refresh patches
[openwrt/staging/hauke.git] / target / linux / layerscape / patches-4.9 / 401-mtd-spi-nor-support-layerscape.patch
1 From 120fa458ffe2250ea58578ccfc85e674005463dc Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 10:53:50 +0800
4 Subject: [PATCH] mtd: spi-nor: support layerscape
5
6 This is a integrated patch for layerscape qspi support.
7
8 Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
9 Signed-off-by: Yunhui Cui <B56489@freescale.com>
10 Signed-off-by: mar.krzeminski <mar.krzeminski@gmail.com>
11 Signed-off-by: Alison Wang <b18965@freescale.com>
12 Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com>
13 Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
14 Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
15 Signed-off-by: Alexander Kurz <akurz@blala.de>
16 Signed-off-by: L. D. Pinney <ldpinney@gmail.com>
17 Signed-off-by: Ash Benz <ash.benz@bk.ru>
18 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
19 ---
20 drivers/mtd/mtdchar.c | 2 +-
21 drivers/mtd/spi-nor/fsl-quadspi.c | 356 +++++++++++++++++++++++++++++++-------
22 drivers/mtd/spi-nor/spi-nor.c | 136 +++++++++++++--
23 include/linux/mtd/spi-nor.h | 14 +-
24 4 files changed, 432 insertions(+), 76 deletions(-)
25
26 --- a/drivers/mtd/mtdchar.c
27 +++ b/drivers/mtd/mtdchar.c
28 @@ -451,7 +451,7 @@ static int mtdchar_readoob(struct file *
29 * data. For our userspace tools it is important to dump areas
30 * with ECC errors!
31 * For kernel internal usage it also might return -EUCLEAN
32 - * to signal the caller that a bitflip has occured and has
33 + * to signal the caller that a bitflip has occurred and has
34 * been corrected by the ECC algorithm.
35 *
36 * Note: currently the standard NAND function, nand_read_oob_std,
37 --- a/drivers/mtd/spi-nor/fsl-quadspi.c
38 +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
39 @@ -41,6 +41,8 @@
40 #define QUADSPI_QUIRK_TKT253890 (1 << 2)
41 /* Controller cannot wake up from wait mode, TKT245618 */
42 #define QUADSPI_QUIRK_TKT245618 (1 << 3)
43 +/* QSPI_AMBA_BASE is internally added by SOC design */
44 +#define QUADSPI_AMBA_BASE_INTERNAL (0x10000)
45
46 /* The registers */
47 #define QUADSPI_MCR 0x00
48 @@ -193,7 +195,7 @@
49 #define QUADSPI_LUT_NUM 64
50
51 /* SEQID -- we can have 16 seqids at most. */
52 -#define SEQID_QUAD_READ 0
53 +#define SEQID_READ 0
54 #define SEQID_WREN 1
55 #define SEQID_WRDI 2
56 #define SEQID_RDSR 3
57 @@ -205,15 +207,22 @@
58 #define SEQID_RDCR 9
59 #define SEQID_EN4B 10
60 #define SEQID_BRWR 11
61 +#define SEQID_RDAR_OR_RD_EVCR 12
62 +#define SEQID_WRAR 13
63 +#define SEQID_WD_EVCR 14
64
65 #define QUADSPI_MIN_IOMAP SZ_4M
66
67 +#define FLASH_VENDOR_SPANSION_FS "s25fs"
68 +#define SPANSION_S25FS_FAMILY (1 << 1)
69 +
70 enum fsl_qspi_devtype {
71 FSL_QUADSPI_VYBRID,
72 FSL_QUADSPI_IMX6SX,
73 FSL_QUADSPI_IMX7D,
74 FSL_QUADSPI_IMX6UL,
75 FSL_QUADSPI_LS1021A,
76 + FSL_QUADSPI_LS2080A,
77 };
78
79 struct fsl_qspi_devtype_data {
80 @@ -224,7 +233,7 @@ struct fsl_qspi_devtype_data {
81 int driver_data;
82 };
83
84 -static struct fsl_qspi_devtype_data vybrid_data = {
85 +static const struct fsl_qspi_devtype_data vybrid_data = {
86 .devtype = FSL_QUADSPI_VYBRID,
87 .rxfifo = 128,
88 .txfifo = 64,
89 @@ -232,7 +241,7 @@ static struct fsl_qspi_devtype_data vybr
90 .driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
91 };
92
93 -static struct fsl_qspi_devtype_data imx6sx_data = {
94 +static const struct fsl_qspi_devtype_data imx6sx_data = {
95 .devtype = FSL_QUADSPI_IMX6SX,
96 .rxfifo = 128,
97 .txfifo = 512,
98 @@ -241,7 +250,7 @@ static struct fsl_qspi_devtype_data imx6
99 | QUADSPI_QUIRK_TKT245618,
100 };
101
102 -static struct fsl_qspi_devtype_data imx7d_data = {
103 +static const struct fsl_qspi_devtype_data imx7d_data = {
104 .devtype = FSL_QUADSPI_IMX7D,
105 .rxfifo = 512,
106 .txfifo = 512,
107 @@ -250,7 +259,7 @@ static struct fsl_qspi_devtype_data imx7
108 | QUADSPI_QUIRK_4X_INT_CLK,
109 };
110
111 -static struct fsl_qspi_devtype_data imx6ul_data = {
112 +static const struct fsl_qspi_devtype_data imx6ul_data = {
113 .devtype = FSL_QUADSPI_IMX6UL,
114 .rxfifo = 128,
115 .txfifo = 512,
116 @@ -267,6 +276,14 @@ static struct fsl_qspi_devtype_data ls10
117 .driver_data = 0,
118 };
119
120 +static struct fsl_qspi_devtype_data ls2080a_data = {
121 + .devtype = FSL_QUADSPI_LS2080A,
122 + .rxfifo = 128,
123 + .txfifo = 64,
124 + .ahb_buf_size = 1024,
125 + .driver_data = QUADSPI_AMBA_BASE_INTERNAL | QUADSPI_QUIRK_TKT253890,
126 +};
127 +
128 #define FSL_QSPI_MAX_CHIP 4
129 struct fsl_qspi {
130 struct spi_nor nor[FSL_QSPI_MAX_CHIP];
131 @@ -282,6 +299,7 @@ struct fsl_qspi {
132 u32 nor_size;
133 u32 nor_num;
134 u32 clk_rate;
135 + u32 ddr_smp;
136 unsigned int chip_base_addr; /* We may support two chips. */
137 bool has_second_chip;
138 bool big_endian;
139 @@ -309,6 +327,23 @@ static inline int needs_wakeup_wait_mode
140 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
141 }
142
143 +static inline int has_added_amba_base_internal(struct fsl_qspi *q)
144 +{
145 + return q->devtype_data->driver_data & QUADSPI_AMBA_BASE_INTERNAL;
146 +}
147 +
148 +static u32 fsl_get_nor_vendor(struct spi_nor *nor)
149 +{
150 + u32 vendor_id;
151 +
152 + if (nor->vendor) {
153 + if (memcmp(nor->vendor, FLASH_VENDOR_SPANSION_FS,
154 + sizeof(FLASH_VENDOR_SPANSION_FS) - 1))
155 + vendor_id = SPANSION_S25FS_FAMILY;
156 + }
157 + return vendor_id;
158 +}
159 +
160 /*
161 * R/W functions for big- or little-endian registers:
162 * The qSPI controller's endian is independent of the CPU core's endian.
163 @@ -331,6 +366,31 @@ static u32 qspi_readl(struct fsl_qspi *q
164 return ioread32(addr);
165 }
166
167 +static inline u32 *u8tou32(u32 *dest, const u8 *src, size_t n)
168 +{
169 + size_t i;
170 + *dest = 0;
171 +
172 + n = n > 4 ? 4 : n;
173 + for (i = 0; i < n; i++)
174 + *dest |= *src++ << i * 8;
175 +
176 + return dest;
177 +
178 +}
179 +
180 +static inline u8 *u32tou8(u8 *dest, const u32 *src, size_t n)
181 +{
182 + size_t i;
183 + u8 *xdest = dest;
184 +
185 + n = n > 4 ? 4 : n;
186 + for (i = 0; i < n; i++)
187 + *xdest++ = *src >> i * 8;
188 +
189 + return dest;
190 +}
191 +
192 /*
193 * An IC bug makes us to re-arrange the 32-bit data.
194 * The following chips, such as IMX6SLX, have fixed this bug.
195 @@ -373,8 +433,15 @@ static void fsl_qspi_init_lut(struct fsl
196 void __iomem *base = q->iobase;
197 int rxfifo = q->devtype_data->rxfifo;
198 u32 lut_base;
199 - u8 cmd, addrlen, dummy;
200 int i;
201 + u32 vendor;
202 +
203 + struct spi_nor *nor = &q->nor[0];
204 + u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
205 + u8 read_op = nor->read_opcode;
206 + u8 read_dm = nor->read_dummy;
207 +
208 + vendor = fsl_get_nor_vendor(nor);
209
210 fsl_qspi_unlock_lut(q);
211
212 @@ -382,25 +449,51 @@ static void fsl_qspi_init_lut(struct fsl
213 for (i = 0; i < QUADSPI_LUT_NUM; i++)
214 qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
215
216 - /* Quad Read */
217 - lut_base = SEQID_QUAD_READ * 4;
218 -
219 - if (q->nor_size <= SZ_16M) {
220 - cmd = SPINOR_OP_READ_1_1_4;
221 - addrlen = ADDR24BIT;
222 - dummy = 8;
223 - } else {
224 - /* use the 4-byte address */
225 - cmd = SPINOR_OP_READ_1_1_4;
226 - addrlen = ADDR32BIT;
227 - dummy = 8;
228 - }
229 + /* Read */
230 + lut_base = SEQID_READ * 4;
231
232 - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
233 + if (nor->flash_read == SPI_NOR_FAST) {
234 + qspi_writel(q, LUT0(CMD, PAD1, read_op) |
235 + LUT1(ADDR, PAD1, addrlen),
236 + base + QUADSPI_LUT(lut_base));
237 + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
238 + LUT1(FSL_READ, PAD1, rxfifo),
239 + base + QUADSPI_LUT(lut_base + 1));
240 + } else if (nor->flash_read == SPI_NOR_QUAD) {
241 + if (q->nor_size == 0x4000000) {
242 + read_op = 0xEC;
243 + qspi_writel(q,
244 + LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD4, addrlen),
245 + base + QUADSPI_LUT(lut_base));
246 + qspi_writel(q,
247 + LUT0(MODE, PAD4, 0xff) | LUT1(DUMMY, PAD4, read_dm),
248 + base + QUADSPI_LUT(lut_base + 1));
249 + qspi_writel(q,
250 + LUT0(FSL_READ, PAD4, rxfifo),
251 + base + QUADSPI_LUT(lut_base + 2));
252 + } else {
253 + qspi_writel(q, LUT0(CMD, PAD1, read_op) |
254 + LUT1(ADDR, PAD1, addrlen),
255 + base + QUADSPI_LUT(lut_base));
256 + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
257 + LUT1(FSL_READ, PAD4, rxfifo),
258 + base + QUADSPI_LUT(lut_base + 1));
259 + }
260 + } else if (nor->flash_read == SPI_NOR_DDR_QUAD) {
261 + /* read mode : 1-4-4, such as Spansion s25fl128s. */
262 + qspi_writel(q, LUT0(CMD, PAD1, read_op)
263 + | LUT1(ADDR_DDR, PAD4, addrlen),
264 base + QUADSPI_LUT(lut_base));
265 - qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
266 +
267 + qspi_writel(q, LUT0(MODE_DDR, PAD4, 0xff)
268 + | LUT1(DUMMY, PAD1, read_dm),
269 base + QUADSPI_LUT(lut_base + 1));
270
271 + qspi_writel(q, LUT0(FSL_READ_DDR, PAD4, rxfifo)
272 + | LUT1(JMP_ON_CS, PAD1, 0),
273 + base + QUADSPI_LUT(lut_base + 2));
274 + }
275 +
276 /* Write enable */
277 lut_base = SEQID_WREN * 4;
278 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
279 @@ -409,16 +502,8 @@ static void fsl_qspi_init_lut(struct fsl
280 /* Page Program */
281 lut_base = SEQID_PP * 4;
282
283 - if (q->nor_size <= SZ_16M) {
284 - cmd = SPINOR_OP_PP;
285 - addrlen = ADDR24BIT;
286 - } else {
287 - /* use the 4-byte address */
288 - cmd = SPINOR_OP_PP;
289 - addrlen = ADDR32BIT;
290 - }
291 -
292 - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
293 + qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
294 + LUT1(ADDR, PAD1, addrlen),
295 base + QUADSPI_LUT(lut_base));
296 qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
297 base + QUADSPI_LUT(lut_base + 1));
298 @@ -432,10 +517,8 @@ static void fsl_qspi_init_lut(struct fsl
299 /* Erase a sector */
300 lut_base = SEQID_SE * 4;
301
302 - cmd = q->nor[0].erase_opcode;
303 - addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;
304 -
305 - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
306 + qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
307 + LUT1(ADDR, PAD1, addrlen),
308 base + QUADSPI_LUT(lut_base));
309
310 /* Erase the whole chip */
311 @@ -476,6 +559,44 @@ static void fsl_qspi_init_lut(struct fsl
312 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
313 base + QUADSPI_LUT(lut_base));
314
315 +
316 + /*
317 + * Flash Micron and Spansion command confilict
318 + * use the same value 0x65. But it indicates different meaning.
319 + */
320 + lut_base = SEQID_RDAR_OR_RD_EVCR * 4;
321 +
322 + if (vendor == SPANSION_S25FS_FAMILY) {
323 + /*
324 + * Read any device register.
325 + * Used for Spansion S25FS-S family flash only.
326 + */
327 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
328 + LUT1(ADDR, PAD1, ADDR24BIT),
329 + base + QUADSPI_LUT(lut_base));
330 + qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
331 + base + QUADSPI_LUT(lut_base + 1));
332 + } else {
333 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RD_EVCR),
334 + base + QUADSPI_LUT(lut_base));
335 + }
336 +
337 + /*
338 + * Write any device register.
339 + * Used for Spansion S25FS-S family flash only.
340 + */
341 + lut_base = SEQID_WRAR * 4;
342 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_WRAR) |
343 + LUT1(ADDR, PAD1, ADDR24BIT),
344 + base + QUADSPI_LUT(lut_base));
345 + qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1),
346 + base + QUADSPI_LUT(lut_base + 1));
347 +
348 + /* Write EVCR register */
349 + lut_base = SEQID_WD_EVCR * 4;
350 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WD_EVCR),
351 + base + QUADSPI_LUT(lut_base));
352 +
353 fsl_qspi_lock_lut(q);
354 }
355
356 @@ -483,8 +604,24 @@ static void fsl_qspi_init_lut(struct fsl
357 static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
358 {
359 switch (cmd) {
360 + case SPINOR_OP_READ_1_4_4_D:
361 + case SPINOR_OP_READ4_1_4_4_D:
362 + case SPINOR_OP_READ4_1_1_4:
363 case SPINOR_OP_READ_1_1_4:
364 - return SEQID_QUAD_READ;
365 + case SPINOR_OP_READ_FAST:
366 + case SPINOR_OP_READ4_FAST:
367 + return SEQID_READ;
368 + /*
369 + * Spansion & Micron use the same command value 0x65
370 + * Spansion: SPINOR_OP_SPANSION_RDAR, read any register.
371 + * Micron: SPINOR_OP_RD_EVCR,
372 + * read enhanced volatile configuration register.
373 + * case SPINOR_OP_RD_EVCR:
374 + */
375 + case SPINOR_OP_SPANSION_RDAR:
376 + return SEQID_RDAR_OR_RD_EVCR;
377 + case SPINOR_OP_SPANSION_WRAR:
378 + return SEQID_WRAR;
379 case SPINOR_OP_WREN:
380 return SEQID_WREN;
381 case SPINOR_OP_WRDI:
382 @@ -496,6 +633,7 @@ static int fsl_qspi_get_seqid(struct fsl
383 case SPINOR_OP_CHIP_ERASE:
384 return SEQID_CHIP_ERASE;
385 case SPINOR_OP_PP:
386 + case SPINOR_OP_PP_4B:
387 return SEQID_PP;
388 case SPINOR_OP_RDID:
389 return SEQID_RDID;
390 @@ -507,6 +645,8 @@ static int fsl_qspi_get_seqid(struct fsl
391 return SEQID_EN4B;
392 case SPINOR_OP_BRWR:
393 return SEQID_BRWR;
394 + case SPINOR_OP_WD_EVCR:
395 + return SEQID_WD_EVCR;
396 default:
397 if (cmd == q->nor[0].erase_opcode)
398 return SEQID_SE;
399 @@ -531,8 +671,11 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
400 /* save the reg */
401 reg = qspi_readl(q, base + QUADSPI_MCR);
402
403 - qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
404 - base + QUADSPI_SFAR);
405 + if (has_added_amba_base_internal(q))
406 + qspi_writel(q, q->chip_base_addr + addr, base + QUADSPI_SFAR);
407 + else
408 + qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
409 + base + QUADSPI_SFAR);
410 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
411 base + QUADSPI_RBCT);
412 qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
413 @@ -582,10 +725,10 @@ static void fsl_qspi_read_data(struct fs
414 q->chip_base_addr, tmp);
415
416 if (len >= 4) {
417 - *((u32 *)rxbuf) = tmp;
418 + u32tou8(rxbuf, &tmp, 4);
419 rxbuf += 4;
420 } else {
421 - memcpy(rxbuf, &tmp, len);
422 + u32tou8(rxbuf, &tmp, len);
423 break;
424 }
425
426 @@ -619,11 +762,12 @@ static inline void fsl_qspi_invalid(stru
427 }
428
429 static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
430 - u8 opcode, unsigned int to, u32 *txbuf,
431 + u8 opcode, unsigned int to, u8 *txbuf,
432 unsigned count)
433 {
434 int ret, i, j;
435 u32 tmp;
436 + u8 byts;
437
438 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
439 q->chip_base_addr, to, count);
440 @@ -633,10 +777,13 @@ static ssize_t fsl_qspi_nor_write(struct
441 qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
442
443 /* fill the TX data to the FIFO */
444 + byts = count;
445 for (j = 0, i = ((count + 3) / 4); j < i; j++) {
446 - tmp = fsl_qspi_endian_xchg(q, *txbuf);
447 + u8tou32(&tmp, txbuf, byts);
448 + tmp = fsl_qspi_endian_xchg(q, tmp);
449 qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
450 - txbuf++;
451 + txbuf += 4;
452 + byts -= 4;
453 }
454
455 /* fill the TXFIFO upto 16 bytes for i.MX7d */
456 @@ -657,11 +804,43 @@ static void fsl_qspi_set_map_addr(struct
457 {
458 int nor_size = q->nor_size;
459 void __iomem *base = q->iobase;
460 + u32 mem_base;
461 +
462 + if (has_added_amba_base_internal(q))
463 + mem_base = 0x0;
464 + else
465 + mem_base = q->memmap_phy;
466 +
467 + qspi_writel(q, nor_size + mem_base, base + QUADSPI_SFA1AD);
468 + qspi_writel(q, nor_size * 2 + mem_base, base + QUADSPI_SFA2AD);
469 + qspi_writel(q, nor_size * 3 + mem_base, base + QUADSPI_SFB1AD);
470 + qspi_writel(q, nor_size * 4 + mem_base, base + QUADSPI_SFB2AD);
471 +}
472 +
473 +/*
474 + * enable controller ddr quad mode to support different
475 + * vender flashes ddr quad mode.
476 + */
477 +static void set_ddr_quad_mode(struct fsl_qspi *q)
478 +{
479 + u32 reg, reg2;
480 +
481 + reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
482 +
483 + /* Firstly, disable the module */
484 + qspi_writel(q, reg | QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
485 +
486 + /* Set the Sampling Register for DDR */
487 + reg2 = qspi_readl(q, q->iobase + QUADSPI_SMPR);
488 + reg2 &= ~QUADSPI_SMPR_DDRSMP_MASK;
489 + reg2 |= (((q->ddr_smp) << QUADSPI_SMPR_DDRSMP_SHIFT) &
490 + QUADSPI_SMPR_DDRSMP_MASK);
491 + qspi_writel(q, reg2, q->iobase + QUADSPI_SMPR);
492 +
493 + /* Enable the module again (enable the DDR too) */
494 + reg |= QUADSPI_MCR_DDR_EN_MASK;
495 + qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
496
497 - qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
498 - qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
499 - qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
500 - qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
501 }
502
503 /*
504 @@ -681,19 +860,36 @@ static void fsl_qspi_init_abh_read(struc
505 {
506 void __iomem *base = q->iobase;
507 int seqid;
508 + const struct fsl_qspi_devtype_data *devtype_data = q->devtype_data;
509
510 /* AHB configuration for access buffer 0/1/2 .*/
511 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
512 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
513 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
514 +
515 /*
516 - * Set ADATSZ with the maximum AHB buffer size to improve the
517 - * read performance.
518 + * Errata: A-009282: QuadSPI data prefetch may result in incorrect data
519 + * Workaround: Keep the read data size to 64 bits (8 bytes).
520 + * This disables the prefetch on the AHB buffer and
521 + * prevents this issue from occurring.
522 */
523 - qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
524 - ((q->devtype_data->ahb_buf_size / 8)
525 - << QUADSPI_BUF3CR_ADATSZ_SHIFT),
526 - base + QUADSPI_BUF3CR);
527 + if (devtype_data->devtype == FSL_QUADSPI_LS2080A ||
528 + devtype_data->devtype == FSL_QUADSPI_LS1021A) {
529 +
530 + qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
531 + (1 << QUADSPI_BUF3CR_ADATSZ_SHIFT),
532 + base + QUADSPI_BUF3CR);
533 +
534 + } else {
535 + /*
536 + * Set ADATSZ with the maximum AHB buffer size to improve the
537 + * read performance.
538 + */
539 + qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
540 + ((q->devtype_data->ahb_buf_size / 8)
541 + << QUADSPI_BUF3CR_ADATSZ_SHIFT),
542 + base + QUADSPI_BUF3CR);
543 + }
544
545 /* We only use the buffer3 */
546 qspi_writel(q, 0, base + QUADSPI_BUF0IND);
547 @@ -704,6 +900,11 @@ static void fsl_qspi_init_abh_read(struc
548 seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
549 qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
550 q->iobase + QUADSPI_BFGENCR);
551 +
552 + /* enable the DDR quad read */
553 + if (q->nor->flash_read == SPI_NOR_DDR_QUAD)
554 + set_ddr_quad_mode(q);
555 +
556 }
557
558 /* This function was used to prepare and enable QSPI clock */
559 @@ -822,6 +1023,7 @@ static const struct of_device_id fsl_qsp
560 { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
561 { .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
562 { .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
563 + { .compatible = "fsl,ls2080a-qspi", .data = (void *)&ls2080a_data, },
564 { /* sentinel */ }
565 };
566 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
567 @@ -835,8 +1037,12 @@ static int fsl_qspi_read_reg(struct spi_
568 {
569 int ret;
570 struct fsl_qspi *q = nor->priv;
571 + u32 to = 0;
572 +
573 + if (opcode == SPINOR_OP_SPANSION_RDAR)
574 + u8tou32(&to, nor->cmd_buf, 4);
575
576 - ret = fsl_qspi_runcmd(q, opcode, 0, len);
577 + ret = fsl_qspi_runcmd(q, opcode, to, len);
578 if (ret)
579 return ret;
580
581 @@ -848,9 +1054,13 @@ static int fsl_qspi_write_reg(struct spi
582 {
583 struct fsl_qspi *q = nor->priv;
584 int ret;
585 + u32 to = 0;
586 +
587 + if (opcode == SPINOR_OP_SPANSION_WRAR)
588 + u8tou32(&to, nor->cmd_buf, 4);
589
590 if (!buf) {
591 - ret = fsl_qspi_runcmd(q, opcode, 0, 1);
592 + ret = fsl_qspi_runcmd(q, opcode, to, 1);
593 if (ret)
594 return ret;
595
596 @@ -859,7 +1069,7 @@ static int fsl_qspi_write_reg(struct spi
597
598 } else if (len > 0) {
599 ret = fsl_qspi_nor_write(q, nor, opcode, 0,
600 - (u32 *)buf, len);
601 + buf, len);
602 if (ret > 0)
603 return 0;
604 } else {
605 @@ -875,7 +1085,7 @@ static ssize_t fsl_qspi_write(struct spi
606 {
607 struct fsl_qspi *q = nor->priv;
608 ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
609 - (u32 *)buf, len);
610 + (u8 *)buf, len);
611
612 /* invalid the data in the AHB buffer. */
613 fsl_qspi_invalid(q);
614 @@ -922,7 +1132,7 @@ static ssize_t fsl_qspi_read(struct spi_
615 len);
616
617 /* Read out the data directly from the AHB buffer.*/
618 - memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
619 + memcpy_toio(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
620 len);
621
622 return len;
623 @@ -980,6 +1190,8 @@ static int fsl_qspi_probe(struct platfor
624 struct spi_nor *nor;
625 struct mtd_info *mtd;
626 int ret, i = 0;
627 + int find_node;
628 + enum read_mode mode = SPI_NOR_QUAD;
629
630 q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
631 if (!q)
632 @@ -1027,6 +1239,12 @@ static int fsl_qspi_probe(struct platfor
633 goto clk_failed;
634 }
635
636 + /* find ddrsmp value */
637 + ret = of_property_read_u32(dev->of_node, "fsl,ddr-sampling-point",
638 + &q->ddr_smp);
639 + if (ret)
640 + q->ddr_smp = 0;
641 +
642 /* find the irq */
643 ret = platform_get_irq(pdev, 0);
644 if (ret < 0) {
645 @@ -1050,6 +1268,7 @@ static int fsl_qspi_probe(struct platfor
646
647 mutex_init(&q->lock);
648
649 + find_node = 0;
650 /* iterate the subnodes. */
651 for_each_available_child_of_node(dev->of_node, np) {
652 /* skip the holes */
653 @@ -1076,18 +1295,25 @@ static int fsl_qspi_probe(struct platfor
654 ret = of_property_read_u32(np, "spi-max-frequency",
655 &q->clk_rate);
656 if (ret < 0)
657 - goto mutex_failed;
658 + continue;
659
660 /* set the chip address for READID */
661 fsl_qspi_set_base_addr(q, nor);
662
663 - ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD);
664 + ret = of_property_read_bool(np, "m25p,fast-read");
665 + mode = (ret) ? SPI_NOR_FAST : SPI_NOR_QUAD;
666 + /* Can we enable the DDR Quad Read? */
667 + ret = of_property_read_bool(np, "ddr-quad-read");
668 if (ret)
669 - goto mutex_failed;
670 + mode = SPI_NOR_DDR_QUAD;
671 +
672 + ret = spi_nor_scan(nor, NULL, mode);
673 + if (ret)
674 + continue;
675
676 ret = mtd_device_register(mtd, NULL, 0);
677 if (ret)
678 - goto mutex_failed;
679 + continue;
680
681 /* Set the correct NOR size now. */
682 if (q->nor_size == 0) {
683 @@ -1110,8 +1336,12 @@ static int fsl_qspi_probe(struct platfor
684 nor->page_size = q->devtype_data->txfifo;
685
686 i++;
687 + find_node++;
688 }
689
690 + if (find_node == 0)
691 + goto mutex_failed;
692 +
693 /* finish the rest init. */
694 ret = fsl_qspi_nor_setup_last(q);
695 if (ret)
696 --- a/drivers/mtd/spi-nor/spi-nor.c
697 +++ b/drivers/mtd/spi-nor/spi-nor.c
698 @@ -40,6 +40,13 @@
699 #define SPI_NOR_MAX_ID_LEN 6
700 #define SPI_NOR_MAX_ADDR_WIDTH 4
701
702 +#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f
703 +/* Added for S25FS-S family flash */
704 +#define SPINOR_CONFIG_REG3_OFFSET 0x800004
705 +#define CR3V_4KB_ERASE_UNABLE 0x8
706 +#define SPINOR_S25FS_FAMILY_ID 0x81
707 +
708 +
709 struct flash_info {
710 char *name;
711
712 @@ -68,7 +75,8 @@ struct flash_info {
713 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
714 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
715 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
716 -#define USE_FSR BIT(7) /* use flag status register */
717 +#define USE_FSR BIT(13) /* use flag status register */
718 +#define SPI_NOR_DDR_QUAD_READ BIT(7) /* Flash supports DDR Quad Read */
719 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
720 #define SPI_NOR_HAS_TB BIT(9) /*
721 * Flash SR has Top/Bottom (TB) protect
722 @@ -85,9 +93,11 @@ struct flash_info {
723 * Use dedicated 4byte address op codes
724 * to support memory size above 128Mib.
725 */
726 +#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
727 };
728
729 #define JEDEC_MFR(info) ((info)->id[0])
730 +#define EXT_ID(info) ((info)->id[5])
731
732 static const struct flash_info *spi_nor_match_id(const char *name);
733
734 @@ -132,7 +142,7 @@ static int read_fsr(struct spi_nor *nor)
735 /*
736 * Read configuration register, returning its value in the
737 * location. Return the configuration register value.
738 - * Returns negative if error occured.
739 + * Returns negative if error occurred.
740 */
741 static int read_cr(struct spi_nor *nor)
742 {
743 @@ -160,6 +170,8 @@ static inline int spi_nor_read_dummy_cyc
744 case SPI_NOR_DUAL:
745 case SPI_NOR_QUAD:
746 return 8;
747 + case SPI_NOR_DDR_QUAD:
748 + return 6;
749 case SPI_NOR_NORMAL:
750 return 0;
751 }
752 @@ -961,6 +973,8 @@ static const struct flash_info spi_nor_i
753
754 /* ESMT */
755 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
756 + { "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
757 + { "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) },
758
759 /* Everspin */
760 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
761 @@ -1014,12 +1028,15 @@ static const struct flash_info spi_nor_i
762 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
763 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
764 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
765 + { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
766 + { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
767 + { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
768 { "mx25u3235f", INFO(0xc22536, 0, 64 * 1024, 64, 0) },
769 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
770 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
771 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
772 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
773 - { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
774 + { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K) },
775 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
776 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
777 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
778 @@ -1033,10 +1050,11 @@ static const struct flash_info spi_nor_i
779 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
780 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
781 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
782 + { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
783 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
784 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
785 - { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
786 - { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
787 + { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
788 + { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
789
790 /* PMC */
791 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
792 @@ -1054,8 +1072,11 @@ static const struct flash_info spi_nor_i
793 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
794 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
795 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
796 - { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
797 + { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, 0)},
798 + { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ
799 + | SPI_NOR_DDR_QUAD_READ) },
800 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
801 + { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)},
802 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
803 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
804 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
805 @@ -1130,6 +1151,9 @@ static const struct flash_info spi_nor_i
806 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
807 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
808 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
809 + { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
810 + { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
811 + { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
812 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
813 {
814 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
815 @@ -1192,6 +1216,53 @@ static const struct flash_info *spi_nor_
816 id[0], id[1], id[2]);
817 return ERR_PTR(-ENODEV);
818 }
819 +/*
820 + * The S25FS-S family physical sectors may be configured as a
821 + * hybrid combination of eight 4-kB parameter sectors
822 + * at the top or bottom of the address space with all
823 + * but one of the remaining sectors being uniform size.
824 + * The Parameter Sector Erase commands (20h or 21h) must
825 + * be used to erase the 4-kB parameter sectors individually.
826 + * The Sector (uniform sector) Erase commands (D8h or DCh)
827 + * must be used to erase any of the remaining
828 + * sectors, including the portion of highest or lowest address
829 + * sector that is not overlaid by the parameter sectors.
830 + * The uniform sector erase command has no effect on parameter sectors.
831 + */
832 +static int spansion_s25fs_disable_4kb_erase(struct spi_nor *nor)
833 +{
834 + struct fsl_qspi *q;
835 + u32 cr3v_addr = SPINOR_CONFIG_REG3_OFFSET;
836 + u8 cr3v = 0x0;
837 + int ret = 0x0;
838 +
839 + q = nor->priv;
840 +
841 + nor->cmd_buf[2] = cr3v_addr >> 16;
842 + nor->cmd_buf[1] = cr3v_addr >> 8;
843 + nor->cmd_buf[0] = cr3v_addr >> 0;
844 +
845 + ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
846 + if (ret)
847 + return ret;
848 + if (cr3v & CR3V_4KB_ERASE_UNABLE)
849 + return 0;
850 + ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
851 + if (ret)
852 + return ret;
853 + cr3v = CR3V_4KB_ERASE_UNABLE;
854 + nor->program_opcode = SPINOR_OP_SPANSION_WRAR;
855 + nor->write(nor, cr3v_addr, 1, &cr3v);
856 +
857 + ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
858 + if (ret)
859 + return ret;
860 + if (!(cr3v & CR3V_4KB_ERASE_UNABLE))
861 + return -EPERM;
862 +
863 + return 0;
864 +}
865 +
866
867 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
868 size_t *retlen, u_char *buf)
869 @@ -1411,7 +1482,7 @@ static int macronix_quad_enable(struct s
870 * Write status Register and configuration register with 2 bytes
871 * The first byte will be written to the status register, while the
872 * second byte will be written to the configuration register.
873 - * Return negative if error occured.
874 + * Return negative if error occurred.
875 */
876 static int write_sr_cr(struct spi_nor *nor, u16 val)
877 {
878 @@ -1459,6 +1530,24 @@ static int spansion_quad_enable(struct s
879 return 0;
880 }
881
882 +static int set_ddr_quad_mode(struct spi_nor *nor, const struct flash_info *info)
883 +{
884 + int status;
885 +
886 + switch (JEDEC_MFR(info)) {
887 + case SNOR_MFR_SPANSION:
888 + status = spansion_quad_enable(nor);
889 + if (status) {
890 + dev_err(nor->dev, "Spansion DDR quad-read not enabled\n");
891 + return status;
892 + }
893 + return status;
894 + default:
895 + return -EINVAL;
896 + }
897 +}
898 +
899 +
900 static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
901 {
902 int status;
903 @@ -1604,9 +1693,25 @@ int spi_nor_scan(struct spi_nor *nor, co
904 write_sr(nor, 0);
905 spi_nor_wait_till_ready(nor);
906 }
907 + if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
908 + ret = read_sr(nor);
909 + ret &= SPI_NOR_MICRON_WRITE_ENABLE;
910 +
911 + write_enable(nor);
912 + write_sr(nor, ret);
913 + }
914 +
915 + if (EXT_ID(info) == SPINOR_S25FS_FAMILY_ID) {
916 + ret = spansion_s25fs_disable_4kb_erase(nor);
917 + if (ret)
918 + return ret;
919 + }
920 +
921
922 if (!mtd->name)
923 mtd->name = dev_name(dev);
924 + if (info->name)
925 + nor->vendor = info->name;
926 mtd->priv = nor;
927 mtd->type = MTD_NORFLASH;
928 mtd->writesize = 1;
929 @@ -1639,6 +1744,8 @@ int spi_nor_scan(struct spi_nor *nor, co
930 nor->flags |= SNOR_F_USE_FSR;
931 if (info->flags & SPI_NOR_HAS_TB)
932 nor->flags |= SNOR_F_HAS_SR_TB;
933 + if (info->flags & NO_CHIP_ERASE)
934 + nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
935
936 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
937 /* prefer "small sector" erase if possible */
938 @@ -1676,9 +1783,15 @@ int spi_nor_scan(struct spi_nor *nor, co
939 /* Some devices cannot do fast-read, no matter what DT tells us */
940 if (info->flags & SPI_NOR_NO_FR)
941 nor->flash_read = SPI_NOR_NORMAL;
942 -
943 - /* Quad/Dual-read mode takes precedence over fast/normal */
944 - if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
945 + /* DDR Quad/Quad/Dual-read mode takes precedence over fast/normal */
946 + if (mode == SPI_NOR_DDR_QUAD && info->flags & SPI_NOR_DDR_QUAD_READ) {
947 + ret = set_ddr_quad_mode(nor, info);
948 + if (ret) {
949 + dev_err(dev, "DDR quad mode not supported\n");
950 + return ret;
951 + }
952 + nor->flash_read = SPI_NOR_DDR_QUAD;
953 + } else if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
954 ret = set_quad_mode(nor, info);
955 if (ret) {
956 dev_err(dev, "quad mode not supported\n");
957 @@ -1691,6 +1804,9 @@ int spi_nor_scan(struct spi_nor *nor, co
958
959 /* Default commands */
960 switch (nor->flash_read) {
961 + case SPI_NOR_DDR_QUAD:
962 + nor->read_opcode = SPINOR_OP_READ4_1_4_4_D;
963 + break;
964 case SPI_NOR_QUAD:
965 nor->read_opcode = SPINOR_OP_READ_1_1_4;
966 break;
967 --- a/include/linux/mtd/spi-nor.h
968 +++ b/include/linux/mtd/spi-nor.h
969 @@ -31,10 +31,10 @@
970
971 /*
972 * Note on opcode nomenclature: some opcodes have a format like
973 - * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
974 + * SPINOR_OP_FUNCTION{4,}_x_y_z{_D}. The numbers x, y,and z stand for the number
975 * of I/O lines used for the opcode, address, and data (respectively). The
976 * FUNCTION has an optional suffix of '4', to represent an opcode which
977 - * requires a 4-byte (32-bit) address.
978 + * requires a 4-byte (32-bit) address. The suffix of 'D' stands for the
979 */
980
981 /* Flash opcodes. */
982 @@ -46,7 +46,9 @@
983 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
984 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
985 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
986 +#define SPINOR_OP_READ_1_4_4_D 0xed /* Read data bytes (DDR Quad SPI) */
987 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
988 +#define SPINOR_OP_READ4_1_4_4_D 0xee /* Read data bytes (DDR Quad SPI) */
989 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
990 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
991 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
992 @@ -62,9 +64,11 @@
993 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
994 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
995 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
996 +#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
997 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
998 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
999 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
1000 +#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
1001 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
1002 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
1003 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
1004 @@ -94,6 +98,10 @@
1005 /* Used for Spansion flashes only. */
1006 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
1007
1008 +/* Used for Spansion S25FS-S family flash only. */
1009 +#define SPINOR_OP_SPANSION_RDAR 0x65 /* Read any device register */
1010 +#define SPINOR_OP_SPANSION_WRAR 0x71 /* Write any device register */
1011 +
1012 /* Used for Micron flashes only. */
1013 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
1014 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
1015 @@ -124,6 +132,7 @@ enum read_mode {
1016 SPI_NOR_FAST,
1017 SPI_NOR_DUAL,
1018 SPI_NOR_QUAD,
1019 + SPI_NOR_DDR_QUAD,
1020 };
1021
1022 #define SPI_NOR_MAX_CMD_SIZE 8
1023 @@ -189,6 +198,7 @@ struct spi_nor {
1024 bool sst_write_second;
1025 u32 flags;
1026 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
1027 + char *vendor;
1028
1029 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
1030 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
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