target/linux/ipq807x/patches-5.15/0019-v6.0-arm64-dts-qcom-Fix-ordering-of-clocks-clock-names-fo.patch

   1 From 18363f691e931abf0e9bdc9b5169fb15aa10224d Mon Sep 17 00:00:00 2001
   2 From: Bhupesh Sharma <bhupesh.sharma@linaro.org>
   3 Date: Sun, 15 May 2022 03:24:22 +0530
   4 Subject: [PATCH] arm64: dts: qcom: Fix ordering of 'clocks' & 'clock-names'
   5  for sdhci nodes
   6
   7 Since the Qualcomm sdhci-msm device-tree binding has been converted
   8 to yaml format, 'make dtbs_check' reports a number of issues with
   9 ordering of 'clocks' & 'clock-names' for sdhci nodes:
  10
  11  arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
  12   clock-names:0: 'iface' was expected
  13
  14  arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
  15   clock-names:1: 'core' was expected
  16
  17  arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
  18   clock-names:2: 'xo' was expected
  19
  20 Fix the same by updating the offending 'dts' files.
  21
  22 Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
  23 Cc: Rob Herring <robh@kernel.org>
  24 Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
  25 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  26 Link: https://lore.kernel.org/r/20220514215424.1007718-5-bhupesh.sharma@linaro.org
  27 ---
  28  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++----
  29  1 file changed, 4 insertions(+), 4 deletions(-)
  30
  31 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  32 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  33 @@ -384,10 +384,10 @@
  34                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
  35                         interrupt-names = "hc_irq", "pwr_irq";
  36
  37 -                       clocks = <&xo>,
  38 -                                <&gcc GCC_SDCC1_AHB_CLK>,
  39 -                                <&gcc GCC_SDCC1_APPS_CLK>;
  40 -                       clock-names = "xo", "iface", "core";
  41 +                       clocks = <&gcc GCC_SDCC1_AHB_CLK>,
  42 +                                <&gcc GCC_SDCC1_APPS_CLK>,
  43 +                                <&xo>;
  44 +                       clock-names = "iface", "core", "xo";
  45                         max-frequency = <384000000>;
  46                         mmc-ddr-1_8v;
  47                         mmc-hs200-1_8v;