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kernel: bump 5.10 to 5.10.35
[openwrt/staging/hauke.git] / target / linux / ipq806x / patches-5.10 / 083-ipq8064-dtsi-additions.patch
1 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
2 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
3 @@ -8,6 +8,8 @@
4 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/soc/qcom,gsbi.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 +#include <dt-bindings/mfd/qcom-rpm.h>
8 +#include <dt-bindings/clock/qcom,rpmcc.h>
9
10 / {
11 #address-cells = <1>;
12 @@ -28,6 +30,16 @@
13 next-level-cache = <&L2>;
14 qcom,acc = <&acc0>;
15 qcom,saw = <&saw0>;
16 + clocks = <&kraitcc 0>, <&kraitcc 4>;
17 + clock-names = "cpu", "l2";
18 + clock-latency = <100000>;
19 + cpu-supply = <&smb208_s2a>;
20 + operating-points-v2 = <&opp_table0>;
21 + voltage-tolerance = <5>;
22 + cooling-min-state = <0>;
23 + cooling-max-state = <10>;
24 + #cooling-cells = <2>;
25 + cpu-idle-states = <&CPU_SPC>;
26 };
27
28 cpu1: cpu@1 {
29 @@ -38,14 +50,347 @@
30 next-level-cache = <&L2>;
31 qcom,acc = <&acc1>;
32 qcom,saw = <&saw1>;
33 + clocks = <&kraitcc 1>, <&kraitcc 4>;
34 + clock-names = "cpu", "l2";
35 + clock-latency = <100000>;
36 + cpu-supply = <&smb208_s2b>;
37 + operating-points-v2 = <&opp_table0>;
38 + voltage-tolerance = <5>;
39 + cooling-min-state = <0>;
40 + cooling-max-state = <10>;
41 + #cooling-cells = <2>;
42 + cpu-idle-states = <&CPU_SPC>;
43 + };
44 +
45 + idle-states {
46 + CPU_SPC: spc {
47 + compatible = "qcom,idle-state-spc";
48 + status = "disabled";
49 + entry-latency-us = <400>;
50 + exit-latency-us = <900>;
51 + min-residency-us = <3000>;
52 + };
53 };
54 + };
55
56 - L2: l2-cache {
57 - compatible = "cache";
58 - cache-level = <2>;
59 + opp_table_l2: opp_table_l2 {
60 + compatible = "operating-points-v2";
61 +
62 + opp-384000000 {
63 + opp-hz = /bits/ 64 <384000000>;
64 + opp-microvolt = <1100000>;
65 + clock-latency-ns = <100000>;
66 + opp-level = <0>;
67 + };
68 +
69 + opp-1000000000 {
70 + opp-hz = /bits/ 64 <1000000000>;
71 + opp-microvolt = <1100000>;
72 + clock-latency-ns = <100000>;
73 + opp-level = <1>;
74 + };
75 +
76 + opp-1200000000 {
77 + opp-hz = /bits/ 64 <1200000000>;
78 + opp-microvolt = <1150000>;
79 + clock-latency-ns = <100000>;
80 + opp-level = <2>;
81 };
82 };
83
84 + opp_table0: opp_table0 {
85 + compatible = "operating-points-v2-kryo-cpu";
86 + nvmem-cells = <&speedbin_efuse>;
87 +
88 + opp-384000000 {
89 + opp-hz = /bits/ 64 <384000000>;
90 + opp-microvolt-speed0-pvs0-v0 = <950000 1000000 1050000>;
91 + opp-microvolt-speed0-pvs1-v0 = <878750 925000 971250>;
92 + opp-microvolt-speed0-pvs2-v0 = <831250 875000 918750>;
93 + opp-microvolt-speed0-pvs3-v0 = <760000 800000 840000>;
94 + opp-supported-hw = <0x1>;
95 + clock-latency-ns = <100000>;
96 + opp-level = <0>;
97 + };
98 +
99 + opp-600000000 {
100 + opp-hz = /bits/ 64 <600000000>;
101 + opp-microvolt-speed0-pvs0-v0 = <997500 1050000 1102500>;
102 + opp-microvolt-speed0-pvs1-v0 = <926250 975000 1023750>;
103 + opp-microvolt-speed0-pvs2-v0 = <878750 925000 971250>;
104 + opp-microvolt-speed0-pvs3-v0 = <807500 850000 892500>;
105 + opp-supported-hw = <0x1>;
106 + clock-latency-ns = <100000>;
107 + opp-level = <1>;
108 + };
109 +
110 + opp-800000000 {
111 + opp-hz = /bits/ 64 <800000000>;
112 + opp-microvolt-speed0-pvs0-v0 = <1045000 1100000 1155000>;
113 + opp-microvolt-speed0-pvs1-v0 = <973750 1025000 1076250>;
114 + opp-microvolt-speed0-pvs2-v0 = <945250 995000 1044750>;
115 + opp-microvolt-speed0-pvs3-v0 = <855000 900000 945000>;
116 + opp-supported-hw = <0x1>;
117 + clock-latency-ns = <100000>;
118 + opp-level = <1>;
119 + };
120 +
121 + opp-1000000000 {
122 + opp-hz = /bits/ 64 <1000000000>;
123 + opp-microvolt-speed0-pvs0-v0 = <1092500 1150000 1207500>;
124 + opp-microvolt-speed0-pvs1-v0 = <1021250 1075000 1128750>;
125 + opp-microvolt-speed0-pvs2-v0 = <973750 1025000 1076250>;
126 + opp-microvolt-speed0-pvs3-v0 = <902500 950000 997500>;
127 + opp-supported-hw = <0x1>;
128 + clock-latency-ns = <100000>;
129 + opp-level = <1>;
130 + };
131 +
132 + opp-1200000000 {
133 + opp-hz = /bits/ 64 <1200000000>;
134 + opp-microvolt-speed0-pvs0-v0 = <1140000 1200000 1260000>;
135 + opp-microvolt-speed0-pvs1-v0 = <1068750 1125000 1181250>;
136 + opp-microvolt-speed0-pvs2-v0 = <1021250 1075000 1128750>;
137 + opp-microvolt-speed0-pvs3-v0 = <950000 1000000 1050000>;
138 + opp-supported-hw = <0x1>;
139 + clock-latency-ns = <100000>;
140 + opp-level = <2>;
141 + };
142 +
143 + opp-1400000000 {
144 + opp-hz = /bits/ 64 <1400000000>;
145 + opp-microvolt-speed0-pvs0-v0 = <1187500 1250000 1312500>;
146 + opp-microvolt-speed0-pvs1-v0 = <1116250 1175000 1233750>;
147 + opp-microvolt-speed0-pvs2-v0 = <1068750 1125000 1181250>;
148 + opp-microvolt-speed0-pvs3-v0 = <997500 1050000 1102500>;
149 + opp-supported-hw = <0x1>;
150 + clock-latency-ns = <100000>;
151 + opp-level = <2>;
152 + };
153 + };
154 +
155 + thermal-zones {
156 + tsens_tz_sensor0 {
157 + polling-delay-passive = <0>;
158 + polling-delay = <0>;
159 + thermal-sensors = <&tsens 0>;
160 +
161 + trips {
162 + cpu-critical {
163 + temperature = <105000>;
164 + hysteresis = <2000>;
165 + type = "critical";
166 + };
167 +
168 + cpu-hot {
169 + temperature = <95000>;
170 + hysteresis = <2000>;
171 + type = "hot";
172 + };
173 + };
174 + };
175 +
176 + tsens_tz_sensor1 {
177 + polling-delay-passive = <0>;
178 + polling-delay = <0>;
179 + thermal-sensors = <&tsens 1>;
180 +
181 + trips {
182 + cpu-critical {
183 + temperature = <105000>;
184 + hysteresis = <2000>;
185 + type = "critical";
186 + };
187 +
188 + cpu-hot {
189 + temperature = <95000>;
190 + hysteresis = <2000>;
191 + type = "hot";
192 + };
193 + };
194 + };
195 +
196 + tsens_tz_sensor2 {
197 + polling-delay-passive = <0>;
198 + polling-delay = <0>;
199 + thermal-sensors = <&tsens 2>;
200 +
201 + trips {
202 + cpu-critical {
203 + temperature = <105000>;
204 + hysteresis = <2000>;
205 + type = "critical";
206 + };
207 +
208 + cpu-hot {
209 + temperature = <95000>;
210 + hysteresis = <2000>;
211 + type = "hot";
212 + };
213 + };
214 + };
215 +
216 + tsens_tz_sensor3 {
217 + polling-delay-passive = <0>;
218 + polling-delay = <0>;
219 + thermal-sensors = <&tsens 3>;
220 +
221 + trips {
222 + cpu-critical {
223 + temperature = <105000>;
224 + hysteresis = <2000>;
225 + type = "critical";
226 + };
227 +
228 + cpu-hot {
229 + temperature = <95000>;
230 + hysteresis = <2000>;
231 + type = "hot";
232 + };
233 + };
234 + };
235 +
236 + tsens_tz_sensor4 {
237 + polling-delay-passive = <0>;
238 + polling-delay = <0>;
239 + thermal-sensors = <&tsens 4>;
240 +
241 + trips {
242 + cpu-critical {
243 + temperature = <105000>;
244 + hysteresis = <2000>;
245 + type = "critical";
246 + };
247 +
248 + cpu-hot {
249 + temperature = <95000>;
250 + hysteresis = <2000>;
251 + type = "hot";
252 + };
253 + };
254 + };
255 +
256 + tsens_tz_sensor5 {
257 + polling-delay-passive = <0>;
258 + polling-delay = <0>;
259 + thermal-sensors = <&tsens 5>;
260 +
261 + trips {
262 + cpu-critical {
263 + temperature = <105000>;
264 + hysteresis = <2000>;
265 + type = "critical";
266 + };
267 +
268 + cpu-hot {
269 + temperature = <95000>;
270 + hysteresis = <2000>;
271 + type = "hot";
272 + };
273 + };
274 + };
275 +
276 + tsens_tz_sensor6 {
277 + polling-delay-passive = <0>;
278 + polling-delay = <0>;
279 + thermal-sensors = <&tsens 6>;
280 +
281 + trips {
282 + cpu-critical {
283 + temperature = <105000>;
284 + hysteresis = <2000>;
285 + type = "critical";
286 + };
287 +
288 + cpu-hot {
289 + temperature = <95000>;
290 + hysteresis = <2000>;
291 + type = "hot";
292 + };
293 + };
294 + };
295 +
296 + tsens_tz_sensor7 {
297 + polling-delay-passive = <0>;
298 + polling-delay = <0>;
299 + thermal-sensors = <&tsens 7>;
300 +
301 + trips {
302 + cpu-critical {
303 + temperature = <105000>;
304 + hysteresis = <2000>;
305 + type = "critical";
306 + };
307 +
308 + cpu-hot {
309 + temperature = <95000>;
310 + hysteresis = <2000>;
311 + type = "hot";
312 + };
313 + };
314 + };
315 +
316 + tsens_tz_sensor8 {
317 + polling-delay-passive = <0>;
318 + polling-delay = <0>;
319 + thermal-sensors = <&tsens 8>;
320 +
321 + trips {
322 + cpu-critical {
323 + temperature = <105000>;
324 + hysteresis = <2000>;
325 + type = "critical";
326 + };
327 +
328 + cpu-hot {
329 + temperature = <95000>;
330 + hysteresis = <2000>;
331 + type = "hot";
332 + };
333 + };
334 + };
335 +
336 + tsens_tz_sensor9 {
337 + polling-delay-passive = <0>;
338 + polling-delay = <0>;
339 + thermal-sensors = <&tsens 9>;
340 +
341 + trips {
342 + cpu-critical {
343 + temperature = <105000>;
344 + hysteresis = <2000>;
345 + type = "critical";
346 + };
347 +
348 + cpu-hot {
349 + temperature = <95000>;
350 + hysteresis = <2000>;
351 + type = "hot";
352 + };
353 + };
354 + };
355 +
356 + tsens_tz_sensor10 {
357 + polling-delay-passive = <0>;
358 + polling-delay = <0>;
359 + thermal-sensors = <&tsens 10>;
360 +
361 + trips {
362 + cpu-critical {
363 + temperature = <105000>;
364 + hysteresis = <2000>;
365 + type = "critical";
366 + };
367 +
368 + cpu-hot {
369 + temperature = <95000>;
370 + hysteresis = <2000>;
371 + type = "hot";
372 + };
373 + };
374 + };
375 + };
376 +
377 memory {
378 device_type = "memory";
379 reg = <0x0 0x0>;
380 @@ -93,6 +438,15 @@
381 };
382 };
383
384 + fab-scaling {
385 + compatible = "qcom,fab-scaling";
386 + clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
387 + clock-names = "apps-fab-clk", "ddr-fab-clk";
388 + fab_freq_high = <533000000>;
389 + fab_freq_nominal = <400000000>;
390 + cpu_freq_threshold = <1000000000>;
391 + };
392 +
393 firmware {
394 scm {
395 compatible = "qcom,scm-ipq806x", "qcom,scm";
396 @@ -120,6 +474,78 @@
397 reg-names = "lpass-lpaif";
398 };
399
400 + L2: l2-cache {
401 + compatible = "qcom,krait-cache", "cache";
402 + cache-level = <2>;
403 + qcom,saw = <&saw_l2>;
404 +
405 + clocks = <&kraitcc 4>;
406 + clock-names = "l2";
407 + l2-supply = <&smb208_s1a>;
408 + operating-points-v2 = <&opp_table_l2>;
409 + };
410 +
411 + rpm: rpm@108000 {
412 + compatible = "qcom,rpm-ipq8064";
413 + reg = <0x108000 0x1000>;
414 + qcom,ipc = <&l2cc 0x8 2>;
415 +
416 + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
417 + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
418 + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
419 + interrupt-names = "ack", "err", "wakeup";
420 +
421 + clocks = <&gcc RPM_MSG_RAM_H_CLK>;
422 + clock-names = "ram";
423 +
424 + #address-cells = <1>;
425 + #size-cells = <0>;
426 +
427 + rpmcc: clock-controller {
428 + compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
429 + #clock-cells = <1>;
430 + };
431 +
432 + regulators {
433 + compatible = "qcom,rpm-smb208-regulators";
434 +
435 + smb208_s1a: s1a {
436 + regulator-min-microvolt = <1050000>;
437 + regulator-max-microvolt = <1150000>;
438 +
439 + qcom,switch-mode-frequency = <1200000>;
440 + };
441 +
442 + smb208_s1b: s1b {
443 + regulator-min-microvolt = <1050000>;
444 + regulator-max-microvolt = <1150000>;
445 +
446 + qcom,switch-mode-frequency = <1200000>;
447 + };
448 +
449 + smb208_s2a: s2a {
450 + regulator-min-microvolt = < 800000>;
451 + regulator-max-microvolt = <1250000>;
452 +
453 + qcom,switch-mode-frequency = <1200000>;
454 + };
455 +
456 + smb208_s2b: s2b {
457 + regulator-min-microvolt = < 800000>;
458 + regulator-max-microvolt = <1250000>;
459 +
460 + qcom,switch-mode-frequency = <1200000>;
461 + };
462 + };
463 + };
464 +
465 + rng@1a500000 {
466 + compatible = "qcom,prng";
467 + reg = <0x1a500000 0x200>;
468 + clocks = <&gcc PRNG_CLK>;
469 + clock-names = "core";
470 + };
471 +
472 qcom_pinmux: pinmux@800000 {
473 compatible = "qcom,ipq8064-pinctrl";
474 reg = <0x800000 0x4000>;
475 @@ -160,6 +586,15 @@
476 };
477 };
478
479 + i2c4_pins: i2c4_pinmux {
480 + mux {
481 + pins = "gpio12", "gpio13";
482 + function = "gsbi4";
483 + drive-strength = <12>;
484 + bias-disable;
485 + };
486 + };
487 +
488 spi_pins: spi_pins {
489 mux {
490 pins = "gpio18", "gpio19", "gpio21";
491 @@ -169,6 +604,53 @@
492 };
493 };
494
495 + nand_pins: nand_pins {
496 + disable {
497 + pins = "gpio34", "gpio35", "gpio36",
498 + "gpio37", "gpio38";
499 + function = "nand";
500 + drive-strength = <10>;
501 + bias-disable;
502 + };
503 +
504 + pullups {
505 + pins = "gpio39";
506 + function = "nand";
507 + drive-strength = <10>;
508 + bias-pull-up;
509 + };
510 +
511 + hold {
512 + pins = "gpio40", "gpio41", "gpio42",
513 + "gpio43", "gpio44", "gpio45",
514 + "gpio46", "gpio47";
515 + function = "nand";
516 + drive-strength = <10>;
517 + bias-bus-hold;
518 + };
519 + };
520 +
521 + mdio0_pins: mdio0_pins {
522 + mux {
523 + pins = "gpio0", "gpio1";
524 + function = "mdio";
525 + drive-strength = <8>;
526 + bias-disable;
527 + };
528 + };
529 +
530 + rgmii2_pins: rgmii2_pins {
531 + mux {
532 + pins = "gpio27", "gpio28", "gpio29",
533 + "gpio30", "gpio31", "gpio32",
534 + "gpio51", "gpio52", "gpio59",
535 + "gpio60", "gpio61", "gpio62";
536 + function = "rgmii2";
537 + drive-strength = <8>;
538 + bias-disable;
539 + };
540 + };
541 +
542 leds_pins: leds_pins {
543 mux {
544 pins = "gpio7", "gpio8", "gpio9",
545 @@ -231,6 +713,17 @@
546 clock-output-names = "acpu1_aux";
547 };
548
549 + l2cc: clock-controller@2011000 {
550 + compatible = "qcom,kpss-gcc", "syscon";
551 + reg = <0x2011000 0x1000>;
552 + clock-output-names = "acpu_l2_aux";
553 + };
554 +
555 + kraitcc: clock-controller {
556 + compatible = "qcom,krait-cc-v1";
557 + #clock-cells = <1>;
558 + };
559 +
560 saw0: regulator@2089000 {
561 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
562 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
563 @@ -243,6 +736,17 @@
564 regulator;
565 };
566
567 + saw_l2: regulator@02012000 {
568 + compatible = "qcom,saw2", "syscon";
569 + reg = <0x02012000 0x1000>;
570 + regulator;
571 + };
572 +
573 + sic_non_secure: sic-non-secure@12100000 {
574 + compatible = "syscon";
575 + reg = <0x12100000 0x10000>;
576 + };
577 +
578 gsbi2: gsbi@12480000 {
579 compatible = "qcom,gsbi-v1.0.0";
580 cell-index = <2>;
581 @@ -478,6 +982,95 @@
582 #reset-cells = <1>;
583 };
584
585 + sfpb_mutex_block: syscon@1200600 {
586 + compatible = "syscon";
587 + reg = <0x01200600 0x100>;
588 + };
589 +
590 + hs_phy_0: hs_phy_0 {
591 + compatible = "qcom,ipq806x-usb-phy-hs";
592 + reg = <0x110f8800 0x30>;
593 + clocks = <&gcc USB30_0_UTMI_CLK>;
594 + clock-names = "ref";
595 + #phy-cells = <0>;
596 + };
597 +
598 + ss_phy_0: ss_phy_0 {
599 + compatible = "qcom,ipq806x-usb-phy-ss";
600 + reg = <0x110f8830 0x30>;
601 + clocks = <&gcc USB30_0_MASTER_CLK>;
602 + clock-names = "ref";
603 + #phy-cells = <0>;
604 + };
605 +
606 + usb3_0: usb3@110f8800 {
607 + compatible = "qcom,dwc3", "syscon";
608 + #address-cells = <1>;
609 + #size-cells = <1>;
610 + reg = <0x110f8800 0x8000>;
611 + clocks = <&gcc USB30_0_MASTER_CLK>;
612 + clock-names = "core";
613 +
614 + ranges;
615 +
616 + resets = <&gcc USB30_0_MASTER_RESET>;
617 + reset-names = "master";
618 +
619 + status = "disabled";
620 +
621 + dwc3_0: dwc3@11000000 {
622 + compatible = "snps,dwc3";
623 + reg = <0x11000000 0xcd00>;
624 + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
625 + phys = <&hs_phy_0>, <&ss_phy_0>;
626 + phy-names = "usb2-phy", "usb3-phy";
627 + dr_mode = "host";
628 + snps,dis_u3_susphy_quirk;
629 + };
630 + };
631 +
632 + hs_phy_1: hs_phy_1 {
633 + compatible = "qcom,ipq806x-usb-phy-hs";
634 + reg = <0x100f8800 0x30>;
635 + clocks = <&gcc USB30_1_UTMI_CLK>;
636 + clock-names = "ref";
637 + #phy-cells = <0>;
638 + };
639 +
640 + ss_phy_1: ss_phy_1 {
641 + compatible = "qcom,ipq806x-usb-phy-ss";
642 + reg = <0x100f8830 0x30>;
643 + clocks = <&gcc USB30_1_MASTER_CLK>;
644 + clock-names = "ref";
645 + #phy-cells = <0>;
646 + };
647 +
648 + usb3_1: usb3@100f8800 {
649 + compatible = "qcom,dwc3", "syscon";
650 + #address-cells = <1>;
651 + #size-cells = <1>;
652 + reg = <0x100f8800 0x8000>;
653 + clocks = <&gcc USB30_1_MASTER_CLK>;
654 + clock-names = "core";
655 +
656 + ranges;
657 +
658 + resets = <&gcc USB30_1_MASTER_RESET>;
659 + reset-names = "master";
660 +
661 + status = "disabled";
662 +
663 + dwc3_1: dwc3@10000000 {
664 + compatible = "snps,dwc3";
665 + reg = <0x10000000 0xcd00>;
666 + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
667 + phys = <&hs_phy_1>, <&ss_phy_1>;
668 + phy-names = "usb2-phy", "usb3-phy";
669 + dr_mode = "host";
670 + snps,dis_u3_susphy_quirk;
671 + };
672 + };
673 +
674 pcie0: pci@1b500000 {
675 compatible = "qcom,pcie-ipq8064";
676 reg = <0x1b500000 0x1000
677 @@ -739,6 +1332,59 @@
678 status = "disabled";
679 };
680
681 + adm_dma: dma@18300000 {
682 + compatible = "qcom,adm";
683 + reg = <0x18300000 0x100000>;
684 + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
685 + #dma-cells = <1>;
686 +
687 + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
688 + clock-names = "core", "iface";
689 +
690 + resets = <&gcc ADM0_RESET>,
691 + <&gcc ADM0_PBUS_RESET>,
692 + <&gcc ADM0_C0_RESET>,
693 + <&gcc ADM0_C1_RESET>,
694 + <&gcc ADM0_C2_RESET>;
695 + reset-names = "clk", "pbus", "c0", "c1", "c2";
696 + qcom,ee = <0>;
697 +
698 + status = "disabled";
699 + };
700 +
701 + nand_controller: nand-controller@1ac00000 {
702 + compatible = "qcom,ipq806x-nand";
703 + reg = <0x1ac00000 0x800>;
704 +
705 + clocks = <&gcc EBI2_CLK>,
706 + <&gcc EBI2_AON_CLK>;
707 + clock-names = "core", "aon";
708 +
709 + dmas = <&adm_dma 3>;
710 + dma-names = "rxtx";
711 + qcom,cmd-crci = <15>;
712 + qcom,data-crci = <3>;
713 +
714 + status = "disabled";
715 +
716 + #address-cells = <1>;
717 + #size-cells = <0>;
718 + };
719 +
720 + mdio0: mdio@37000000 {
721 + #address-cells = <1>;
722 + #size-cells = <0>;
723 +
724 + compatible = "qcom,ipq8064-mdio", "syscon";
725 + reg = <0x37000000 0x200000>;
726 + resets = <&gcc GMAC_CORE1_RESET>;
727 + reset-names = "stmmaceth";
728 + clocks = <&gcc GMAC_CORE1_CLK>;
729 + clock-names = "stmmaceth";
730 +
731 + status = "disabled";
732 + };
733 +
734 vsdcc_fixed: vsdcc-regulator {
735 compatible = "regulator-fixed";
736 regulator-name = "SDCC Power";
737 @@ -814,4 +1460,17 @@
738 };
739 };
740 };
741 +
742 + sfpb_mutex: sfpb-mutex {
743 + compatible = "qcom,sfpb-mutex";
744 + syscon = <&sfpb_mutex_block 4 4>;
745 +
746 + #hwlock-cells = <1>;
747 + };
748 +
749 + smem {
750 + compatible = "qcom,smem";
751 + memory-region = <&smem>;
752 + hwlocks = <&sfpb_mutex 3>;
753 + };
754 };
Hauke Mehrtens staging tree