target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-le1.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "qcom-ipq4019.dtsi"
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/soc/qcom,tcsr.h>
   7
   8 / {
   9         model = "YYeTs LE1";
  10         compatible = "yyets,le1";
  11
  12         aliases {
  13                 led-boot = &led_usb;
  14                 led-failsafe = &led_usb;
  15                 led-upgrade = &led_usb;
  16
  17                 ethernet0 = &swport5;
  18                 ethernet1 = &gmac;
  19                 label-mac-device = &gmac;
  20         };
  21
  22         keys {
  23                 compatible = "gpio-keys";
  24
  25                 reset {
  26                         label = "reset";
  27                         gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  28                         linux,code = <KEY_RESTART>;
  29                 };
  30         };
  31
  32         leds {
  33                 compatible = "gpio-leds";
  34
  35                 led_usb: usb {
  36                         label = "green:usb";
  37                         gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
  38                         linux,default-trigger = "usbport";
  39                         trigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>;
  40                 };
  41
  42                 wlan2g {
  43                         label = "green:wlan2g";
  44                         gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
  45                         linux,default-trigger = "phy0tpt";
  46                 };
  47
  48                 wlan5g {
  49                         label = "green:wlan5g";
  50                         gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
  51                         linux,default-trigger = "phy1tpt";
  52                 };
  53         };
  54
  55         soc {
  56                 tcsr@1949000 {
  57                         compatible = "qcom,tcsr";
  58                         reg = <0x1949000 0x100>;
  59                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  60                 };
  61
  62                 tcsr@194b000 {
  63                         compatible = "qcom,tcsr";
  64                         reg = <0x194b000 0x100>;
  65                         qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  66                 };
  67
  68                 ess_tcsr@1953000 {
  69                         compatible = "qcom,tcsr";
  70                         reg = <0x1953000 0x1000>;
  71                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  72                 };
  73
  74                 tcsr@1957000 {
  75                         compatible = "qcom,tcsr";
  76                         reg = <0x1957000 0x100>;
  77                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  78                 };
  79         };
  80 };
  81
  82 &blsp_dma {
  83         status = "okay";
  84 };
  85
  86 &blsp1_spi1 {
  87         cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
  88         pinctrl-0 = <&spi_0_pins>;
  89         pinctrl-names = "default";
  90         status = "okay";
  91
  92         flash@0 {
  93                 compatible = "jedec,spi-nor";
  94                 #address-cells = <1>;
  95                 #size-cells = <1>;
  96                 reg = <0>;
  97                 spi-max-frequency = <24000000>;
  98
  99                 partitions {
 100                         compatible = "fixed-partitions";
 101                         #address-cells = <1>;
 102                         #size-cells = <1>;
 103
 104                         partition@0 {
 105                                 label = "SBL1";
 106                                 reg = <0x0 0x40000>;
 107                                 read-only;
 108                         };
 109
 110                         partition@40000 {
 111                                 label = "MIBIB";
 112                                 reg = <0x40000 0x20000>;
 113                                 read-only;
 114                         };
 115
 116                         partition@60000 {
 117                                 label = "QSEE";
 118                                 reg = <0x60000 0x60000>;
 119                                 read-only;
 120                         };
 121
 122                         partition@c0000 {
 123                                 label = "CDT";
 124                                 reg = <0xc0000 0x10000>;
 125                                 read-only;
 126                         };
 127
 128                         partition@d0000 {
 129                                 label = "DDRPARAMS";
 130                                 reg = <0xd0000 0x10000>;
 131                                 read-only;
 132                         };
 133
 134                         partition@e0000 {
 135                                 label = "APPSBLENV";
 136                                 reg = <0xe0000 0x10000>;
 137                                 read-only;
 138                         };
 139
 140                         partition@f0000 {
 141                                 label = "APPSBL";
 142                                 reg = <0xf0000 0x80000>;
 143                                 read-only;
 144                         };
 145
 146                         partition@170000 {
 147                                 label = "ART";
 148                                 reg = <0x170000 0x10000>;
 149                                 read-only;
 150
 151                                 nvmem-layout {
 152                                         compatible = "fixed-layout";
 153                                         #address-cells = <1>;
 154                                         #size-cells = <1>;
 155
 156                                         precal_art_1000: precal@1000 {
 157                                                 reg = <0x1000 0x2f20>;
 158                                         };
 159
 160                                         precal_art_5000: precal@5000 {
 161                                                 reg = <0x5000 0x2f20>;
 162                                         };
 163                                 };
 164                         };
 165
 166                         partition@180000 {
 167                                 compatible = "denx,fit";
 168                                 label = "firmware";
 169                                 reg = <0x180000 0x1e80000>;
 170                         };
 171                 };
 172         };
 173 };
 174
 175 &blsp1_uart1 {
 176         pinctrl-0 = <&serial_pins>;
 177         pinctrl-names = "default";
 178         status = "okay";
 179 };
 180
 181 &cryptobam {
 182         status = "okay";
 183 };
 184
 185 &crypto {
 186         status = "okay";
 187 };
 188
 189 &gmac {
 190         status = "okay";
 191 };
 192
 193 &mdio {
 194         pinctrl-0 = <&mdio_pins>;
 195         pinctrl-names = "default";
 196         status = "okay";
 197 };
 198
 199 &prng {
 200         status = "okay";
 201 };
 202
 203 &switch {
 204         status = "okay";
 205 };
 206
 207 &swport1 {
 208         status = "okay";
 209 };
 210
 211 &swport2 {
 212         status = "okay";
 213 };
 214
 215 &swport3 {
 216         status = "okay";
 217 };
 218
 219 &swport4 {
 220         status = "okay";
 221 };
 222
 223 &swport5 {
 224         status = "okay";
 225 };
 226
 227 &tlmm {
 228         mdio_pins: mdio_pinmux {
 229                 mux_1 {
 230                         pins = "gpio6";
 231                         function = "mdio";
 232                         bias-pull-up;
 233                 };
 234                 mux_2 {
 235                         pins = "gpio7";
 236                         function = "mdc";
 237                         bias-pull-up;
 238                 };
 239         };
 240
 241         serial_pins: serial_pinmux {
 242                 mux {
 243                         pins = "gpio16", "gpio17";
 244                         function = "blsp_uart0";
 245                         bias-disable;
 246                 };
 247         };
 248
 249         spi_0_pins: spi_0_pinmux {
 250                 pinmux {
 251                         function = "blsp_spi0";
 252                         pins = "gpio13", "gpio14", "gpio15";
 253                         drive-strength = <12>;
 254                         bias-disable;
 255                 };
 256
 257                 pinmux_cs {
 258                         function = "gpio";
 259                         pins = "gpio12";
 260                         drive-strength = <2>;
 261                         bias-disable;
 262                         output-high;
 263                 };
 264         };
 265 };
 266
 267 &usb2 {
 268         status = "okay";
 269
 270         dwc3@6000000 {
 271                 #address-cells = <1>;
 272                 #size-cells = <0>;
 273
 274                 usb2_port1: port@1 {
 275                         reg = <1>;
 276                         #trigger-source-cells = <0>;
 277                 };
 278         };
 279 };
 280
 281 &usb2_hs_phy {
 282         status = "okay";
 283 };
 284
 285 &usb3 {
 286         status = "okay";
 287
 288         dwc3@8a00000 {
 289                 #address-cells = <1>;
 290                 #size-cells = <0>;
 291
 292                 usb3_port1: port@1 {
 293                         reg = <1>;
 294                         #trigger-source-cells = <0>;
 295                 };
 296
 297                 usb3_port2: port@2 {
 298                         reg = <2>;
 299                         #trigger-source-cells = <0>;
 300                 };
 301         };
 302 };
 303
 304 &usb3_hs_phy {
 305         status = "okay";
 306 };
 307
 308 &usb3_ss_phy {
 309         status = "okay";
 310 };
 311
 312 &watchdog {
 313         status = "okay";
 314 };
 315
 316 &wifi0 {
 317         status = "okay";
 318         nvmem-cells = <&precal_art_1000>;
 319         nvmem-cell-names = "pre-calibration";
 320         qcom,ath10k-calibration-variant = "YYeTs-LE1";
 321 };
 322
 323 &wifi1 {
 324         status = "okay";
 325         nvmem-cells = <&precal_art_5000>;
 326         nvmem-cell-names = "pre-calibration";
 327         qcom,ath10k-calibration-variant = "YYeTs-LE1";
 328 };