target/linux/brcm47xx/image/lzma-loader/src/head.S

   1 /* Copyright 2005 Oleg I. Vdovikin (oleg@cs.msu.su)     */
   2 /* cache manipulation adapted from Broadcom code        */
   3 /* idea taken from original bunzip2 decompressor code   */
   4 /* Copyright 2004 Manuel Novoa III (mjn3@codepoet.org)  */
   5 /* Licensed under the linux kernel's version of the GPL.*/
   6
   7 #include <asm/asm.h>
   8 #include <asm/regdef.h>
   9
  10 #define KSEG0           0x80000000
  11
  12 #define C0_CONFIG       $16
  13 #define C0_TAGLO        $28
  14 #define C0_TAGHI        $29
  15
  16 #define CONF1_DA_SHIFT  7                       /* D$ associativity */
  17 #define CONF1_DA_MASK   0x00000380
  18 #define CONF1_DA_BASE   1
  19 #define CONF1_DL_SHIFT  10                      /* D$ line size */
  20 #define CONF1_DL_MASK   0x00001c00
  21 #define CONF1_DL_BASE   2
  22 #define CONF1_DS_SHIFT  13                      /* D$ sets/way */
  23 #define CONF1_DS_MASK   0x0000e000
  24 #define CONF1_DS_BASE   64
  25 #define CONF1_IA_SHIFT  16                      /* I$ associativity */
  26 #define CONF1_IA_MASK   0x00070000
  27 #define CONF1_IA_BASE   1
  28 #define CONF1_IL_SHIFT  19                      /* I$ line size */
  29 #define CONF1_IL_MASK   0x00380000
  30 #define CONF1_IL_BASE   2
  31 #define CONF1_IS_SHIFT  22                      /* Instruction cache sets/way */
  32 #define CONF1_IS_MASK   0x01c00000
  33 #define CONF1_IS_BASE   64
  34
  35 #define Index_Invalidate_I      0x00
  36 #define Index_Writeback_Inv_D   0x01
  37
  38         .text
  39         LEAF(startup)
  40         .set noreorder
  41         li      sp, BZ_STACK_START
  42         addi    sp, -48
  43         sw      a0, 16(sp)
  44         sw      a1, 20(sp)
  45         sw      a2, 24(sp)
  46         sw      a3, 28(sp)
  47
  48         /* Copy decompressor code to the right place */
  49         li      t2, BZ_TEXT_START
  50         add     a0, t2, 0
  51         la      a1, code_start
  52         la      a2, code_stop
  53 $L1:
  54         lw      t0, 0(a1)
  55         sw      t0, 0(a0)
  56         add     a1, 4
  57         add     a0, 4
  58         blt     a1, a2, $L1
  59         nop
  60
  61         /* At this point we need to invalidate dcache and */
  62         /* icache before jumping to new code */
  63
  64 1:      /* Get cache sizes */
  65         .set    mips32
  66         mfc0    s0,C0_CONFIG,1
  67         .set    mips0
  68
  69         li      s1,CONF1_DL_MASK
  70         and     s1,s0
  71         beq     s1,zero,nodc
  72         nop
  73
  74         srl     s1,CONF1_DL_SHIFT
  75         li      t0,CONF1_DL_BASE
  76         sll     s1,t0,s1                /* s1 has D$ cache line size */
  77
  78         li      s2,CONF1_DA_MASK
  79         and     s2,s0
  80         srl     s2,CONF1_DA_SHIFT
  81         addiu   s2,CONF1_DA_BASE        /* s2 now has D$ associativity */
  82
  83         li      t0,CONF1_DS_MASK
  84         and     t0,s0
  85         srl     t0,CONF1_DS_SHIFT
  86         li      s3,CONF1_DS_BASE
  87         sll     s3,s3,t0                /* s3 has D$ sets per way */
  88
  89         multu   s2,s3                   /* sets/way * associativity */
  90         mflo    t0                      /* total cache lines */
  91
  92         multu   s1,t0                   /* D$ linesize * lines */
  93         mflo    s2                      /* s2 is now D$ size in bytes */
  94
  95         /* Initilize the D$: */
  96         mtc0    zero,C0_TAGLO
  97         mtc0    zero,C0_TAGHI
  98
  99         li      t0,KSEG0                /* Just an address for the first $ line */
 100         addu    t1,t0,s2                /*  + size of cache == end */
 101
 102         .set    mips3
 103 1:      cache   Index_Writeback_Inv_D,0(t0)
 104         .set    mips0
 105         bne     t0,t1,1b
 106         addu    t0,s1
 107
 108 nodc:
 109         /* Now we get to do it all again for the I$ */
 110
 111         move    s3,zero                 /* just in case there is no icache */
 112         move    s4,zero
 113
 114         li      t0,CONF1_IL_MASK
 115         and     t0,s0
 116         beq     t0,zero,noic
 117         nop
 118
 119         srl     t0,CONF1_IL_SHIFT
 120         li      s3,CONF1_IL_BASE
 121         sll     s3,t0                   /* s3 has I$ cache line size */
 122
 123         li      t0,CONF1_IA_MASK
 124         and     t0,s0
 125         srl     t0,CONF1_IA_SHIFT
 126         addiu   s4,t0,CONF1_IA_BASE     /* s4 now has I$ associativity */
 127
 128         li      t0,CONF1_IS_MASK
 129         and     t0,s0
 130         srl     t0,CONF1_IS_SHIFT
 131         li      s5,CONF1_IS_BASE
 132         sll     s5,t0                   /* s5 has I$ sets per way */
 133
 134         multu   s4,s5                   /* sets/way * associativity */
 135         mflo    t0                      /* s4 is now total cache lines */
 136
 137         multu   s3,t0                   /* I$ linesize * lines */
 138         mflo    s4                      /* s4 is cache size in bytes */
 139
 140         /* Initilize the I$: */
 141         mtc0    zero,C0_TAGLO
 142         mtc0    zero,C0_TAGHI
 143
 144         li      t0,KSEG0                /* Just an address for the first $ line */
 145         addu    t1,t0,s4                /*  + size of cache == end */
 146
 147         .set    mips3
 148 1:      cache   Index_Invalidate_I,0(t0)
 149         .set    mips0
 150         bne     t0,t1,1b
 151         addu    t0,s3
 152
 153 noic:
 154         move    a0,s4                   /* icache size */
 155         move    a1,s3                   /* icache line size */
 156         move    a2,s2                   /* dcache size */
 157         jal     t2
 158         move    a3,s1                   /* dcache line size */
 159
 160         .set reorder
 161         END(startup)