target/linux/bcm4908/patches-5.15/033-v6.0-0004-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM63146.patchgit

   1 From 82a58061ada60058ec00113c179380f945914709 Mon Sep 17 00:00:00 2001
   2 From: William Zhang <william.zhang@broadcom.com>
   3 Date: Wed, 8 Jun 2022 11:00:59 -0700
   4 Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM63146
   5
   6 Add DTS for ARMv8 based broadband SoC BCM63146. bcm63146.dtsi is the
   7 SoC description DTS header and bcm963146.dts is a simple DTS file for
   8 Broadcom BCM963146 Reference board that only enable the UART port.
   9
  10 Signed-off-by: William Zhang <william.zhang@broadcom.com>
  11 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  12 ---
  13  arch/arm64/boot/dts/broadcom/bcmbca/Makefile  |   3 +-
  14  .../boot/dts/broadcom/bcmbca/bcm63146.dtsi    | 110 ++++++++++++++++++
  15  .../boot/dts/broadcom/bcmbca/bcm963146.dts    |  30 +++++
  16  3 files changed, 142 insertions(+), 1 deletion(-)
  17  create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
  18  create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
  19
  20 --- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
  21 +++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
  22 @@ -1,4 +1,5 @@
  23  # SPDX-License-Identifier: GPL-2.0
  24  dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \
  25                                 bcm963158.dtb \
  26 -                               bcm96858.dtb
  27 +                               bcm96858.dtb \
  28 +                               bcm963146.dtb
  29 --- /dev/null
  30 +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
  31 @@ -0,0 +1,110 @@
  32 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  33 +/*
  34 + * Copyright 2022 Broadcom Ltd.
  35 + */
  36 +
  37 +#include <dt-bindings/interrupt-controller/irq.h>
  38 +#include <dt-bindings/interrupt-controller/arm-gic.h>
  39 +
  40 +/ {
  41 +       compatible = "brcm,bcm63146", "brcm,bcmbca";
  42 +       #address-cells = <2>;
  43 +       #size-cells = <2>;
  44 +
  45 +       interrupt-parent = <&gic>;
  46 +
  47 +       cpus {
  48 +               #address-cells = <2>;
  49 +               #size-cells = <0>;
  50 +
  51 +               B53_0: cpu@0 {
  52 +                       compatible = "brcm,brahma-b53";
  53 +                       device_type = "cpu";
  54 +                       reg = <0x0 0x0>;
  55 +                       next-level-cache = <&L2_0>;
  56 +                       enable-method = "psci";
  57 +               };
  58 +
  59 +               B53_1: cpu@1 {
  60 +                       compatible = "brcm,brahma-b53";
  61 +                       device_type = "cpu";
  62 +                       reg = <0x0 0x1>;
  63 +                       next-level-cache = <&L2_0>;
  64 +                       enable-method = "psci";
  65 +               };
  66 +
  67 +               L2_0: l2-cache0 {
  68 +                       compatible = "cache";
  69 +               };
  70 +       };
  71 +
  72 +       timer {
  73 +               compatible = "arm,armv8-timer";
  74 +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  75 +                       <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  76 +                       <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  77 +                       <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  78 +       };
  79 +
  80 +       pmu: pmu {
  81 +               compatible = "arm,cortex-a53-pmu";
  82 +               interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  83 +                       <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  84 +               interrupt-affinity = <&B53_0>, <&B53_1>;
  85 +       };
  86 +
  87 +       clocks: clocks {
  88 +               periph_clk: periph-clk {
  89 +                       compatible = "fixed-clock";
  90 +                       #clock-cells = <0>;
  91 +                       clock-frequency = <200000000>;
  92 +               };
  93 +               uart_clk: uart-clk {
  94 +                       compatible = "fixed-factor-clock";
  95 +                       #clock-cells = <0>;
  96 +                       clocks = <&periph_clk>;
  97 +                       clock-div = <4>;
  98 +                       clock-mult = <1>;
  99 +               };
 100 +       };
 101 +
 102 +       psci {
 103 +               compatible = "arm,psci-0.2";
 104 +               method = "smc";
 105 +       };
 106 +
 107 +       axi@81000000 {
 108 +               compatible = "simple-bus";
 109 +               #address-cells = <1>;
 110 +               #size-cells = <1>;
 111 +               ranges = <0x0 0x0 0x81000000 0x8000>;
 112 +
 113 +               gic: interrupt-controller@1000 {
 114 +                       compatible = "arm,gic-400";
 115 +                       #interrupt-cells = <3>;
 116 +                       interrupt-controller;
 117 +                       reg = <0x1000 0x1000>,
 118 +                               <0x2000 0x2000>,
 119 +                               <0x4000 0x2000>,
 120 +                               <0x6000 0x2000>;
 121 +                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
 122 +                                       IRQ_TYPE_LEVEL_HIGH)>;
 123 +               };
 124 +       };
 125 +
 126 +       bus@ff800000 {
 127 +               compatible = "simple-bus";
 128 +               #address-cells = <1>;
 129 +               #size-cells = <1>;
 130 +               ranges = <0x0 0x0 0xff800000 0x800000>;
 131 +
 132 +               uart0: serial@12000 {
 133 +                       compatible = "arm,pl011", "arm,primecell";
 134 +                       reg = <0x12000 0x1000>;
 135 +                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 136 +                       clocks = <&uart_clk>, <&uart_clk>;
 137 +                       clock-names = "uartclk", "apb_pclk";
 138 +                       status = "disabled";
 139 +               };
 140 +       };
 141 +};
 142 --- /dev/null
 143 +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
 144 @@ -0,0 +1,30 @@
 145 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 146 +/*
 147 + * Copyright 2022 Broadcom Ltd.
 148 + */
 149 +
 150 +/dts-v1/;
 151 +
 152 +#include "bcm63146.dtsi"
 153 +
 154 +/ {
 155 +       model = "Broadcom BCM963146 Reference Board";
 156 +       compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca";
 157 +
 158 +       aliases {
 159 +               serial0 = &uart0;
 160 +       };
 161 +
 162 +       chosen {
 163 +               stdout-path = "serial0:115200n8";
 164 +       };
 165 +
 166 +       memory@0 {
 167 +               device_type = "memory";
 168 +               reg = <0x0 0x0 0x0 0x08000000>;
 169 +       };
 170 +};
 171 +
 172 +&uart0 {
 173 +       status = "okay";
 174 +};