b3447f8be368b144ba56da4c4de9b2ff421bef31
[openwrt/staging/hauke.git] / target / linux / ath79 / dts / qca9558_librerouter_librerouter-v1.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qca955x.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "librerouter,librerouter-v1", "qca,qca9558";
10 model = "LibreRouter v1";
11
12 aliases {
13 led-boot = &led_system;
14 led-failsafe = &led_system;
15 led-running = &led_system;
16 led-upgrade = &led_system;
17 };
18
19 leds {
20 compatible = "gpio-leds";
21
22 led_system: system {
23 label = "green:system";
24 gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
25 default-state = "on";
26 };
27
28 wifi_green {
29 label = "green:wlan2g";
30 gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
31 linux,default-trigger = "phy0tpt";
32 };
33
34 status_blue {
35 label = "blue:status";
36 gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
37 };
38 };
39
40 keys {
41 compatible = "gpio-keys";
42
43 pinctrl-names = "default";
44 /* GPIO1 (poe_pass) and GPIO2 (watchdog) requires jtag disabled */
45 pinctrl-0 = <&jtag_disable_pins>;
46
47 reset {
48 label = "Reset";
49 linux,code = <KEY_RESTART>;
50 gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
51 debounce-interval = <60>;
52 };
53 };
54
55 watchdog {
56 compatible = "linux,wdt-gpio";
57 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
58 hw_algo = "toggle";
59 hw_margin_ms = <1000>;
60 always-running;
61 };
62 };
63
64 &pcie0 {
65 status = "okay";
66
67 wifi@0,0 {
68 compatible = "pci168c,0033";
69 reg = <0x0000 0 0 0 0>;
70 };
71 };
72
73 &pcie1 {
74 status = "okay";
75
76 wifi@0,0 {
77 compatible = "pci168c,0033";
78 reg = <0x0000 0 0 0 0>;
79 };
80 };
81
82 &usb_phy0 {
83 status = "okay";
84 };
85
86 &usb0 {
87 status = "okay";
88 };
89
90 &usb_phy1 {
91 status = "okay";
92 };
93
94 &usb1 {
95 status = "okay";
96 };
97
98 &spi {
99 status = "okay";
100
101 flash@0 {
102 compatible = "jedec,spi-nor";
103 reg = <0>;
104 spi-max-frequency = <25000000>;
105
106 partitions {
107 compatible = "fixed-partitions";
108 #address-cells = <1>;
109 #size-cells = <1>;
110
111 partition@0 {
112 label = "u-boot";
113 reg = <0x000000 0x040000>;
114 read-only;
115 };
116
117 partition@40000 {
118 label = "u-boot-env";
119 reg = <0x040000 0x010000>;
120 };
121
122 partition@50000 {
123 compatible = "denx,uimage";
124 label = "firmware";
125 reg = <0x050000 0x7c0000>;
126 };
127
128 partition@810000 {
129 label = "fw2";
130 reg = <0x810000 0x7d0000>;
131 };
132
133 partition@fd0000 {
134 label = "res";
135 reg = <0xfd0000 0x20000>;
136 };
137
138 art: partition@ff0000 {
139 label = "art";
140 reg = <0xff0000 0x010000>;
141 read-only;
142 };
143 };
144 };
145 };
146
147 &mdio0 {
148 status = "okay";
149
150 phy0: ethernet-phy@0 {
151 reg = <0>;
152 qca,ar8327-initvals = <
153 0x04 0x87600000 /* PORT0: RGMII, MAC0/6 exchage, tx_delay 01, rx_delay 10 */
154 0x0c 0x00000080 /* PORT6: SGMII */
155 0x10 0x81000080 /* POWER_ON_STRAP: LED open drain, SerDes auto-neg disabled */
156 0x50 0xcf37cf37 /* LED_CTRL0 */
157 0x54 0xcf37cf37 /* LED_CTRL1 */
158 0x58 0xcf37cf37 /* LED_CTRL2 */
159 0x5c 0x0 /* LED_CTRL3 */
160 0x7c 0x0000007e /* PORT0_STATUS */
161 0x94 0x0000007e /* PORT6 STATUS */
162 >;
163 };
164 };
165
166 &eth0 {
167 status = "okay";
168
169 pll-data = <0xa6000000 0x00000101 0x00001616>;
170 nvmem-cells = <&macaddr_art_0>;
171 nvmem-cell-names = "mac-address";
172
173 phy-handle = <&phy0>;
174 };
175
176 &eth1 {
177 status = "okay";
178
179 pll-data = <0x03000101 0x00000101 0x00001616>;
180 nvmem-cells = <&macaddr_art_6>;
181 nvmem-cell-names = "mac-address";
182
183 fixed-link {
184 speed = <1000>;
185 full-duplex;
186 };
187 };
188
189 &wmac {
190 status = "okay";
191
192 mtd-cal-data = <&art 0x1000>;
193 nvmem-cells = <&macaddr_art_c>;
194 nvmem-cell-names = "mac-address";
195 };
196
197 &art {
198 compatible = "nvmem-cells";
199 #address-cells = <1>;
200 #size-cells = <1>;
201
202 macaddr_art_0: macaddr@0 {
203 reg = <0x0 0x6>;
204 };
205
206 macaddr_art_6: macaddr@6 {
207 reg = <0x6 0x6>;
208 };
209
210 macaddr_art_c: macaddr@c {
211 reg = <0xc 0x6>;
212 };
213 };