520ca60144b265cca61a26b28ef187b028b20339
[openwrt/staging/hauke.git] / target / linux / ath79 / dts / qca9558_araknis_an-700-ap-i-ac.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qca955x_senao_loader.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "araknis,an-700-ap-i-ac", "qca,qca9558";
10 model = "Araknis AN-700-AP-I-AC";
11
12 aliases {
13 label-mac-device = &eth0;
14 led-boot = &led_power;
15 led-failsafe = &led_power;
16 led-upgrade = &led_power;
17 };
18
19 keys {
20 compatible = "gpio-keys";
21
22 reset {
23 linux,code = <KEY_RESTART>;
24 gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
25 debounce-interval = <60>;
26 };
27 };
28
29 leds {
30 compatible = "gpio-leds";
31
32 led_power: power {
33 label = "amber:power";
34 gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
35 default-state = "off";
36 };
37
38 wifi2g {
39 label = "blue:wifi2g";
40 gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
41 linux,default-trigger = "phy1tpt";
42 };
43
44 wifi5g {
45 label = "blue:wifi5g";
46 gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
47 linux,default-trigger = "phy0tpt";
48 };
49
50 wps {
51 label = "blue:wps";
52 gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
53 };
54 };
55 };
56
57 &partitions {
58 art: partition@ff0000 {
59 label = "art";
60 reg = <0xff0000 0x010000>;
61 read-only;
62 };
63 };
64
65 &mdio0 {
66 status = "okay";
67
68 phy5: ethernet-phy@5 {
69 reg = <5>;
70 eee-broken-100tx;
71 eee-broken-1000t;
72 };
73 };
74
75 &eth0 {
76 status = "okay";
77
78 nvmem-cells = <&macaddr_art_0>;
79 nvmem-cell-names = "mac-address";
80
81 phy-handle = <&phy5>;
82 phy-mode = "rgmii-id";
83
84 pll-data = <0x82000000 0x80000101 0x80001313>;
85 };
86
87 &wmac {
88 status = "okay";
89
90 mtd-cal-data = <&art 0x1000>;
91 nvmem-cells = <&macaddr_art_0>;
92 nvmem-cell-names = "mac-address";
93 mac-address-increment = <1>;
94 };
95
96 &pcie0 {
97 status = "okay";
98 };
99
100 &art {
101 compatible = "nvmem-cells";
102 #address-cells = <1>;
103 #size-cells = <1>;
104
105 macaddr_art_0: macaddr@0 {
106 reg = <0x0 0x6>;
107 };
108 };