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ar71xx: use page fragment API in the ethernet driver
[openwrt/staging/hauke.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0)
17 static inline void skb_free_frag(void *data)
18 {
19 put_page(virt_to_head_page(data));
20 }
21 #endif
22
23 #define AG71XX_DEFAULT_MSG_ENABLE \
24 (NETIF_MSG_DRV \
25 | NETIF_MSG_PROBE \
26 | NETIF_MSG_LINK \
27 | NETIF_MSG_TIMER \
28 | NETIF_MSG_IFDOWN \
29 | NETIF_MSG_IFUP \
30 | NETIF_MSG_RX_ERR \
31 | NETIF_MSG_TX_ERR)
32
33 static int ag71xx_msg_level = -1;
34
35 module_param_named(msg_level, ag71xx_msg_level, int, 0);
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
37
38 #define ETH_SWITCH_HEADER_LEN 2
39
40 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
41
42 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
43 {
44 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
45 }
46
47 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
48 {
49 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
50 ag->dev->name,
51 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
52 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
53 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
54
55 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
58 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
59 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
60 }
61
62 static void ag71xx_dump_regs(struct ag71xx *ag)
63 {
64 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
65 ag->dev->name,
66 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
67 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
68 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
69 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
70 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
71 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
72 ag->dev->name,
73 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
74 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
75 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
76 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
77 ag->dev->name,
78 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
79 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
80 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
81 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
82 ag->dev->name,
83 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
84 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
85 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
86 }
87
88 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
89 {
90 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
91 ag->dev->name, label, intr,
92 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
93 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
94 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
95 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
96 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
97 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
98 }
99
100 static void ag71xx_ring_free(struct ag71xx_ring *ring)
101 {
102 kfree(ring->buf);
103
104 if (ring->descs_cpu)
105 dma_free_coherent(NULL, ring->size * ring->desc_size,
106 ring->descs_cpu, ring->descs_dma);
107 }
108
109 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
110 {
111 int err;
112
113 ring->desc_size = sizeof(struct ag71xx_desc);
114 if (ring->desc_size % cache_line_size()) {
115 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
116 ring, ring->desc_size,
117 roundup(ring->desc_size, cache_line_size()));
118 ring->desc_size = roundup(ring->desc_size, cache_line_size());
119 }
120
121 ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
122 &ring->descs_dma, GFP_ATOMIC);
123 if (!ring->descs_cpu) {
124 err = -ENOMEM;
125 goto err;
126 }
127
128
129 ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
130 if (!ring->buf) {
131 err = -ENOMEM;
132 goto err;
133 }
134
135 return 0;
136
137 err:
138 return err;
139 }
140
141 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
142 {
143 struct ag71xx_ring *ring = &ag->tx_ring;
144 struct net_device *dev = ag->dev;
145 u32 bytes_compl = 0, pkts_compl = 0;
146
147 while (ring->curr != ring->dirty) {
148 struct ag71xx_desc *desc;
149 u32 i = ring->dirty % ring->size;
150
151 desc = ag71xx_ring_desc(ring, i);
152 if (!ag71xx_desc_empty(desc)) {
153 desc->ctrl = 0;
154 dev->stats.tx_errors++;
155 }
156
157 if (ring->buf[i].skb) {
158 bytes_compl += ring->buf[i].len;
159 pkts_compl++;
160 dev_kfree_skb_any(ring->buf[i].skb);
161 }
162 ring->buf[i].skb = NULL;
163 ring->dirty++;
164 }
165
166 /* flush descriptors */
167 wmb();
168
169 netdev_completed_queue(dev, pkts_compl, bytes_compl);
170 }
171
172 static void ag71xx_ring_tx_init(struct ag71xx *ag)
173 {
174 struct ag71xx_ring *ring = &ag->tx_ring;
175 int i;
176
177 for (i = 0; i < ring->size; i++) {
178 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
179
180 desc->next = (u32) (ring->descs_dma +
181 ring->desc_size * ((i + 1) % ring->size));
182
183 desc->ctrl = DESC_EMPTY;
184 ring->buf[i].skb = NULL;
185 }
186
187 /* flush descriptors */
188 wmb();
189
190 ring->curr = 0;
191 ring->dirty = 0;
192 netdev_reset_queue(ag->dev);
193 }
194
195 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
196 {
197 struct ag71xx_ring *ring = &ag->rx_ring;
198 int i;
199
200 if (!ring->buf)
201 return;
202
203 for (i = 0; i < ring->size; i++)
204 if (ring->buf[i].rx_buf) {
205 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
206 ag->rx_buf_size, DMA_FROM_DEVICE);
207 skb_free_frag(ring->buf[i].rx_buf);
208 }
209 }
210
211 static int ag71xx_buffer_offset(struct ag71xx *ag)
212 {
213 int offset = NET_SKB_PAD;
214
215 /*
216 * On AR71xx/AR91xx packets must be 4-byte aligned.
217 *
218 * When using builtin AR8216 support, hardware adds a 2-byte header,
219 * so we don't need any extra alignment in that case.
220 */
221 if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag))
222 return offset;
223
224 return offset + NET_IP_ALIGN;
225 }
226
227 static int ag71xx_buffer_size(struct ag71xx *ag)
228 {
229 return ag->rx_buf_size +
230 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
231 }
232
233 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
234 int offset,
235 void *(*alloc)(unsigned int size))
236 {
237 struct ag71xx_ring *ring = &ag->rx_ring;
238 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
239 void *data;
240
241 data = alloc(ag71xx_buffer_size(ag));
242 if (!data)
243 return false;
244
245 buf->rx_buf = data;
246 buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
247 DMA_FROM_DEVICE);
248 desc->data = (u32) buf->dma_addr + offset;
249 return true;
250 }
251
252 static int ag71xx_ring_rx_init(struct ag71xx *ag)
253 {
254 struct ag71xx_ring *ring = &ag->rx_ring;
255 unsigned int i;
256 int ret;
257 int offset = ag71xx_buffer_offset(ag);
258
259 ret = 0;
260 for (i = 0; i < ring->size; i++) {
261 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
262
263 desc->next = (u32) (ring->descs_dma +
264 ring->desc_size * ((i + 1) % ring->size));
265
266 DBG("ag71xx: RX desc at %p, next is %08x\n",
267 desc, desc->next);
268 }
269
270 for (i = 0; i < ring->size; i++) {
271 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
272
273 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
274 netdev_alloc_frag)) {
275 ret = -ENOMEM;
276 break;
277 }
278
279 desc->ctrl = DESC_EMPTY;
280 }
281
282 /* flush descriptors */
283 wmb();
284
285 ring->curr = 0;
286 ring->dirty = 0;
287
288 return ret;
289 }
290
291 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
292 {
293 struct ag71xx_ring *ring = &ag->rx_ring;
294 unsigned int count;
295 int offset = ag71xx_buffer_offset(ag);
296
297 count = 0;
298 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
299 struct ag71xx_desc *desc;
300 unsigned int i;
301
302 i = ring->dirty % ring->size;
303 desc = ag71xx_ring_desc(ring, i);
304
305 if (!ring->buf[i].rx_buf &&
306 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
307 napi_alloc_frag))
308 break;
309
310 desc->ctrl = DESC_EMPTY;
311 count++;
312 }
313
314 /* flush descriptors */
315 wmb();
316
317 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
318
319 return count;
320 }
321
322 static int ag71xx_rings_init(struct ag71xx *ag)
323 {
324 int ret;
325
326 ret = ag71xx_ring_alloc(&ag->tx_ring);
327 if (ret)
328 return ret;
329
330 ag71xx_ring_tx_init(ag);
331
332 ret = ag71xx_ring_alloc(&ag->rx_ring);
333 if (ret)
334 return ret;
335
336 ret = ag71xx_ring_rx_init(ag);
337 return ret;
338 }
339
340 static void ag71xx_rings_cleanup(struct ag71xx *ag)
341 {
342 ag71xx_ring_rx_clean(ag);
343 ag71xx_ring_free(&ag->rx_ring);
344
345 ag71xx_ring_tx_clean(ag);
346 netdev_reset_queue(ag->dev);
347 ag71xx_ring_free(&ag->tx_ring);
348 }
349
350 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
351 {
352 switch (ag->speed) {
353 case SPEED_1000:
354 return "1000";
355 case SPEED_100:
356 return "100";
357 case SPEED_10:
358 return "10";
359 }
360
361 return "?";
362 }
363
364 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
365 {
366 u32 t;
367
368 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
369 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
370
371 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
372
373 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
374 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
375 }
376
377 static void ag71xx_dma_reset(struct ag71xx *ag)
378 {
379 u32 val;
380 int i;
381
382 ag71xx_dump_dma_regs(ag);
383
384 /* stop RX and TX */
385 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
386 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
387
388 /*
389 * give the hardware some time to really stop all rx/tx activity
390 * clearing the descriptors too early causes random memory corruption
391 */
392 mdelay(1);
393
394 /* clear descriptor addresses */
395 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
396 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
397
398 /* clear pending RX/TX interrupts */
399 for (i = 0; i < 256; i++) {
400 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
401 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
402 }
403
404 /* clear pending errors */
405 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
406 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
407
408 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
409 if (val)
410 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
411 ag->dev->name, val);
412
413 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
414
415 /* mask out reserved bits */
416 val &= ~0xff000000;
417
418 if (val)
419 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
420 ag->dev->name, val);
421
422 ag71xx_dump_dma_regs(ag);
423 }
424
425 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
426 MAC_CFG1_SRX | MAC_CFG1_STX)
427
428 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
429
430 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
431 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
432 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
433 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
434 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
435 FIFO_CFG4_VT)
436
437 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
438 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
439 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
440 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
441 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
442 FIFO_CFG5_17 | FIFO_CFG5_SF)
443
444 static void ag71xx_hw_stop(struct ag71xx *ag)
445 {
446 /* disable all interrupts and stop the rx/tx engine */
447 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
448 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
449 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
450 }
451
452 static void ag71xx_hw_setup(struct ag71xx *ag)
453 {
454 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
455
456 /* setup MAC configuration registers */
457 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
458
459 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
460 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
461
462 /* setup max frame length to zero */
463 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
464
465 /* setup FIFO configuration registers */
466 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
467 if (pdata->is_ar724x) {
468 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
469 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
470 } else {
471 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
472 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
473 }
474 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
475 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
476 }
477
478 static void ag71xx_hw_init(struct ag71xx *ag)
479 {
480 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
481 u32 reset_mask = pdata->reset_bit;
482
483 ag71xx_hw_stop(ag);
484
485 if (pdata->is_ar724x) {
486 u32 reset_phy = reset_mask;
487
488 reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
489 reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
490
491 ath79_device_reset_set(reset_phy);
492 msleep(50);
493 ath79_device_reset_clear(reset_phy);
494 msleep(200);
495 }
496
497 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
498 udelay(20);
499
500 ath79_device_reset_set(reset_mask);
501 msleep(100);
502 ath79_device_reset_clear(reset_mask);
503 msleep(200);
504
505 ag71xx_hw_setup(ag);
506
507 ag71xx_dma_reset(ag);
508 }
509
510 static void ag71xx_fast_reset(struct ag71xx *ag)
511 {
512 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
513 struct net_device *dev = ag->dev;
514 u32 reset_mask = pdata->reset_bit;
515 u32 rx_ds, tx_ds;
516 u32 mii_reg;
517
518 reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
519
520 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
521 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
522 tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
523
524 ath79_device_reset_set(reset_mask);
525 udelay(10);
526 ath79_device_reset_clear(reset_mask);
527 udelay(10);
528
529 ag71xx_dma_reset(ag);
530 ag71xx_hw_setup(ag);
531 ag71xx_tx_packets(ag, true);
532
533 /* setup max frame length */
534 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
535 ag71xx_max_frame_len(ag->dev->mtu));
536
537 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
538 ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
539 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
540
541 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
542 }
543
544 static void ag71xx_hw_start(struct ag71xx *ag)
545 {
546 /* start RX engine */
547 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
548
549 /* enable interrupts */
550 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
551
552 netif_wake_queue(ag->dev);
553 }
554
555 static void
556 __ag71xx_link_adjust(struct ag71xx *ag, bool update)
557 {
558 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
559 u32 cfg2;
560 u32 ifctl;
561 u32 fifo5;
562 u32 fifo3;
563
564 if (!ag->link && update) {
565 ag71xx_hw_stop(ag);
566 netif_carrier_off(ag->dev);
567 if (netif_msg_link(ag))
568 pr_info("%s: link down\n", ag->dev->name);
569 return;
570 }
571
572 if (pdata->is_ar724x)
573 ag71xx_fast_reset(ag);
574
575 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
576 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
577 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
578
579 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
580 ifctl &= ~(MAC_IFCTL_SPEED);
581
582 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
583 fifo5 &= ~FIFO_CFG5_BM;
584
585 switch (ag->speed) {
586 case SPEED_1000:
587 cfg2 |= MAC_CFG2_IF_1000;
588 fifo5 |= FIFO_CFG5_BM;
589 break;
590 case SPEED_100:
591 cfg2 |= MAC_CFG2_IF_10_100;
592 ifctl |= MAC_IFCTL_SPEED;
593 break;
594 case SPEED_10:
595 cfg2 |= MAC_CFG2_IF_10_100;
596 break;
597 default:
598 BUG();
599 return;
600 }
601
602 if (pdata->is_ar91xx)
603 fifo3 = 0x00780fff;
604 else if (pdata->is_ar724x)
605 fifo3 = pdata->fifo_cfg3;
606 else
607 fifo3 = 0x008001ff;
608
609 if (ag->tx_ring.desc_split) {
610 fifo3 &= 0xffff;
611 fifo3 |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
612 }
613
614 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, fifo3);
615
616 if (update && pdata->set_speed)
617 pdata->set_speed(ag->speed);
618
619 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
620 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
621 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
622 ag71xx_hw_start(ag);
623
624 netif_carrier_on(ag->dev);
625 if (update && netif_msg_link(ag))
626 pr_info("%s: link up (%sMbps/%s duplex)\n",
627 ag->dev->name,
628 ag71xx_speed_str(ag),
629 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
630
631 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
632 ag->dev->name,
633 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
634 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
635 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
636
637 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
638 ag->dev->name,
639 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
640 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
641 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
642
643 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
644 ag->dev->name,
645 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
646 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
647 }
648
649 void ag71xx_link_adjust(struct ag71xx *ag)
650 {
651 __ag71xx_link_adjust(ag, true);
652 }
653
654 static int ag71xx_hw_enable(struct ag71xx *ag)
655 {
656 int ret;
657
658 ret = ag71xx_rings_init(ag);
659 if (ret)
660 return ret;
661
662 napi_enable(&ag->napi);
663 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
664 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
665 netif_start_queue(ag->dev);
666
667 return 0;
668 }
669
670 static void ag71xx_hw_disable(struct ag71xx *ag)
671 {
672 unsigned long flags;
673
674 spin_lock_irqsave(&ag->lock, flags);
675
676 netif_stop_queue(ag->dev);
677
678 ag71xx_hw_stop(ag);
679 ag71xx_dma_reset(ag);
680
681 napi_disable(&ag->napi);
682 del_timer_sync(&ag->oom_timer);
683
684 spin_unlock_irqrestore(&ag->lock, flags);
685
686 ag71xx_rings_cleanup(ag);
687 }
688
689 static int ag71xx_open(struct net_device *dev)
690 {
691 struct ag71xx *ag = netdev_priv(dev);
692 unsigned int max_frame_len;
693 int ret;
694
695 netif_carrier_off(dev);
696 max_frame_len = ag71xx_max_frame_len(dev->mtu);
697 ag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
698
699 /* setup max frame length */
700 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
701 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
702
703 ret = ag71xx_hw_enable(ag);
704 if (ret)
705 goto err;
706
707 ag71xx_phy_start(ag);
708
709 return 0;
710
711 err:
712 ag71xx_rings_cleanup(ag);
713 return ret;
714 }
715
716 static int ag71xx_stop(struct net_device *dev)
717 {
718 struct ag71xx *ag = netdev_priv(dev);
719
720 netif_carrier_off(dev);
721 ag71xx_phy_stop(ag);
722 ag71xx_hw_disable(ag);
723
724 return 0;
725 }
726
727 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
728 {
729 int i;
730 struct ag71xx_desc *desc;
731 int ndesc = 0;
732 int split = ring->desc_split;
733
734 if (!split)
735 split = len;
736
737 while (len > 0) {
738 unsigned int cur_len = len;
739
740 i = (ring->curr + ndesc) % ring->size;
741 desc = ag71xx_ring_desc(ring, i);
742
743 if (!ag71xx_desc_empty(desc))
744 return -1;
745
746 if (cur_len > split) {
747 cur_len = split;
748
749 /*
750 * TX will hang if DMA transfers <= 4 bytes,
751 * make sure next segment is more than 4 bytes long.
752 */
753 if (len <= split + 4)
754 cur_len -= 4;
755 }
756
757 desc->data = addr;
758 addr += cur_len;
759 len -= cur_len;
760
761 if (len > 0)
762 cur_len |= DESC_MORE;
763
764 /* prevent early tx attempt of this descriptor */
765 if (!ndesc)
766 cur_len |= DESC_EMPTY;
767
768 desc->ctrl = cur_len;
769 ndesc++;
770 }
771
772 return ndesc;
773 }
774
775 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
776 struct net_device *dev)
777 {
778 struct ag71xx *ag = netdev_priv(dev);
779 struct ag71xx_ring *ring = &ag->tx_ring;
780 struct ag71xx_desc *desc;
781 dma_addr_t dma_addr;
782 int i, n, ring_min;
783
784 if (ag71xx_has_ar8216(ag))
785 ag71xx_add_ar8216_header(ag, skb);
786
787 if (skb->len <= 4) {
788 DBG("%s: packet len is too small\n", ag->dev->name);
789 goto err_drop;
790 }
791
792 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
793 DMA_TO_DEVICE);
794
795 i = ring->curr % ring->size;
796 desc = ag71xx_ring_desc(ring, i);
797
798 /* setup descriptor fields */
799 n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
800 if (n < 0)
801 goto err_drop_unmap;
802
803 i = (ring->curr + n - 1) % ring->size;
804 ring->buf[i].len = skb->len;
805 ring->buf[i].skb = skb;
806 ring->buf[i].timestamp = jiffies;
807
808 netdev_sent_queue(dev, skb->len);
809
810 desc->ctrl &= ~DESC_EMPTY;
811 ring->curr += n;
812
813 /* flush descriptor */
814 wmb();
815
816 ring_min = 2;
817 if (ring->desc_split)
818 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
819
820 if (ring->curr - ring->dirty >= ring->size - ring_min) {
821 DBG("%s: tx queue full\n", dev->name);
822 netif_stop_queue(dev);
823 }
824
825 DBG("%s: packet injected into TX queue\n", ag->dev->name);
826
827 /* enable TX engine */
828 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
829
830 return NETDEV_TX_OK;
831
832 err_drop_unmap:
833 dma_unmap_single(&dev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
834
835 err_drop:
836 dev->stats.tx_dropped++;
837
838 dev_kfree_skb(skb);
839 return NETDEV_TX_OK;
840 }
841
842 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
843 {
844 struct ag71xx *ag = netdev_priv(dev);
845 int ret;
846
847 switch (cmd) {
848 case SIOCETHTOOL:
849 if (ag->phy_dev == NULL)
850 break;
851
852 spin_lock_irq(&ag->lock);
853 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
854 spin_unlock_irq(&ag->lock);
855 return ret;
856
857 case SIOCSIFHWADDR:
858 if (copy_from_user
859 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
860 return -EFAULT;
861 return 0;
862
863 case SIOCGIFHWADDR:
864 if (copy_to_user
865 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
866 return -EFAULT;
867 return 0;
868
869 case SIOCGMIIPHY:
870 case SIOCGMIIREG:
871 case SIOCSMIIREG:
872 if (ag->phy_dev == NULL)
873 break;
874
875 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
876
877 default:
878 break;
879 }
880
881 return -EOPNOTSUPP;
882 }
883
884 static void ag71xx_oom_timer_handler(unsigned long data)
885 {
886 struct net_device *dev = (struct net_device *) data;
887 struct ag71xx *ag = netdev_priv(dev);
888
889 napi_schedule(&ag->napi);
890 }
891
892 static void ag71xx_tx_timeout(struct net_device *dev)
893 {
894 struct ag71xx *ag = netdev_priv(dev);
895
896 if (netif_msg_tx_err(ag))
897 pr_info("%s: tx timeout\n", ag->dev->name);
898
899 schedule_work(&ag->restart_work);
900 }
901
902 static void ag71xx_restart_work_func(struct work_struct *work)
903 {
904 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
905
906 rtnl_lock();
907 ag71xx_hw_disable(ag);
908 ag71xx_hw_enable(ag);
909 if (ag->link)
910 __ag71xx_link_adjust(ag, false);
911 rtnl_unlock();
912 }
913
914 static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
915 {
916 u32 rx_sm, tx_sm, rx_fd;
917
918 if (likely(time_before(jiffies, timestamp + HZ/10)))
919 return false;
920
921 if (!netif_carrier_ok(ag->dev))
922 return false;
923
924 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
925 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
926 return true;
927
928 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
929 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
930 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
931 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
932 return true;
933
934 return false;
935 }
936
937 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
938 {
939 struct ag71xx_ring *ring = &ag->tx_ring;
940 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
941 int sent = 0;
942 int bytes_compl = 0;
943 int n = 0;
944
945 DBG("%s: processing TX ring\n", ag->dev->name);
946
947 while (ring->dirty + n != ring->curr) {
948 unsigned int i = (ring->dirty + n) % ring->size;
949 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
950 struct sk_buff *skb = ring->buf[i].skb;
951
952 if (!flush && !ag71xx_desc_empty(desc)) {
953 if (pdata->is_ar724x &&
954 ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
955 schedule_work(&ag->restart_work);
956 break;
957 }
958
959 n++;
960 if (!skb)
961 continue;
962
963 dev_kfree_skb_any(skb);
964 ring->buf[i].skb = NULL;
965
966 bytes_compl += ring->buf[i].len;
967
968 sent++;
969 ring->dirty += n;
970
971 while (n > 0) {
972 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
973 n--;
974 }
975 }
976
977 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
978
979 ag->dev->stats.tx_bytes += bytes_compl;
980 ag->dev->stats.tx_packets += sent;
981
982 if (!sent)
983 return 0;
984
985 netdev_completed_queue(ag->dev, sent, bytes_compl);
986 if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
987 netif_wake_queue(ag->dev);
988
989 return sent;
990 }
991
992 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
993 {
994 struct net_device *dev = ag->dev;
995 struct ag71xx_ring *ring = &ag->rx_ring;
996 int offset = ag71xx_buffer_offset(ag);
997 unsigned int pktlen_mask = ag->desc_pktlen_mask;
998 int done = 0;
999
1000 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1001 dev->name, limit, ring->curr, ring->dirty);
1002
1003 while (done < limit) {
1004 unsigned int i = ring->curr % ring->size;
1005 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1006 struct sk_buff *skb;
1007 int pktlen;
1008 int err = 0;
1009
1010 if (ag71xx_desc_empty(desc))
1011 break;
1012
1013 if ((ring->dirty + ring->size) == ring->curr) {
1014 ag71xx_assert(0);
1015 break;
1016 }
1017
1018 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1019
1020 pktlen = desc->ctrl & pktlen_mask;
1021 pktlen -= ETH_FCS_LEN;
1022
1023 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
1024 ag->rx_buf_size, DMA_FROM_DEVICE);
1025
1026 dev->stats.rx_packets++;
1027 dev->stats.rx_bytes += pktlen;
1028
1029 skb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag));
1030 if (!skb) {
1031 skb_free_frag(ring->buf[i].rx_buf);
1032 goto next;
1033 }
1034
1035 skb_reserve(skb, offset);
1036 skb_put(skb, pktlen);
1037
1038 if (ag71xx_has_ar8216(ag))
1039 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
1040
1041 if (err) {
1042 dev->stats.rx_dropped++;
1043 kfree_skb(skb);
1044 } else {
1045 skb->dev = dev;
1046 skb->ip_summed = CHECKSUM_NONE;
1047 skb->protocol = eth_type_trans(skb, dev);
1048 netif_receive_skb(skb);
1049 }
1050
1051 next:
1052 ring->buf[i].rx_buf = NULL;
1053 done++;
1054
1055 ring->curr++;
1056 }
1057
1058 ag71xx_ring_rx_refill(ag);
1059
1060 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1061 dev->name, ring->curr, ring->dirty, done);
1062
1063 return done;
1064 }
1065
1066 static int ag71xx_poll(struct napi_struct *napi, int limit)
1067 {
1068 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1069 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
1070 struct net_device *dev = ag->dev;
1071 struct ag71xx_ring *rx_ring;
1072 unsigned long flags;
1073 u32 status;
1074 int tx_done;
1075 int rx_done;
1076
1077 pdata->ddr_flush();
1078 tx_done = ag71xx_tx_packets(ag, false);
1079
1080 DBG("%s: processing RX ring\n", dev->name);
1081 rx_done = ag71xx_rx_packets(ag, limit);
1082
1083 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1084
1085 rx_ring = &ag->rx_ring;
1086 if (rx_ring->buf[rx_ring->dirty % rx_ring->size].rx_buf == NULL)
1087 goto oom;
1088
1089 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1090 if (unlikely(status & RX_STATUS_OF)) {
1091 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1092 dev->stats.rx_fifo_errors++;
1093
1094 /* restart RX */
1095 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1096 }
1097
1098 if (rx_done < limit) {
1099 if (status & RX_STATUS_PR)
1100 goto more;
1101
1102 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1103 if (status & TX_STATUS_PS)
1104 goto more;
1105
1106 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1107 dev->name, rx_done, tx_done, limit);
1108
1109 napi_complete(napi);
1110
1111 /* enable interrupts */
1112 spin_lock_irqsave(&ag->lock, flags);
1113 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1114 spin_unlock_irqrestore(&ag->lock, flags);
1115 return rx_done;
1116 }
1117
1118 more:
1119 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1120 dev->name, rx_done, tx_done, limit);
1121 return limit;
1122
1123 oom:
1124 if (netif_msg_rx_err(ag))
1125 pr_info("%s: out of memory\n", dev->name);
1126
1127 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1128 napi_complete(napi);
1129 return 0;
1130 }
1131
1132 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1133 {
1134 struct net_device *dev = dev_id;
1135 struct ag71xx *ag = netdev_priv(dev);
1136 u32 status;
1137
1138 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1139 ag71xx_dump_intr(ag, "raw", status);
1140
1141 if (unlikely(!status))
1142 return IRQ_NONE;
1143
1144 if (unlikely(status & AG71XX_INT_ERR)) {
1145 if (status & AG71XX_INT_TX_BE) {
1146 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1147 dev_err(&dev->dev, "TX BUS error\n");
1148 }
1149 if (status & AG71XX_INT_RX_BE) {
1150 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1151 dev_err(&dev->dev, "RX BUS error\n");
1152 }
1153 }
1154
1155 if (likely(status & AG71XX_INT_POLL)) {
1156 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1157 DBG("%s: enable polling mode\n", dev->name);
1158 napi_schedule(&ag->napi);
1159 }
1160
1161 ag71xx_debugfs_update_int_stats(ag, status);
1162
1163 return IRQ_HANDLED;
1164 }
1165
1166 #ifdef CONFIG_NET_POLL_CONTROLLER
1167 /*
1168 * Polling 'interrupt' - used by things like netconsole to send skbs
1169 * without having to re-enable interrupts. It's not called while
1170 * the interrupt routine is executing.
1171 */
1172 static void ag71xx_netpoll(struct net_device *dev)
1173 {
1174 disable_irq(dev->irq);
1175 ag71xx_interrupt(dev->irq, dev);
1176 enable_irq(dev->irq);
1177 }
1178 #endif
1179
1180 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1181 {
1182 struct ag71xx *ag = netdev_priv(dev);
1183 unsigned int max_frame_len;
1184
1185 max_frame_len = ag71xx_max_frame_len(new_mtu);
1186 if (new_mtu < 68 || max_frame_len > ag->max_frame_len)
1187 return -EINVAL;
1188
1189 if (netif_running(dev))
1190 return -EBUSY;
1191
1192 dev->mtu = new_mtu;
1193 return 0;
1194 }
1195
1196 static const struct net_device_ops ag71xx_netdev_ops = {
1197 .ndo_open = ag71xx_open,
1198 .ndo_stop = ag71xx_stop,
1199 .ndo_start_xmit = ag71xx_hard_start_xmit,
1200 .ndo_do_ioctl = ag71xx_do_ioctl,
1201 .ndo_tx_timeout = ag71xx_tx_timeout,
1202 .ndo_change_mtu = ag71xx_change_mtu,
1203 .ndo_set_mac_address = eth_mac_addr,
1204 .ndo_validate_addr = eth_validate_addr,
1205 #ifdef CONFIG_NET_POLL_CONTROLLER
1206 .ndo_poll_controller = ag71xx_netpoll,
1207 #endif
1208 };
1209
1210 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
1211 {
1212 switch (mode) {
1213 case PHY_INTERFACE_MODE_MII:
1214 return "MII";
1215 case PHY_INTERFACE_MODE_GMII:
1216 return "GMII";
1217 case PHY_INTERFACE_MODE_RMII:
1218 return "RMII";
1219 case PHY_INTERFACE_MODE_RGMII:
1220 return "RGMII";
1221 case PHY_INTERFACE_MODE_SGMII:
1222 return "SGMII";
1223 default:
1224 break;
1225 }
1226
1227 return "unknown";
1228 }
1229
1230
1231 static int ag71xx_probe(struct platform_device *pdev)
1232 {
1233 struct net_device *dev;
1234 struct resource *res;
1235 struct ag71xx *ag;
1236 struct ag71xx_platform_data *pdata;
1237 int err;
1238
1239 pdata = pdev->dev.platform_data;
1240 if (!pdata) {
1241 dev_err(&pdev->dev, "no platform data specified\n");
1242 err = -ENXIO;
1243 goto err_out;
1244 }
1245
1246 if (pdata->mii_bus_dev == NULL && pdata->phy_mask) {
1247 dev_err(&pdev->dev, "no MII bus device specified\n");
1248 err = -EINVAL;
1249 goto err_out;
1250 }
1251
1252 dev = alloc_etherdev(sizeof(*ag));
1253 if (!dev) {
1254 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1255 err = -ENOMEM;
1256 goto err_out;
1257 }
1258
1259 if (!pdata->max_frame_len || !pdata->desc_pktlen_mask)
1260 return -EINVAL;
1261
1262 SET_NETDEV_DEV(dev, &pdev->dev);
1263
1264 ag = netdev_priv(dev);
1265 ag->pdev = pdev;
1266 ag->dev = dev;
1267 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1268 AG71XX_DEFAULT_MSG_ENABLE);
1269 spin_lock_init(&ag->lock);
1270
1271 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1272 if (!res) {
1273 dev_err(&pdev->dev, "no mac_base resource found\n");
1274 err = -ENXIO;
1275 goto err_out;
1276 }
1277
1278 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1279 if (!ag->mac_base) {
1280 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1281 err = -ENOMEM;
1282 goto err_free_dev;
1283 }
1284
1285 dev->irq = platform_get_irq(pdev, 0);
1286 err = request_irq(dev->irq, ag71xx_interrupt,
1287 0x0,
1288 dev->name, dev);
1289 if (err) {
1290 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1291 goto err_unmap_base;
1292 }
1293
1294 dev->base_addr = (unsigned long)ag->mac_base;
1295 dev->netdev_ops = &ag71xx_netdev_ops;
1296 dev->ethtool_ops = &ag71xx_ethtool_ops;
1297
1298 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1299
1300 init_timer(&ag->oom_timer);
1301 ag->oom_timer.data = (unsigned long) dev;
1302 ag->oom_timer.function = ag71xx_oom_timer_handler;
1303
1304 ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
1305 ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
1306
1307 ag->max_frame_len = pdata->max_frame_len;
1308 ag->desc_pktlen_mask = pdata->desc_pktlen_mask;
1309
1310 if (!pdata->is_ar724x && !pdata->is_ar91xx) {
1311 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1312 ag->tx_ring.size *= AG71XX_TX_RING_DS_PER_PKT;
1313 }
1314
1315 ag->stop_desc = dma_alloc_coherent(NULL,
1316 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1317
1318 if (!ag->stop_desc)
1319 goto err_free_irq;
1320
1321 ag->stop_desc->data = 0;
1322 ag->stop_desc->ctrl = 0;
1323 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1324
1325 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1326
1327 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1328
1329 ag71xx_dump_regs(ag);
1330
1331 ag71xx_hw_init(ag);
1332
1333 ag71xx_dump_regs(ag);
1334
1335 err = ag71xx_phy_connect(ag);
1336 if (err)
1337 goto err_free_desc;
1338
1339 err = ag71xx_debugfs_init(ag);
1340 if (err)
1341 goto err_phy_disconnect;
1342
1343 platform_set_drvdata(pdev, dev);
1344
1345 err = register_netdev(dev);
1346 if (err) {
1347 dev_err(&pdev->dev, "unable to register net device\n");
1348 goto err_debugfs_exit;
1349 }
1350
1351 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1352 dev->name, dev->base_addr, dev->irq,
1353 ag71xx_get_phy_if_mode_name(pdata->phy_if_mode));
1354
1355 return 0;
1356
1357 err_debugfs_exit:
1358 ag71xx_debugfs_exit(ag);
1359 err_phy_disconnect:
1360 ag71xx_phy_disconnect(ag);
1361 err_free_desc:
1362 dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1363 ag->stop_desc_dma);
1364 err_free_irq:
1365 free_irq(dev->irq, dev);
1366 err_unmap_base:
1367 iounmap(ag->mac_base);
1368 err_free_dev:
1369 kfree(dev);
1370 err_out:
1371 platform_set_drvdata(pdev, NULL);
1372 return err;
1373 }
1374
1375 static int ag71xx_remove(struct platform_device *pdev)
1376 {
1377 struct net_device *dev = platform_get_drvdata(pdev);
1378
1379 if (dev) {
1380 struct ag71xx *ag = netdev_priv(dev);
1381
1382 ag71xx_debugfs_exit(ag);
1383 ag71xx_phy_disconnect(ag);
1384 unregister_netdev(dev);
1385 free_irq(dev->irq, dev);
1386 iounmap(ag->mac_base);
1387 kfree(dev);
1388 platform_set_drvdata(pdev, NULL);
1389 }
1390
1391 return 0;
1392 }
1393
1394 static struct platform_driver ag71xx_driver = {
1395 .probe = ag71xx_probe,
1396 .remove = ag71xx_remove,
1397 .driver = {
1398 .name = AG71XX_DRV_NAME,
1399 }
1400 };
1401
1402 static int __init ag71xx_module_init(void)
1403 {
1404 int ret;
1405
1406 ret = ag71xx_debugfs_root_init();
1407 if (ret)
1408 goto err_out;
1409
1410 ret = ag71xx_mdio_driver_init();
1411 if (ret)
1412 goto err_debugfs_exit;
1413
1414 ret = platform_driver_register(&ag71xx_driver);
1415 if (ret)
1416 goto err_mdio_exit;
1417
1418 return 0;
1419
1420 err_mdio_exit:
1421 ag71xx_mdio_driver_exit();
1422 err_debugfs_exit:
1423 ag71xx_debugfs_root_exit();
1424 err_out:
1425 return ret;
1426 }
1427
1428 static void __exit ag71xx_module_exit(void)
1429 {
1430 platform_driver_unregister(&ag71xx_driver);
1431 ag71xx_mdio_driver_exit();
1432 ag71xx_debugfs_root_exit();
1433 }
1434
1435 module_init(ag71xx_module_init);
1436 module_exit(ag71xx_module_exit);
1437
1438 MODULE_VERSION(AG71XX_DRV_VERSION);
1439 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1440 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1441 MODULE_LICENSE("GPL v2");
1442 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
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