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ar71xx: ar934x_nfc: return error code from some low-level functions
[openwrt/staging/hauke.git] / target / linux / ar71xx / files / drivers / mtd / nand / ar934x_nfc.c
1 /*
2 * Driver for the built-in NAND controller of the Atheros AR934x SoCs
3 *
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/nand.h>
17 #include <linux/mtd/partitions.h>
18 #include <linux/platform_device.h>
19 #include <linux/delay.h>
20 #include <linux/slab.h>
21
22 #include <linux/platform/ar934x_nfc.h>
23
24 #define AR934X_NFC_REG_CMD 0x00
25 #define AR934X_NFC_REG_CTRL 0x04
26 #define AR934X_NFC_REG_STATUS 0x08
27 #define AR934X_NFC_REG_INT_MASK 0x0c
28 #define AR934X_NFC_REG_INT_STATUS 0x10
29 #define AR934X_NFC_REG_ECC_CTRL 0x14
30 #define AR934X_NFC_REG_ECC_OFFSET 0x18
31 #define AR934X_NFC_REG_ADDR0_0 0x1c
32 #define AR934X_NFC_REG_ADDR0_1 0x24
33 #define AR934X_NFC_REG_ADDR1_0 0x20
34 #define AR934X_NFC_REG_ADDR1_1 0x28
35 #define AR934X_NFC_REG_SPARE_SIZE 0x30
36 #define AR934X_NFC_REG_PROTECT 0x38
37 #define AR934X_NFC_REG_LOOKUP_EN 0x40
38 #define AR934X_NFC_REG_LOOKUP(_x) (0x44 + (_i) * 4)
39 #define AR934X_NFC_REG_DMA_ADDR 0x64
40 #define AR934X_NFC_REG_DMA_COUNT 0x68
41 #define AR934X_NFC_REG_DMA_CTRL 0x6c
42 #define AR934X_NFC_REG_MEM_CTRL 0x80
43 #define AR934X_NFC_REG_DATA_SIZE 0x84
44 #define AR934X_NFC_REG_READ_STATUS 0x88
45 #define AR934X_NFC_REG_TIME_SEQ 0x8c
46 #define AR934X_NFC_REG_TIMINGS_ASYN 0x90
47 #define AR934X_NFC_REG_TIMINGS_SYN 0x94
48 #define AR934X_NFC_REG_FIFO_DATA 0x98
49 #define AR934X_NFC_REG_TIME_MODE 0x9c
50 #define AR934X_NFC_REG_DMA_ADDR_OFFS 0xa0
51 #define AR934X_NFC_REG_FIFO_INIT 0xb0
52 #define AR934X_NFC_REG_GEN_SEQ_CTRL 0xb4
53
54 #define AR934X_NFC_CMD_CMD_SEQ_S 0
55 #define AR934X_NFC_CMD_CMD_SEQ_M 0x3f
56 #define AR934X_NFC_CMD_SEQ_1C 0x00
57 #define AR934X_NFC_CMD_SEQ_ERASE 0x0e
58 #define AR934X_NFC_CMD_SEQ_12 0x0c
59 #define AR934X_NFC_CMD_SEQ_1C1AXR 0x21
60 #define AR934X_NFC_CMD_SEQ_S 0x24
61 #define AR934X_NFC_CMD_SEQ_1C3AXR 0x27
62 #define AR934X_NFC_CMD_SEQ_1C5A1CXR 0x2a
63 #define AR934X_NFC_CMD_SEQ_18 0x32
64 #define AR934X_NFC_CMD_INPUT_SEL_SIU 0
65 #define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6)
66 #define AR934X_NFC_CMD_ADDR_SEL_0 0
67 #define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7)
68 #define AR934X_NFC_CMD_CMD0_S 8
69 #define AR934X_NFC_CMD_CMD0_M 0xff
70 #define AR934X_NFC_CMD_CMD1_S 16
71 #define AR934X_NFC_CMD_CMD1_M 0xff
72 #define AR934X_NFC_CMD_CMD2_S 24
73 #define AR934X_NFC_CMD_CMD2_M 0xff
74
75 #define AR934X_NFC_CTRL_ADDR_CYCLE0_M 0x7
76 #define AR934X_NFC_CTRL_ADDR_CYCLE0_S 0
77 #define AR934X_NFC_CTRL_SPARE_EN BIT(3)
78 #define AR934X_NFC_CTRL_INT_EN BIT(4)
79 #define AR934X_NFC_CTRL_ECC_EN BIT(5)
80 #define AR934X_NFC_CTRL_BLOCK_SIZE_S 6
81 #define AR934X_NFC_CTRL_BLOCK_SIZE_M 0x3
82 #define AR934X_NFC_CTRL_BLOCK_SIZE_32 0
83 #define AR934X_NFC_CTRL_BLOCK_SIZE_64 1
84 #define AR934X_NFC_CTRL_BLOCK_SIZE_128 2
85 #define AR934X_NFC_CTRL_BLOCK_SIZE_256 3
86 #define AR934X_NFC_CTRL_PAGE_SIZE_S 8
87 #define AR934X_NFC_CTRL_PAGE_SIZE_M 0x7
88 #define AR934X_NFC_CTRL_PAGE_SIZE_256 0
89 #define AR934X_NFC_CTRL_PAGE_SIZE_512 1
90 #define AR934X_NFC_CTRL_PAGE_SIZE_1024 2
91 #define AR934X_NFC_CTRL_PAGE_SIZE_2048 3
92 #define AR934X_NFC_CTRL_PAGE_SIZE_4096 4
93 #define AR934X_NFC_CTRL_PAGE_SIZE_8192 5
94 #define AR934X_NFC_CTRL_PAGE_SIZE_16384 6
95 #define AR934X_NFC_CTRL_CUSTOM_SIZE_EN BIT(11)
96 #define AR934X_NFC_CTRL_IO_WIDTH_8BITS 0
97 #define AR934X_NFC_CTRL_IO_WIDTH_16BITS BIT(12)
98 #define AR934X_NFC_CTRL_LOOKUP_EN BIT(13)
99 #define AR934X_NFC_CTRL_PROT_EN BIT(14)
100 #define AR934X_NFC_CTRL_WORK_MODE_ASYNC 0
101 #define AR934X_NFC_CTRL_WORK_MODE_SYNC BIT(15)
102 #define AR934X_NFC_CTRL_ADDR0_AUTO_INC BIT(16)
103 #define AR934X_NFC_CTRL_ADDR1_AUTO_INC BIT(17)
104 #define AR934X_NFC_CTRL_ADDR_CYCLE1_M 0x7
105 #define AR934X_NFC_CTRL_ADDR_CYCLE1_S 18
106 #define AR934X_NFC_CTRL_SMALL_PAGE BIT(21)
107
108 #define AR934X_NFC_DMA_CTRL_DMA_START BIT(7)
109 #define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE 0
110 #define AR934X_NFC_DMA_CTRL_DMA_DIR_READ BIT(6)
111 #define AR934X_NFC_DMA_CTRL_DMA_MODE_SG BIT(5)
112 #define AR934X_NFC_DMA_CTRL_DMA_BURST_S 2
113 #define AR934X_NFC_DMA_CTRL_DMA_BURST_0 0
114 #define AR934X_NFC_DMA_CTRL_DMA_BURST_1 1
115 #define AR934X_NFC_DMA_CTRL_DMA_BURST_2 2
116 #define AR934X_NFC_DMA_CTRL_DMA_BURST_3 3
117 #define AR934X_NFC_DMA_CTRL_DMA_BURST_4 4
118 #define AR934X_NFC_DMA_CTRL_DMA_BURST_5 5
119 #define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1)
120 #define AR934X_NFC_DMA_CTRL_DMA_READY BIT(0)
121
122 #define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x))
123 #define AR934X_NFC_INT_CMD_END BIT(1)
124
125 /* default timing values */
126 #define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff
127 #define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22
128 #define AR934X_NFC_TIMINGS_SYN_DEFAULT 0xf
129
130 #define AR934X_NFC_ID_BUF_SIZE 8
131 #define AR934X_NFC_DEV_READY_TIMEOUT 25 /* msecs */
132 #define AR934X_NFC_DMA_READY_TIMEOUT 25 /* msecs */
133 #define AR934X_NFC_DONE_TIMEOUT 1000
134 #define AR934X_NFC_DMA_RETRIES 20
135
136 #define AR934X_NFC_USE_IRQ true
137 #define AR934X_NFC_IRQ_MASK AR934X_NFC_INT_DEV_RDY(0)
138
139 #define AR934X_NFC_GENSEQ_SMALL_PAGE_READ 0x30043
140
141 #undef AR934X_NFC_DEBUG_DATA
142 #undef AR934X_NFC_DEBUG
143
144 struct ar934x_nfc;
145
146 static inline __attribute__ ((format (printf, 2, 3)))
147 void _nfc_dbg(struct ar934x_nfc *nfc, const char *fmt, ...)
148 {
149 }
150
151 #ifdef AR934X_NFC_DEBUG
152 #define nfc_dbg(_nfc, fmt, ...) \
153 dev_info((_nfc)->parent, fmt, ##__VA_ARGS__)
154 #else
155 #define nfc_dbg(_nfc, fmt, ...) \
156 _nfc_dbg((_nfc), fmt, ##__VA_ARGS__)
157 #endif /* AR934X_NFC_DEBUG */
158
159 #ifdef AR934X_NFC_DEBUG_DATA
160 static void
161 nfc_debug_data(const char *label, void *data, int len)
162 {
163 print_hex_dump(KERN_WARNING, label, DUMP_PREFIX_OFFSET, 16, 1,
164 data, len, 0);
165 }
166 #else
167 static inline void
168 nfc_debug_data(const char *label, void *data, int len) {}
169 #endif /* AR934X_NFC_DEBUG_DATA */
170
171 struct ar934x_nfc {
172 struct mtd_info mtd;
173 struct nand_chip nand_chip;
174 struct device *parent;
175 void __iomem *base;
176 void (*select_chip)(int chip_no);
177 bool swap_dma;
178 int irq;
179 wait_queue_head_t irq_waitq;
180
181 bool spurious_irq_expected;
182 u32 irq_status;
183
184 u32 ctrl_reg;
185 bool small_page;
186 unsigned int addr_count0;
187 unsigned int addr_count1;
188
189 u8 *buf;
190 dma_addr_t buf_dma;
191 unsigned int buf_size;
192 int buf_index;
193
194 bool read_id;
195
196 int erase1_page_addr;
197
198 int rndout_page_addr;
199 int rndout_read_cmd;
200
201 int seqin_page_addr;
202 int seqin_column;
203 int seqin_read_cmd;
204 };
205
206 static void ar934x_nfc_restart(struct ar934x_nfc *nfc);
207
208 static inline void
209 ar934x_nfc_wr(struct ar934x_nfc *nfc, unsigned reg, u32 val)
210 {
211 __raw_writel(val, nfc->base + reg);
212 }
213
214 static inline u32
215 ar934x_nfc_rr(struct ar934x_nfc *nfc, unsigned reg)
216 {
217 return __raw_readl(nfc->base + reg);
218 }
219
220 static inline struct ar934x_nfc_platform_data *
221 ar934x_nfc_get_platform_data(struct ar934x_nfc *nfc)
222 {
223 return nfc->parent->platform_data;
224 }
225
226 static inline struct
227 ar934x_nfc *mtd_to_ar934x_nfc(struct mtd_info *mtd)
228 {
229 return container_of(mtd, struct ar934x_nfc, mtd);
230 }
231
232 static inline bool ar934x_nfc_use_irq(struct ar934x_nfc *nfc)
233 {
234 return AR934X_NFC_USE_IRQ;
235 }
236
237 static inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc *nfc, u32 cmd_reg)
238 {
239 wmb();
240
241 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CMD, cmd_reg);
242 /* flush write */
243 ar934x_nfc_rr(nfc, AR934X_NFC_REG_CMD);
244 }
245
246 static bool
247 __ar934x_nfc_dev_ready(struct ar934x_nfc *nfc)
248 {
249 u32 status;
250
251 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS);
252 return (status & 0xff) == 0xff;
253 }
254
255 static inline bool
256 __ar934x_nfc_is_dma_ready(struct ar934x_nfc *nfc)
257 {
258 u32 status;
259
260 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL);
261 return (status & AR934X_NFC_DMA_CTRL_DMA_READY) != 0;
262 }
263
264 static int
265 ar934x_nfc_wait_dev_ready(struct ar934x_nfc *nfc)
266 {
267 unsigned long timeout;
268
269 timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT);
270 do {
271 if (__ar934x_nfc_dev_ready(nfc))
272 return 0;
273 } while time_before(jiffies, timeout);
274
275 nfc_dbg(nfc, "timeout waiting for device ready, status:%08x int:%08x\n",
276 ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS),
277 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS));
278 return -ETIMEDOUT;
279 }
280
281 static int
282 ar934x_nfc_wait_dma_ready(struct ar934x_nfc *nfc)
283 {
284 unsigned long timeout;
285
286 timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT);
287 do {
288 if (__ar934x_nfc_is_dma_ready(nfc))
289 return 0;
290 } while time_before(jiffies, timeout);
291
292 nfc_dbg(nfc, "timeout waiting for DMA ready, dma_ctrl:%08x\n",
293 ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL));
294 return -ETIMEDOUT;
295 }
296
297 static int
298 ar934x_nfc_wait_irq(struct ar934x_nfc *nfc)
299 {
300 long timeout;
301 int ret;
302
303 timeout = wait_event_timeout(nfc->irq_waitq,
304 (nfc->irq_status & AR934X_NFC_IRQ_MASK) != 0,
305 msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT));
306
307 ret = 0;
308 if (!timeout) {
309 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, 0);
310 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
311 /* flush write */
312 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
313
314 nfc_dbg(nfc,
315 "timeout waiting for interrupt, status:%08x\n",
316 nfc->irq_status);
317 ret = -ETIMEDOUT;
318 }
319
320 nfc->irq_status = 0;
321 return ret;
322 }
323
324 static int
325 ar934x_nfc_wait_done(struct ar934x_nfc *nfc)
326 {
327 int ret;
328
329 if (ar934x_nfc_use_irq(nfc))
330 ret = ar934x_nfc_wait_irq(nfc);
331 else
332 ret = ar934x_nfc_wait_dev_ready(nfc);
333
334 if (ret)
335 return ret;
336
337 return ar934x_nfc_wait_dma_ready(nfc);
338 }
339
340 static int
341 ar934x_nfc_alloc_buf(struct ar934x_nfc *nfc, unsigned size)
342 {
343 nfc->buf = dma_alloc_coherent(nfc->parent, size,
344 &nfc->buf_dma, GFP_KERNEL);
345 if (nfc->buf == NULL) {
346 dev_err(nfc->parent, "no memory for DMA buffer\n");
347 return -ENOMEM;
348 }
349
350 nfc->buf_size = size;
351 nfc_dbg(nfc, "buf:%p size:%u\n", nfc->buf, nfc->buf_size);
352
353 return 0;
354 }
355
356 static void
357 ar934x_nfc_free_buf(struct ar934x_nfc *nfc)
358 {
359 dma_free_coherent(nfc->parent, nfc->buf_size, nfc->buf, nfc->buf_dma);
360 }
361
362 static void
363 ar934x_nfc_get_addr(struct ar934x_nfc *nfc, int column, int page_addr,
364 u32 *addr0, u32 *addr1)
365 {
366 u32 a0, a1;
367
368 a0 = 0;
369 a1 = 0;
370
371 if (column == -1) {
372 /* ERASE1 */
373 a0 = (page_addr & 0xffff) << 16;
374 a1 = (page_addr >> 16) & 0xf;
375 } else if (page_addr != -1) {
376 /* SEQIN, READ0, etc.. */
377
378 /* TODO: handle 16bit bus width */
379 if (nfc->small_page) {
380 a0 = column & 0xff;
381 a0 |= (page_addr & 0xff) << 8;
382 a0 |= ((page_addr >> 8) & 0xff) << 16;
383 a0 |= ((page_addr >> 16) & 0xff) << 24;
384 } else {
385 a0 = column & 0x0FFF;
386 a0 |= (page_addr & 0xffff) << 16;
387
388 if (nfc->addr_count0 > 4)
389 a1 = (page_addr >> 16) & 0xf;
390 }
391 }
392
393 *addr0 = a0;
394 *addr1 = a1;
395 }
396
397 static void
398 ar934x_nfc_send_cmd(struct ar934x_nfc *nfc, unsigned command)
399 {
400 u32 cmd_reg;
401
402 cmd_reg = AR934X_NFC_CMD_INPUT_SEL_SIU | AR934X_NFC_CMD_ADDR_SEL_0 |
403 AR934X_NFC_CMD_SEQ_1C;
404 cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
405
406 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
407 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
408
409 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
410 ar934x_nfc_wait_dev_ready(nfc);
411 }
412
413 static int
414 ar934x_nfc_do_rw_command(struct ar934x_nfc *nfc, int column, int page_addr,
415 int len, u32 cmd_reg, u32 ctrl_reg, bool write)
416 {
417 u32 addr0, addr1;
418 u32 dma_ctrl;
419 int dir;
420 int err;
421 int retries = 0;
422
423 WARN_ON(len & 3);
424
425 if (WARN_ON(len > nfc->buf_size))
426 dev_err(nfc->parent, "len=%d > buf_size=%d", len, nfc->buf_size);
427
428 if (write) {
429 dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE;
430 dir = DMA_TO_DEVICE;
431 } else {
432 dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_READ;
433 dir = DMA_FROM_DEVICE;
434 }
435
436 ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
437
438 dma_ctrl |= AR934X_NFC_DMA_CTRL_DMA_START |
439 (AR934X_NFC_DMA_CTRL_DMA_BURST_3 <<
440 AR934X_NFC_DMA_CTRL_DMA_BURST_S);
441
442 cmd_reg |= AR934X_NFC_CMD_INPUT_SEL_DMA | AR934X_NFC_CMD_ADDR_SEL_0;
443 ctrl_reg |= AR934X_NFC_CTRL_INT_EN;
444
445 nfc_dbg(nfc, "%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\n",
446 (write) ? "write" : "read",
447 addr0, addr1, len, cmd_reg, dma_ctrl, ctrl_reg);
448
449 retry:
450 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
451 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
452 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
453 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR, nfc->buf_dma);
454 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_COUNT, len);
455 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DATA_SIZE, len);
456 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
457 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_CTRL, dma_ctrl);
458
459 if (ar934x_nfc_use_irq(nfc)) {
460 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, AR934X_NFC_IRQ_MASK);
461 /* flush write */
462 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
463 }
464
465 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
466 err = ar934x_nfc_wait_done(nfc);
467 if (err) {
468 dev_dbg(nfc->parent, "%s operation stuck at page %d\n",
469 (write) ? "write" : "read", page_addr);
470
471 ar934x_nfc_restart(nfc);
472 if (retries++ < AR934X_NFC_DMA_RETRIES)
473 goto retry;
474
475 dev_err(nfc->parent, "%s operation failed on page %d\n",
476 (write) ? "write" : "read", page_addr);
477 }
478
479 return err;
480 }
481
482 static int
483 ar934x_nfc_send_readid(struct ar934x_nfc *nfc, unsigned command)
484 {
485 u32 cmd_reg;
486 int err;
487
488 nfc_dbg(nfc, "readid, cmd:%02x\n", command);
489
490 cmd_reg = AR934X_NFC_CMD_SEQ_1C1AXR;
491 cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
492
493 err = ar934x_nfc_do_rw_command(nfc, -1, -1, AR934X_NFC_ID_BUF_SIZE,
494 cmd_reg, nfc->ctrl_reg, false);
495
496 nfc_debug_data("[id] ", nfc->buf, AR934X_NFC_ID_BUF_SIZE);
497
498 return err;
499 }
500
501 static int
502 ar934x_nfc_send_read(struct ar934x_nfc *nfc, unsigned command, int column,
503 int page_addr, int len)
504 {
505 u32 cmd_reg;
506 int err;
507
508 nfc_dbg(nfc, "read, column=%d page=%d len=%d\n",
509 column, page_addr, len);
510
511 cmd_reg = (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
512
513 if (nfc->small_page) {
514 cmd_reg |= AR934X_NFC_CMD_SEQ_18;
515 } else {
516 cmd_reg |= NAND_CMD_READSTART << AR934X_NFC_CMD_CMD1_S;
517 cmd_reg |= AR934X_NFC_CMD_SEQ_1C5A1CXR;
518 }
519
520 err = ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
521 cmd_reg, nfc->ctrl_reg, false);
522
523 nfc_debug_data("[data] ", nfc->buf, len);
524
525 return err;
526 }
527
528 static void
529 ar934x_nfc_send_erase(struct ar934x_nfc *nfc, unsigned command, int column,
530 int page_addr)
531 {
532 u32 addr0, addr1;
533 u32 ctrl_reg;
534 u32 cmd_reg;
535
536 ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
537
538 ctrl_reg = nfc->ctrl_reg;
539 if (nfc->small_page) {
540 /* override number of address cycles for the erase command */
541 ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M <<
542 AR934X_NFC_CTRL_ADDR_CYCLE0_S);
543 ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M <<
544 AR934X_NFC_CTRL_ADDR_CYCLE1_S);
545 ctrl_reg &= ~(AR934X_NFC_CTRL_SMALL_PAGE);
546 ctrl_reg |= (nfc->addr_count0 + 1) <<
547 AR934X_NFC_CTRL_ADDR_CYCLE0_S;
548 }
549
550 cmd_reg = NAND_CMD_ERASE1 << AR934X_NFC_CMD_CMD0_S;
551 cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
552 cmd_reg |= AR934X_NFC_CMD_SEQ_ERASE;
553
554 nfc_dbg(nfc, "erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\n",
555 page_addr, addr0, addr1, cmd_reg, ctrl_reg);
556
557 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
558 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
559 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
560 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
561
562 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
563 ar934x_nfc_wait_dev_ready(nfc);
564 }
565
566 static int
567 ar934x_nfc_send_write(struct ar934x_nfc *nfc, unsigned command, int column,
568 int page_addr, int len)
569 {
570 u32 cmd_reg;
571
572 nfc_dbg(nfc, "write, column=%d page=%d len=%d\n",
573 column, page_addr, len);
574
575 nfc_debug_data("[data] ", nfc->buf, len);
576
577 cmd_reg = NAND_CMD_SEQIN << AR934X_NFC_CMD_CMD0_S;
578 cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
579 cmd_reg |= AR934X_NFC_CMD_SEQ_12;
580
581 return ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
582 cmd_reg, nfc->ctrl_reg, true);
583 }
584
585 static void
586 ar934x_nfc_read_status(struct ar934x_nfc *nfc)
587 {
588 u32 cmd_reg;
589 u32 status;
590
591 cmd_reg = NAND_CMD_STATUS << AR934X_NFC_CMD_CMD0_S;
592 cmd_reg |= AR934X_NFC_CMD_SEQ_S;
593
594 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
595 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
596
597 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
598 ar934x_nfc_wait_dev_ready(nfc);
599
600 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_READ_STATUS);
601
602 nfc_dbg(nfc, "read status, cmd:%08x status:%02x\n",
603 cmd_reg, (status & 0xff));
604
605 if (nfc->swap_dma)
606 nfc->buf[0 ^ 3] = status;
607 else
608 nfc->buf[0] = status;
609 }
610
611 static void
612 ar934x_nfc_cmdfunc(struct mtd_info *mtd, unsigned int command, int column,
613 int page_addr)
614 {
615 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
616
617 nfc->read_id = false;
618 if (command != NAND_CMD_PAGEPROG)
619 nfc->buf_index = 0;
620
621 switch (command) {
622 case NAND_CMD_RESET:
623 ar934x_nfc_send_cmd(nfc, command);
624 break;
625
626 case NAND_CMD_READID:
627 nfc->read_id = true;
628 ar934x_nfc_send_readid(nfc, command);
629 break;
630
631 case NAND_CMD_READ0:
632 case NAND_CMD_READ1:
633 if (nfc->small_page) {
634 ar934x_nfc_send_read(nfc, command, column, page_addr,
635 mtd->writesize + mtd->oobsize);
636 } else {
637 ar934x_nfc_send_read(nfc, command, 0, page_addr,
638 mtd->writesize + mtd->oobsize);
639 nfc->buf_index = column;
640 nfc->rndout_page_addr = page_addr;
641 nfc->rndout_read_cmd = command;
642 }
643 break;
644
645 case NAND_CMD_READOOB:
646 if (nfc->small_page)
647 ar934x_nfc_send_read(nfc, NAND_CMD_READOOB,
648 column, page_addr,
649 mtd->oobsize);
650 else
651 ar934x_nfc_send_read(nfc, NAND_CMD_READ0,
652 mtd->writesize, page_addr,
653 mtd->oobsize);
654 break;
655
656 case NAND_CMD_RNDOUT:
657 if (WARN_ON(nfc->small_page))
658 break;
659
660 /* emulate subpage read */
661 ar934x_nfc_send_read(nfc, nfc->rndout_read_cmd, 0,
662 nfc->rndout_page_addr,
663 mtd->writesize + mtd->oobsize);
664 nfc->buf_index = column;
665 break;
666
667 case NAND_CMD_ERASE1:
668 nfc->erase1_page_addr = page_addr;
669 break;
670
671 case NAND_CMD_ERASE2:
672 ar934x_nfc_send_erase(nfc, command, -1, nfc->erase1_page_addr);
673 break;
674
675 case NAND_CMD_STATUS:
676 ar934x_nfc_read_status(nfc);
677 break;
678
679 case NAND_CMD_SEQIN:
680 if (nfc->small_page) {
681 /* output read command */
682 if (column >= mtd->writesize) {
683 column -= mtd->writesize;
684 nfc->seqin_read_cmd = NAND_CMD_READOOB;
685 } else if (column < 256) {
686 nfc->seqin_read_cmd = NAND_CMD_READ0;
687 } else {
688 column -= 256;
689 nfc->seqin_read_cmd = NAND_CMD_READ1;
690 }
691 } else {
692 nfc->seqin_read_cmd = NAND_CMD_READ0;
693 }
694 nfc->seqin_column = column;
695 nfc->seqin_page_addr = page_addr;
696 break;
697
698 case NAND_CMD_PAGEPROG:
699 if (nfc->small_page)
700 ar934x_nfc_send_cmd(nfc, nfc->seqin_read_cmd);
701
702 ar934x_nfc_send_write(nfc, command, nfc->seqin_column,
703 nfc->seqin_page_addr,
704 nfc->buf_index);
705 break;
706
707 default:
708 dev_err(nfc->parent,
709 "unsupported command: %x, column:%d page_addr=%d\n",
710 command, column, page_addr);
711 break;
712 }
713 }
714
715 static int
716 ar934x_nfc_dev_ready(struct mtd_info *mtd)
717 {
718 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
719
720 return __ar934x_nfc_dev_ready(nfc);
721 }
722
723 static void
724 ar934x_nfc_select_chip(struct mtd_info *mtd, int chip_no)
725 {
726 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
727
728 if (nfc->select_chip)
729 nfc->select_chip(chip_no);
730 }
731
732 static u8
733 ar934x_nfc_read_byte(struct mtd_info *mtd)
734 {
735 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
736 u8 data;
737
738 WARN_ON(nfc->buf_index >= nfc->buf_size);
739
740 if (nfc->swap_dma || nfc->read_id)
741 data = nfc->buf[nfc->buf_index ^ 3];
742 else
743 data = nfc->buf[nfc->buf_index];
744
745 nfc->buf_index++;
746
747 return data;
748 }
749
750 static void
751 ar934x_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
752 {
753 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
754 int i;
755
756 WARN_ON(nfc->buf_index + len > nfc->buf_size);
757
758 if (nfc->swap_dma) {
759 for (i = 0; i < len; i++) {
760 nfc->buf[nfc->buf_index ^ 3] = buf[i];
761 nfc->buf_index++;
762 }
763 } else {
764 for (i = 0; i < len; i++) {
765 nfc->buf[nfc->buf_index] = buf[i];
766 nfc->buf_index++;
767 }
768 }
769 }
770
771 static void
772 ar934x_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
773 {
774 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
775 int buf_index;
776 int i;
777
778 WARN_ON(nfc->buf_index + len > nfc->buf_size);
779
780 buf_index = nfc->buf_index;
781
782 if (nfc->swap_dma || nfc->read_id) {
783 for (i = 0; i < len; i++) {
784 buf[i] = nfc->buf[buf_index ^ 3];
785 buf_index++;
786 }
787 } else {
788 for (i = 0; i < len; i++) {
789 buf[i] = nfc->buf[buf_index];
790 buf_index++;
791 }
792 }
793
794 nfc->buf_index = buf_index;
795 }
796
797 static void
798 ar934x_nfc_hw_init(struct ar934x_nfc *nfc)
799 {
800 struct ar934x_nfc_platform_data *pdata;
801
802 pdata = ar934x_nfc_get_platform_data(nfc);
803 if (pdata->hw_reset) {
804 pdata->hw_reset(true);
805 pdata->hw_reset(false);
806 }
807
808 /*
809 * setup timings
810 * TODO: make it configurable via platform data
811 */
812 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIME_SEQ,
813 AR934X_NFC_TIME_SEQ_DEFAULT);
814 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_ASYN,
815 AR934X_NFC_TIMINGS_ASYN_DEFAULT);
816 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_SYN,
817 AR934X_NFC_TIMINGS_SYN_DEFAULT);
818
819 /* disable WP on all chips, and select chip 0 */
820 ar934x_nfc_wr(nfc, AR934X_NFC_REG_MEM_CTRL, 0xff00);
821
822 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR_OFFS, 0);
823
824 /* initialize Control register */
825 nfc->ctrl_reg = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
826 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
827
828 if (nfc->small_page) {
829 /* Setup generic sequence register for small page reads. */
830 ar934x_nfc_wr(nfc, AR934X_NFC_REG_GEN_SEQ_CTRL,
831 AR934X_NFC_GENSEQ_SMALL_PAGE_READ);
832 }
833 }
834
835 static void
836 ar934x_nfc_restart(struct ar934x_nfc *nfc)
837 {
838 u32 ctrl_reg;
839
840 if (nfc->select_chip)
841 nfc->select_chip(-1);
842
843 ctrl_reg = nfc->ctrl_reg;
844 ar934x_nfc_hw_init(nfc);
845 nfc->ctrl_reg = ctrl_reg;
846
847 if (nfc->select_chip)
848 nfc->select_chip(0);
849
850 ar934x_nfc_send_cmd(nfc, NAND_CMD_RESET);
851 }
852
853 static irqreturn_t
854 ar934x_nfc_irq_handler(int irq, void *data)
855 {
856 struct ar934x_nfc *nfc = data;
857 u32 status;
858
859 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
860
861 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
862 /* flush write */
863 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
864
865 status &= ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
866 if (status) {
867 nfc_dbg(nfc, "got IRQ, status:%08x\n", status);
868
869 nfc->irq_status = status;
870 nfc->spurious_irq_expected = true;
871 wake_up(&nfc->irq_waitq);
872 } else {
873 if (nfc->spurious_irq_expected) {
874 nfc->spurious_irq_expected = false;
875 } else {
876 dev_warn(nfc->parent, "spurious interrupt\n");
877 }
878 }
879
880 return IRQ_HANDLED;
881 }
882
883 static int
884 ar934x_nfc_init_tail(struct mtd_info *mtd)
885 {
886 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
887 struct nand_chip *chip = &nfc->nand_chip;
888 u32 ctrl;
889 u32 t;
890 int err;
891
892 switch (mtd->oobsize) {
893 case 16:
894 case 64:
895 case 128:
896 ar934x_nfc_wr(nfc, AR934X_NFC_REG_SPARE_SIZE, mtd->oobsize);
897 break;
898
899 default:
900 dev_err(nfc->parent, "unsupported OOB size: %d bytes\n",
901 mtd->oobsize);
902 return -ENXIO;
903 }
904
905 ctrl = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
906
907 switch (mtd->erasesize / mtd->writesize) {
908 case 32:
909 t = AR934X_NFC_CTRL_BLOCK_SIZE_32;
910 break;
911
912 case 64:
913 t = AR934X_NFC_CTRL_BLOCK_SIZE_64;
914 break;
915
916 case 128:
917 t = AR934X_NFC_CTRL_BLOCK_SIZE_128;
918 break;
919
920 case 256:
921 t = AR934X_NFC_CTRL_BLOCK_SIZE_256;
922 break;
923
924 default:
925 dev_err(nfc->parent, "unsupported block size: %u\n",
926 mtd->erasesize / mtd->writesize);
927 return -ENXIO;
928 }
929
930 ctrl |= t << AR934X_NFC_CTRL_BLOCK_SIZE_S;
931
932 switch (mtd->writesize) {
933 case 256:
934 nfc->small_page = 1;
935 t = AR934X_NFC_CTRL_PAGE_SIZE_256;
936 break;
937
938 case 512:
939 nfc->small_page = 1;
940 t = AR934X_NFC_CTRL_PAGE_SIZE_512;
941 break;
942
943 case 1024:
944 t = AR934X_NFC_CTRL_PAGE_SIZE_1024;
945 break;
946
947 case 2048:
948 t = AR934X_NFC_CTRL_PAGE_SIZE_2048;
949 break;
950
951 case 4096:
952 t = AR934X_NFC_CTRL_PAGE_SIZE_4096;
953 break;
954
955 case 8192:
956 t = AR934X_NFC_CTRL_PAGE_SIZE_8192;
957 break;
958
959 case 16384:
960 t = AR934X_NFC_CTRL_PAGE_SIZE_16384;
961 break;
962
963 default:
964 dev_err(nfc->parent, "unsupported write size: %d bytes\n",
965 mtd->writesize);
966 return -ENXIO;
967 }
968
969 ctrl |= t << AR934X_NFC_CTRL_PAGE_SIZE_S;
970
971 if (nfc->small_page) {
972 ctrl |= AR934X_NFC_CTRL_SMALL_PAGE;
973
974 if (chip->chipsize > (32 << 20)) {
975 nfc->addr_count0 = 4;
976 nfc->addr_count1 = 3;
977 } else if (chip->chipsize > (2 << 16)) {
978 nfc->addr_count0 = 3;
979 nfc->addr_count1 = 2;
980 } else {
981 nfc->addr_count0 = 2;
982 nfc->addr_count1 = 1;
983 }
984 } else {
985 if (chip->chipsize > (128 << 20)) {
986 nfc->addr_count0 = 5;
987 nfc->addr_count1 = 3;
988 } else if (chip->chipsize > (8 << 16)) {
989 nfc->addr_count0 = 4;
990 nfc->addr_count1 = 2;
991 } else {
992 nfc->addr_count0 = 3;
993 nfc->addr_count1 = 1;
994 }
995 }
996
997 ctrl |= nfc->addr_count0 << AR934X_NFC_CTRL_ADDR_CYCLE0_S;
998 ctrl |= nfc->addr_count1 << AR934X_NFC_CTRL_ADDR_CYCLE1_S;
999
1000 nfc->ctrl_reg = ctrl;
1001 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
1002
1003 ar934x_nfc_free_buf(nfc);
1004 err = ar934x_nfc_alloc_buf(nfc, mtd->writesize + mtd->oobsize);
1005
1006 return err;
1007 }
1008
1009 static int
1010 ar934x_nfc_probe(struct platform_device *pdev)
1011 {
1012 static const char *part_probes[] = { "cmdlinepart", NULL, };
1013 struct ar934x_nfc_platform_data *pdata;
1014 struct ar934x_nfc *nfc;
1015 struct resource *res;
1016 struct mtd_info *mtd;
1017 struct nand_chip *nand;
1018 struct mtd_part_parser_data ppdata;
1019 int ret;
1020
1021 pdata = pdev->dev.platform_data;
1022 if (pdata == NULL) {
1023 dev_err(&pdev->dev, "no platform data defined\n");
1024 return -EINVAL;
1025 }
1026
1027 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1028 if (!res) {
1029 dev_err(&pdev->dev, "failed to get I/O memory\n");
1030 return -EINVAL;
1031 }
1032
1033 nfc = devm_kzalloc(&pdev->dev, sizeof(struct ar934x_nfc), GFP_KERNEL);
1034 if (!nfc) {
1035 dev_err(&pdev->dev, "failed to allocate driver data\n");
1036 return -ENOMEM;
1037 }
1038
1039 nfc->base = devm_ioremap_resource(&pdev->dev, res);
1040 if (IS_ERR(nfc->base)) {
1041 dev_err(&pdev->dev, "failed to remap I/O memory\n");
1042 return PTR_ERR(nfc->base);
1043 }
1044
1045 nfc->irq = platform_get_irq(pdev, 0);
1046 if (nfc->irq < 0) {
1047 dev_err(&pdev->dev, "no IRQ resource specified\n");
1048 return -EINVAL;
1049 }
1050
1051 init_waitqueue_head(&nfc->irq_waitq);
1052 ret = request_irq(nfc->irq, ar934x_nfc_irq_handler, IRQF_DISABLED,
1053 dev_name(&pdev->dev), nfc);
1054 if (ret) {
1055 dev_err(&pdev->dev, "requast_irq failed, err:%d\n", ret);
1056 return ret;
1057 }
1058
1059 nfc->parent = &pdev->dev;
1060 nfc->select_chip = pdata->select_chip;
1061 nfc->swap_dma = pdata->swap_dma;
1062
1063 nand = &nfc->nand_chip;
1064 mtd = &nfc->mtd;
1065
1066 mtd->priv = nand;
1067 mtd->owner = THIS_MODULE;
1068 if (pdata->name)
1069 mtd->name = pdata->name;
1070 else
1071 mtd->name = dev_name(&pdev->dev);
1072
1073 nand->chip_delay = 25;
1074 nand->ecc.mode = NAND_ECC_SOFT;
1075
1076 nand->dev_ready = ar934x_nfc_dev_ready;
1077 nand->cmdfunc = ar934x_nfc_cmdfunc;
1078 nand->read_byte = ar934x_nfc_read_byte;
1079 nand->write_buf = ar934x_nfc_write_buf;
1080 nand->read_buf = ar934x_nfc_read_buf;
1081 nand->select_chip = ar934x_nfc_select_chip;
1082
1083 ret = ar934x_nfc_alloc_buf(nfc, AR934X_NFC_ID_BUF_SIZE);
1084 if (ret)
1085 goto err_free_irq;
1086
1087 platform_set_drvdata(pdev, nfc);
1088
1089 ar934x_nfc_hw_init(nfc);
1090
1091 ret = nand_scan_ident(mtd, 1, NULL);
1092 if (ret) {
1093 dev_err(&pdev->dev, "nand_scan_ident failed, err:%d\n", ret);
1094 goto err_free_buf;
1095 }
1096
1097 ret = ar934x_nfc_init_tail(mtd);
1098 if (ret) {
1099 dev_err(&pdev->dev, "init tail failed, err:%d\n", ret);
1100 goto err_free_buf;
1101 }
1102
1103 if (pdata->scan_fixup) {
1104 ret = pdata->scan_fixup(mtd);
1105 if (ret)
1106 goto err_free_buf;
1107 }
1108
1109 ret = nand_scan_tail(mtd);
1110 if (ret) {
1111 dev_err(&pdev->dev, "scan tail failed, err:%d\n", ret);
1112 goto err_free_buf;
1113 }
1114
1115 memset(&ppdata, '\0', sizeof(ppdata));
1116 ret = mtd_device_parse_register(mtd, part_probes, &ppdata,
1117 pdata->parts, pdata->nr_parts);
1118 if (ret) {
1119 dev_err(&pdev->dev, "unable to register mtd, err:%d\n", ret);
1120 goto err_free_buf;
1121 }
1122
1123 return 0;
1124
1125 err_free_buf:
1126 ar934x_nfc_free_buf(nfc);
1127 err_free_irq:
1128 free_irq(nfc->irq, nfc);
1129 return ret;
1130 }
1131
1132 static int
1133 ar934x_nfc_remove(struct platform_device *pdev)
1134 {
1135 struct ar934x_nfc *nfc;
1136
1137 nfc = platform_get_drvdata(pdev);
1138 if (nfc) {
1139 nand_release(&nfc->mtd);
1140 ar934x_nfc_free_buf(nfc);
1141 free_irq(nfc->irq, nfc);
1142 }
1143
1144 return 0;
1145 }
1146
1147 static struct platform_driver ar934x_nfc_driver = {
1148 .probe = ar934x_nfc_probe,
1149 .remove = ar934x_nfc_remove,
1150 .driver = {
1151 .name = AR934X_NFC_DRIVER_NAME,
1152 .owner = THIS_MODULE,
1153 },
1154 };
1155
1156 module_platform_driver(ar934x_nfc_driver);
1157
1158 MODULE_LICENSE("GPL v2");
1159 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1160 MODULE_DESCRIPTION("Atheros AR934x NAND Flash Controller driver");
1161 MODULE_ALIAS("platform:" AR934X_NFC_DRIVER_NAME);
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