package/kernel/mac80211/patches/rt2x00/998-wifi-rt2x00-rework-MT7620-PA-LNA-RF-calibration.patch

   1 From: Shiji Yang <yangshiji66@outlook.com>
   2 Date: Tue, 25 Jul 2023 20:05:06 +0800
   3 Subject: [PATCH] wifi: rt2x00: rework MT7620 PA/LNA RF calibration
   4
   5 1. Move MT7620 PA/LNA calibration code to dedicated functions.
   6 2. For external PA/LNA devices, restore RF and BBP registers before
   7    R-Calibration.
   8 3. Do Rx DCOC calibration again before RXIQ calibration.
   9 4. Correct MAC_SYS_CTRL register RX mask to 0x08 in R-Calibration
  10    function. For MAC_SYS_CTRL register, Bit[2] controls MAC_TX_EN
  11    and Bit[3] controls MAC_RX_EN (Bit index starts from 0).
  12 5. Move the channel configuration code from rt2800_vco_calibration()
  13    to the rt2800_config_channel().
  14 6. Use MT7620 SOC specific AGC initial LNA value instead of the
  15    RT5592's value.
  16 7. Adjust the register operation sequence according to the vendor
  17    driver code. This may not be useful, but it can make things
  18    clearer when developers try to review it.
  19
  20 Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
  21 ---
  22  .../net/wireless/ralink/rt2x00/rt2800lib.c    | 306 ++++++++++--------
  23  drivers/net/wireless/ralink/rt2x00/rt2x00.h   |   6 +
  24  2 files changed, 182 insertions(+), 130 deletions(-)
  25
  26 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  27 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  28 @@ -3881,14 +3881,6 @@ static void rt2800_config_channel_rf7620
  29                 rfcsr |= tx_agc_fc;
  30                 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
  31         }
  32 -
  33 -       if (conf_is_ht40(conf)) {
  34 -               rt2800_bbp_glrt_write(rt2x00dev, 141, 0x10);
  35 -               rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2f);
  36 -       } else {
  37 -               rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1a);
  38 -               rt2800_bbp_glrt_write(rt2x00dev, 157, 0x40);
  39 -       }
  40  }
  41
  42  static void rt2800_config_alc_rt6352(struct rt2x00_dev *rt2x00dev,
  43 @@ -4457,89 +4449,63 @@ static void rt2800_config_channel(struct
  44                 usleep_range(1000, 1500);
  45         }
  46
  47 -       if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
  48 +       if (rt2x00_rt(rt2x00dev, RT5592)) {
  49                 reg = 0x10;
  50 -               if (!conf_is_ht40(conf)) {
  51 -                       if (rt2x00_rt(rt2x00dev, RT6352) &&
  52 -                           rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
  53 -                               reg |= 0x5;
  54 -                       } else {
  55 -                               reg |= 0xa;
  56 -                       }
  57 -               }
  58 +               if (!conf_is_ht40(conf))
  59 +                       reg |= 0xa;
  60                 rt2800_bbp_write(rt2x00dev, 195, 141);
  61                 rt2800_bbp_write(rt2x00dev, 196, reg);
  62
  63 -               /* AGC init.
  64 -                * Despite the vendor driver using different values here for
  65 -                * RT6352 chip, we use 0x1c for now. This may have to be changed
  66 -                * once TSSI got implemented.
  67 -                */
  68                 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain;
  69                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
  70 -
  71 -               if (rt2x00_rt(rt2x00dev, RT5592))
  72 -                       rt2800_iq_calibrate(rt2x00dev, rf->channel);
  73 +
  74 +               rt2800_iq_calibrate(rt2x00dev, rf->channel);
  75         }
  76
  77         if (rt2x00_rt(rt2x00dev, RT6352)) {
  78 -               if (test_bit(CAPABILITY_EXTERNAL_PA_TX0,
  79 -                            &rt2x00dev->cap_flags)) {
  80 -                       reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
  81 -                       reg |= 0x00000101;
  82 -                       rt2800_register_write(rt2x00dev, RF_CONTROL3, reg);
  83 -
  84 -                       reg = rt2800_register_read(rt2x00dev, RF_BYPASS3);
  85 -                       reg |= 0x00000101;
  86 -                       rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
  87 -
  88 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73);
  89 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73);
  90 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73);
  91 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
  92 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xC8);
  93 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xA4);
  94 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05);
  95 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
  96 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xC8);
  97 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xA4);
  98 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05);
  99 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27);
 100 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xC8);
 101 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xA4);
 102 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05);
 103 -                       rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00);
 104 +               /* BBP for GLRT BW */
 105 +               if (conf_is_ht40(conf)) {
 106 +                       rt2800_bbp_glrt_write(rt2x00dev, 141, 0x10);
 107 +                       rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2f);
 108 +               } else {
 109 +                       rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1a);
 110 +                       rt2800_bbp_glrt_write(rt2x00dev, 157, 0x40);
 111
 112 -                       rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
 113 -                                             0x36303636);
 114 -                       rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN,
 115 -                                             0x6C6C6B6C);
 116 -                       rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN,
 117 -                                             0x6C6C6B6C);
 118 +                       if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
 119 +                               rt2x00_has_cap_external_lna_bg(rt2x00dev))
 120 +                               rt2800_bbp_glrt_write(rt2x00dev, 141, 0x15);
 121                 }
 122
 123 -               if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 124 -                       reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
 125 -                       reg |= 0x00000101;
 126 -                       rt2800_register_write(rt2x00dev, RF_CONTROL3, reg);
 127 -
 128 -                       reg = rt2800_register_read(rt2x00dev, RF_BYPASS3);
 129 -                       reg |= 0x00000101;
 130 -                       rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
 131 -
 132 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x66);
 133 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x20);
 134 -                       rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x42);
 135 -                       rt2800_bbp_write(rt2x00dev, 75, 0x68);
 136 -                       rt2800_bbp_write(rt2x00dev, 76, 0x4C);
 137 -                       rt2800_bbp_write(rt2x00dev, 79, 0x1C);
 138 -                       rt2800_bbp_write(rt2x00dev, 80, 0x0C);
 139 -                       rt2800_bbp_write(rt2x00dev, 82, 0xB6);
 140 -                       /* bank 0 RF reg 42 and glrt BBP reg 141 will be set in
 141 -                        * config channel function in dependence of channel and
 142 -                        * HT20/HT40 so don't touch it
 143 -                        */
 144 +               if (rt2x00dev->default_ant.rx_chain_num == 1) {
 145 +                       rt2800_bbp_write(rt2x00dev, 91, 0x07);
 146 +                       rt2800_bbp_write(rt2x00dev, 95, 0x1A);
 147 +                       rt2800_bbp_write(rt2x00dev, 195, 128);
 148 +                       rt2800_bbp_write(rt2x00dev, 196, 0xA0);
 149 +                       rt2800_bbp_write(rt2x00dev, 195, 170);
 150 +                       rt2800_bbp_write(rt2x00dev, 196, 0x12);
 151 +                       rt2800_bbp_write(rt2x00dev, 195, 171);
 152 +                       rt2800_bbp_write(rt2x00dev, 196, 0x10);
 153 +               } else {
 154 +                       rt2800_bbp_write(rt2x00dev, 91, 0x06);
 155 +                       rt2800_bbp_write(rt2x00dev, 95, 0x9A);
 156 +                       rt2800_bbp_write(rt2x00dev, 195, 128);
 157 +                       rt2800_bbp_write(rt2x00dev, 196, 0xE0);
 158 +                       rt2800_bbp_write(rt2x00dev, 195, 170);
 159 +                       rt2800_bbp_write(rt2x00dev, 196, 0x30);
 160 +                       rt2800_bbp_write(rt2x00dev, 195, 171);
 161 +                       rt2800_bbp_write(rt2x00dev, 196, 0x30);
 162                 }
 163 +
 164 +               /* AGC init */
 165 +               reg = rf->channel <= 14 ? 0x04 + 2 * rt2x00dev->lna_gain : 0;
 166 +               rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
 167 +
 168 +               /* On 11A, We should delay and wait RF/BBP to be stable
 169 +                * and the appropriate time should be 1000 micro seconds
 170 +                * 2005/06/05 - On 11G, we also need this delay time.
 171 +                * Otherwise it's difficult to pass the WHQL.
 172 +                */
 173 +               usleep_range(1000, 1500);
 174         }
 175
 176         bbp = rt2800_bbp_read(rt2x00dev, 4);
 177 @@ -5649,43 +5615,6 @@ void rt2800_vco_calibration(struct rt2x0
 178                 }
 179         }
 180         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 181 -
 182 -       if (rt2x00_rt(rt2x00dev, RT6352)) {
 183 -               if (rt2x00dev->default_ant.rx_chain_num == 1) {
 184 -                       rt2800_bbp_write(rt2x00dev, 91, 0x07);
 185 -                       rt2800_bbp_write(rt2x00dev, 95, 0x1A);
 186 -                       rt2800_bbp_write(rt2x00dev, 195, 128);
 187 -                       rt2800_bbp_write(rt2x00dev, 196, 0xA0);
 188 -                       rt2800_bbp_write(rt2x00dev, 195, 170);
 189 -                       rt2800_bbp_write(rt2x00dev, 196, 0x12);
 190 -                       rt2800_bbp_write(rt2x00dev, 195, 171);
 191 -                       rt2800_bbp_write(rt2x00dev, 196, 0x10);
 192 -               } else {
 193 -                       rt2800_bbp_write(rt2x00dev, 91, 0x06);
 194 -                       rt2800_bbp_write(rt2x00dev, 95, 0x9A);
 195 -                       rt2800_bbp_write(rt2x00dev, 195, 128);
 196 -                       rt2800_bbp_write(rt2x00dev, 196, 0xE0);
 197 -                       rt2800_bbp_write(rt2x00dev, 195, 170);
 198 -                       rt2800_bbp_write(rt2x00dev, 196, 0x30);
 199 -                       rt2800_bbp_write(rt2x00dev, 195, 171);
 200 -                       rt2800_bbp_write(rt2x00dev, 196, 0x30);
 201 -               }
 202 -
 203 -               if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 204 -                       rt2800_bbp_write(rt2x00dev, 75, 0x68);
 205 -                       rt2800_bbp_write(rt2x00dev, 76, 0x4C);
 206 -                       rt2800_bbp_write(rt2x00dev, 79, 0x1C);
 207 -                       rt2800_bbp_write(rt2x00dev, 80, 0x0C);
 208 -                       rt2800_bbp_write(rt2x00dev, 82, 0xB6);
 209 -               }
 210 -
 211 -               /* On 11A, We should delay and wait RF/BBP to be stable
 212 -                * and the appropriate time should be 1000 micro seconds
 213 -                * 2005/06/05 - On 11G, we also need this delay time.
 214 -                * Otherwise it's difficult to pass the WHQL.
 215 -                */
 216 -               usleep_range(1000, 1500);
 217 -       }
 218  }
 219  EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
 220
 221 @@ -8650,7 +8579,7 @@ static void rt2800_r_calibration(struct
 222                 rt2x00_warn(rt2x00dev, "Wait MAC Tx Status to MAX !!!\n");
 223
 224         maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
 225 -       maccfg &= (~0x04);
 226 +       maccfg &= (~0x08);
 227         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);
 228
 229         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
 230 @@ -10686,30 +10615,143 @@ static void rt2800_init_rfcsr_6352(struc
 231                 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
 232                 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
 233         }
 234 +}
 235
 236 -       rt6352_enable_pa_pin(rt2x00dev, 0);
 237 -       rt2800_r_calibration(rt2x00dev);
 238 -       rt2800_rf_self_txdc_cal(rt2x00dev);
 239 -       rt2800_rxdcoc_calibration(rt2x00dev);
 240 -       rt2800_bw_filter_calibration(rt2x00dev, true);
 241 -       rt2800_bw_filter_calibration(rt2x00dev, false);
 242 -       rt2800_loft_iq_calibration(rt2x00dev);
 243 -       rt2800_rxiq_calibration(rt2x00dev);
 244 -       rt6352_enable_pa_pin(rt2x00dev, 1);
 245 +static void rt2800_init_palna_rt6352(struct rt2x00_dev *rt2x00dev)
 246 +{
 247 +       u32 reg;
 248 +
 249 +       if (rt2x00_has_cap_external_pa(rt2x00dev)) {
 250 +               reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
 251 +               reg |= 0x00000101;
 252 +               rt2800_register_write(rt2x00dev, RF_CONTROL3, reg);
 253 +
 254 +               reg = rt2800_register_read(rt2x00dev, RF_BYPASS3);
 255 +               reg |= 0x00000101;
 256 +               rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
 257 +       }
 258
 259 -       if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 260 +       if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
 261 +           rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 262                 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x66);
 263                 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x20);
 264                 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x42);
 265 +       }
 266 +
 267 +       if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
 268 +           rt2x00_has_cap_external_pa(rt2x00dev)) {
 269 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73);
 270 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73);
 271 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73);
 272 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
 273 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xC8);
 274 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xA4);
 275 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05);
 276 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
 277 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xC8);
 278 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xA4);
 279 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05);
 280 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27);
 281 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xC8);
 282 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xA4);
 283 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05);
 284 +       }
 285 +
 286 +       if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
 287 +           rt2x00_has_cap_external_pa(rt2x00dev))
 288 +               rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00);
 289 +
 290 +       if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
 291 +           rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 292                 rt2800_bbp_write(rt2x00dev, 75, 0x68);
 293                 rt2800_bbp_write(rt2x00dev, 76, 0x4C);
 294                 rt2800_bbp_write(rt2x00dev, 79, 0x1C);
 295                 rt2800_bbp_write(rt2x00dev, 80, 0x0C);
 296                 rt2800_bbp_write(rt2x00dev, 82, 0xB6);
 297 -               /* bank 0 RF reg 42 and glrt BBP reg 141 will be set in config
 298 -                * channel function in dependence of channel and HT20/HT40,
 299 -                * so don't touch them here.
 300 -                */
 301 +       }
 302 +
 303 +       if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
 304 +           rt2x00_has_cap_external_pa(rt2x00dev)) {
 305 +               rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 0x36303636);
 306 +               rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C6B6C);
 307 +               rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C6B6C);
 308 +       }
 309 +}
 310 +
 311 +static void rt2800_restore_rf_bbp_rt6352(struct rt2x00_dev *rt2x00dev)
 312 +{
 313 +       if (rt2x00_has_cap_external_pa(rt2x00dev)) {
 314 +               rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0);
 315 +               rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0);
 316 +       }
 317 +
 318 +       if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
 319 +           rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 320 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
 321 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
 322 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
 323 +       }
 324 +
 325 +       if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
 326 +           rt2x00_has_cap_external_pa(rt2x00dev)) {
 327 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
 328 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
 329 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
 330 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
 331 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
 332 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
 333 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
 334 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
 335 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
 336 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
 337 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
 338 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
 339 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
 340 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
 341 +               rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
 342 +       }
 343 +
 344 +       if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
 345 +           rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 346 +               rt2800_bbp_write(rt2x00dev, 75, 0x60);
 347 +               rt2800_bbp_write(rt2x00dev, 76, 0x44);
 348 +               rt2800_bbp_write(rt2x00dev, 79, 0x1C);
 349 +               rt2800_bbp_write(rt2x00dev, 80, 0x0C);
 350 +               rt2800_bbp_write(rt2x00dev, 82, 0xB6);
 351 +       }
 352 +
 353 +       if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
 354 +           rt2x00_has_cap_external_pa(rt2x00dev)) {
 355 +               rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 0x3630363A);
 356 +               rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
 357 +               rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
 358 +       }
 359 +}
 360 +
 361 +static void rt2800_calibration_rt6352(struct rt2x00_dev *rt2x00dev)
 362 +{
 363 +       if (rt2x00_has_cap_external_pa(rt2x00dev) ||
 364 +           rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 365 +               rt6352_enable_pa_pin(rt2x00dev, 0);
 366 +               rt2800_restore_rf_bbp_rt6352(rt2x00dev);
 367 +       }
 368 +
 369 +       rt2800_r_calibration(rt2x00dev);
 370 +       rt2800_rf_self_txdc_cal(rt2x00dev);
 371 +       rt2800_rxdcoc_calibration(rt2x00dev);
 372 +       rt2800_bw_filter_calibration(rt2x00dev, true);
 373 +       rt2800_bw_filter_calibration(rt2x00dev, false);
 374 +       rt2800_loft_iq_calibration(rt2x00dev);
 375 +
 376 +       /* missing DPD Calibration for devices using internal PA */
 377 +
 378 +       rt2800_rxdcoc_calibration(rt2x00dev);
 379 +       rt2800_rxiq_calibration(rt2x00dev);
 380 +
 381 +       if (rt2x00_has_cap_external_pa(rt2x00dev) ||
 382 +          rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
 383 +               rt6352_enable_pa_pin(rt2x00dev, 1);
 384 +               rt2800_init_palna_rt6352(rt2x00dev);
 385         }
 386  }
 387
 388 @@ -10802,6 +10844,10 @@ int rt2800_enable_radio(struct rt2x00_de
 389         rt2800_init_bbp(rt2x00dev);
 390         rt2800_init_rfcsr(rt2x00dev);
 391
 392 +       /* Do calibration and init PA/LNA for RT6352 */
 393 +       if (rt2x00_rt(rt2x00dev, RT6352))
 394 +               rt2800_calibration_rt6352(rt2x00dev);
 395 +
 396         if (rt2x00_is_usb(rt2x00dev) &&
 397             (rt2x00_rt(rt2x00dev, RT3070) ||
 398              rt2x00_rt(rt2x00dev, RT3071) ||
 399 --- a/drivers/net/wireless/ralink/rt2x00/rt2x00.h
 400 +++ b/drivers/net/wireless/ralink/rt2x00/rt2x00.h
 401 @@ -1272,6 +1272,12 @@ rt2x00_has_cap_external_lna_bg(struct rt
 402  }
 403
 404  static inline bool
 405 +rt2x00_has_cap_external_pa(struct rt2x00_dev *rt2x00dev)
 406 +{
 407 +       return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_EXTERNAL_PA_TX0);
 408 +}
 409 +
 410 +static inline bool
 411  rt2x00_has_cap_double_antenna(struct rt2x00_dev *rt2x00dev)
 412  {
 413         return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_DOUBLE_ANTENNA);