package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ar9.c

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_atm_ar9.c
   4 ** PROJECT      : UEIP
   5 ** MODULES      : ATM
   6 **
   7 ** DATE         : 7 Jul 2009
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : ATM driver common source file (core functions)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 ** 07 JUL 2009  Xu Liang        Init Version
  22 *******************************************************************************/
  23
  24
  25
  26 /*
  27  * ####################################
  28  *              Head File
  29  * ####################################
  30  */
  31
  32 /*
  33  *  Common Head File
  34  */
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/version.h>
  38 #include <linux/types.h>
  39 #include <linux/errno.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/init.h>
  42 #include <linux/ioctl.h>
  43 #include <linux/platform_device.h>
  44 #include <asm/delay.h>
  45
  46 /*
  47  *  Chip Specific Head File
  48  */
  49 #include "ifxmips_atm_core.h"
  50
  51 #include "ifxmips_atm_fw_ar9.h"
  52 #include "ifxmips_atm_fw_regs_ar9.h"
  53
  54 #include <lantiq_soc.h>
  55
  56
  57
  58 /*
  59  * ####################################
  60  *              Definition
  61  * ####################################
  62  */
  63
  64 /*
  65  *  EMA Settings
  66  */
  67 #define EMA_CMD_BUF_LEN      0x0040
  68 #define EMA_CMD_BASE_ADDR    (0x00003B80 << 2)
  69 #define EMA_DATA_BUF_LEN     0x0100
  70 #define EMA_DATA_BASE_ADDR   (0x00003C00 << 2)
  71 #define EMA_WRITE_BURST      0x2
  72 #define EMA_READ_BURST       0x2
  73
  74
  75
  76 /*
  77  * ####################################
  78  *             Declaration
  79  * ####################################
  80  */
  81
  82 /*
  83  *  Hardware Init/Uninit Functions
  84  */
  85 static inline void init_pmu(void);
  86 static inline void uninit_pmu(void);
  87 static inline void reset_ppe(struct platform_device *pdev);
  88 static inline void init_ema(void);
  89 static inline void init_mailbox(void);
  90 static inline void clear_share_buffer(void);
  91
  92
  93
  94 /*
  95  * ####################################
  96  *            Local Variable
  97  * ####################################
  98  */
  99
 100
 101
 102 /*
 103  * ####################################
 104  *            Local Function
 105  * ####################################
 106  */
 107
 108 #define IFX_PMU_MODULE_PPE_SLL01  BIT(19)
 109 #define IFX_PMU_MODULE_PPE_TC     BIT(21)
 110 #define IFX_PMU_MODULE_PPE_EMA    BIT(22)
 111 #define IFX_PMU_MODULE_PPE_QSB    BIT(18)
 112 #define IFX_PMU_MODULE_TPE       BIT(13)
 113 #define IFX_PMU_MODULE_DSL_DFE    BIT(9)
 114
 115 static inline void init_pmu(void)
 116 {
 117         ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
 118                 IFX_PMU_MODULE_PPE_TC |
 119                 IFX_PMU_MODULE_PPE_EMA |
 120                 IFX_PMU_MODULE_PPE_QSB |
 121                 IFX_PMU_MODULE_TPE |
 122                 IFX_PMU_MODULE_DSL_DFE);
 123 }
 124
 125 static inline void uninit_pmu(void)
 126 {
 127 }
 128
 129 static inline void reset_ppe(struct platform_device *pdev)
 130 {
 131 #ifdef MODULE
 132     //  reset PPE
 133 //    ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
 134 #endif
 135 }
 136
 137 static inline void init_ema(void)
 138 {
 139     IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
 140     IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
 141     IFX_REG_W32(0x000000FF, EMA_IER);
 142     IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
 143 }
 144
 145 static inline void init_mailbox(void)
 146 {
 147     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
 148     IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
 149     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
 150     IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
 151 }
 152
 153 static inline void clear_share_buffer(void)
 154 {
 155     volatile u32 *p = SB_RAM0_ADDR(0);
 156     unsigned int i;
 157
 158     for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN + SB_RAM4_DWLEN; i++ )
 159         IFX_REG_W32(0, p++);
 160 }
 161
 162 static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
 163 {
 164     volatile u32 *dest;
 165
 166     if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
 167         || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
 168         return -1;
 169
 170     if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
 171         IFX_REG_W32(0x00, CDM_CFG);
 172     else
 173         IFX_REG_W32(0x04, CDM_CFG);
 174
 175     /*  copy code   */
 176     dest = CDM_CODE_MEMORY(0, 0);
 177     while ( code_dword_len-- > 0 )
 178         IFX_REG_W32(*code_src++, dest++);
 179
 180     /*  copy data   */
 181     dest = CDM_DATA_MEMORY(0, 0);
 182     while ( data_dword_len-- > 0 )
 183         IFX_REG_W32(*data_src++, dest++);
 184
 185     return 0;
 186 }
 187
 188 void ar9_fw_ver(unsigned int *major, unsigned int *minor)
 189 {
 190     ASSERT(major != NULL, "pointer is NULL");
 191     ASSERT(minor != NULL, "pointer is NULL");
 192
 193     *major = FW_VER_ID->major;
 194     *minor = FW_VER_ID->minor;
 195 }
 196
 197 void ar9_init(struct platform_device *pdev)
 198 {
 199         init_pmu();
 200         reset_ppe(pdev);
 201         init_ema();
 202         init_mailbox();
 203         clear_share_buffer();
 204 }
 205
 206 void ar9_shutdown(void)
 207 {
 208         ltq_pmu_disable(IFX_PMU_MODULE_PPE_SLL01 |
 209                 IFX_PMU_MODULE_PPE_TC |
 210                 IFX_PMU_MODULE_PPE_EMA |
 211                 IFX_PMU_MODULE_PPE_QSB |
 212                 IFX_PMU_MODULE_TPE |
 213                 IFX_PMU_MODULE_DSL_DFE);
 214 }
 215
 216 int ar9_start(int pp32)
 217 {
 218         int ret;
 219
 220         ret = pp32_download_code(ar9_fw_bin, sizeof(ar9_fw_bin) / sizeof(*ar9_fw_bin),
 221                         ar9_fw_data, sizeof(ar9_fw_data) / sizeof(*ar9_fw_data));
 222         if ( ret != 0 )
 223                 return ret;
 224
 225         IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL(0));
 226
 227         udelay(10);
 228
 229         return 0;
 230 }
 231
 232 void ar9_stop(int pp32)
 233 {
 234         IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL(0));
 235 }
 236
 237 struct ltq_atm_ops ar9_ops = {
 238         .init = ar9_init,
 239         .shutdown = ar9_shutdown,
 240         .start = ar9_start,
 241         .stop = ar9_stop,
 242         .fw_ver = ar9_fw_ver,
 243 };
 244
 245