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uboot-rockchip: add NanoPi R5S support
[openwrt/staging/hauke.git] / package / boot / uboot-rockchip / patches / 103-rockchip-rk3568-Add-support-for-FriendlyARM-NanoPi-R.patch
1 From c84214aab0e4c5b2f619dd89655f27b3ae40e82b Mon Sep 17 00:00:00 2001
2 From: Tianling Shen <cnsztl@gmail.com>
3 Date: Tue, 30 May 2023 15:00:33 +0800
4 Subject: [PATCH] rockchip: rk3568: Add support for FriendlyARM NanoPi R5S
5
6 FriendlyARM NanoPi R5S is an open-sourced mini IoT gateway device.
7
8 Board Specifications
9 - Rockchip RK3568
10 - 2 or 4GB LPDDR4X
11 - 8GB or 16GB eMMC, SD card slot
12 - GbE LAN (Native)
13 - 2x 2.5G LAN (PCIe)
14 - M.2 Connector
15 - HDMI 2.0, MIPI DSI/CSI
16 - 2xUSB 3.0 Host
17 - USB Type C PD, 5V/9V/12V
18 - GPIO: 12-pin 0.5mm FPC connector
19
20 The device tree is taken from kernel v6.4-rc1.
21
22 Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
23 Signed-off-by: Tianling Shen <cnsztl@gmail.com>
24 ---
25 arch/arm/dts/Makefile | 1 +
26 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 31 ++
27 arch/arm/dts/rk3568-nanopi-r5s.dts | 136 +++++
28 arch/arm/dts/rk3568-nanopi-r5s.dtsi | 590 +++++++++++++++++++++
29 board/rockchip/evb_rk3568/MAINTAINERS | 8 +
30 configs/nanopi-r5s-rk3568_defconfig | 85 +++
31 6 files changed, 851 insertions(+)
32 create mode 100644 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
33 create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts
34 create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dtsi
35 create mode 100644 configs/nanopi-r5s-rk3568_defconfig
36
37 --- a/arch/arm/dts/Makefile
38 +++ b/arch/arm/dts/Makefile
39 @@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
40 rk3566-anbernic-rgxx3.dtb \
41 rk3566-radxa-cm3-io.dtb \
42 rk3568-evb.dtb \
43 + rk3568-nanopi-r5s.dtb \
44 rk3568-rock-3a.dtb
45
46 dtb-$(CONFIG_ROCKCHIP_RK3588) += \
47 --- /dev/null
48 +++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
49 @@ -0,0 +1,31 @@
50 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
51 +/*
52 + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
53 + * (http://www.friendlyelec.com)
54 + *
55 + * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
56 + */
57 +
58 +#include "rk356x-u-boot.dtsi"
59 +
60 +/ {
61 + chosen {
62 + stdout-path = &uart2;
63 + u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
64 + };
65 +};
66 +
67 +&sdhci {
68 + cap-mmc-highspeed;
69 + mmc-ddr-1_8v;
70 + mmc-hs200-1_8v;
71 + mmc-hs400-1_8v;
72 + mmc-hs400-enhanced-strobe;
73 + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
74 +};
75 +
76 +&uart2 {
77 + clock-frequency = <24000000>;
78 + bootph-all;
79 + status = "okay";
80 +};
81 --- /dev/null
82 +++ b/arch/arm/dts/rk3568-nanopi-r5s.dts
83 @@ -0,0 +1,136 @@
84 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
85 +/*
86 + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
87 + * (http://www.friendlyelec.com)
88 + *
89 + * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
90 + */
91 +
92 +/dts-v1/;
93 +#include "rk3568-nanopi-r5s.dtsi"
94 +
95 +/ {
96 + model = "FriendlyElec NanoPi R5S";
97 + compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
98 +
99 + aliases {
100 + ethernet0 = &gmac0;
101 + };
102 +
103 + gpio-leds {
104 + compatible = "gpio-leds";
105 + pinctrl-names = "default";
106 + pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;
107 +
108 + led-lan1 {
109 + color = <LED_COLOR_ID_GREEN>;
110 + function = LED_FUNCTION_LAN;
111 + function-enumerator = <1>;
112 + gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
113 + };
114 +
115 + led-lan2 {
116 + color = <LED_COLOR_ID_GREEN>;
117 + function = LED_FUNCTION_LAN;
118 + function-enumerator = <2>;
119 + gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
120 + };
121 +
122 + power_led: led-power {
123 + color = <LED_COLOR_ID_RED>;
124 + function = LED_FUNCTION_POWER;
125 + linux,default-trigger = "heartbeat";
126 + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
127 + };
128 +
129 + led-wan {
130 + color = <LED_COLOR_ID_GREEN>;
131 + function = LED_FUNCTION_WAN;
132 + gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
133 + };
134 + };
135 +};
136 +
137 +&gmac0 {
138 + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
139 + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
140 + assigned-clock-rates = <0>, <125000000>;
141 + clock_in_out = "output";
142 + phy-handle = <&rgmii_phy0>;
143 + phy-mode = "rgmii";
144 + pinctrl-names = "default";
145 + pinctrl-0 = <&gmac0_miim
146 + &gmac0_tx_bus2
147 + &gmac0_rx_bus2
148 + &gmac0_rgmii_clk
149 + &gmac0_rgmii_bus>;
150 + snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
151 + snps,reset-active-low;
152 + /* Reset time is 15ms, 50ms for rtl8211f */
153 + snps,reset-delays-us = <0 15000 50000>;
154 + tx_delay = <0x3c>;
155 + rx_delay = <0x2f>;
156 + status = "okay";
157 +};
158 +
159 +&mdio0 {
160 + rgmii_phy0: ethernet-phy@1 {
161 + compatible = "ethernet-phy-ieee802.3-c22";
162 + reg = <1>;
163 + pinctrl-0 = <&eth_phy0_reset_pin>;
164 + pinctrl-names = "default";
165 + };
166 +};
167 +
168 +&pcie2x1 {
169 + num-lanes = <1>;
170 + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
171 + status = "okay";
172 +};
173 +
174 +&pcie30phy {
175 + data-lanes = <1 2>;
176 + status = "okay";
177 +};
178 +
179 +&pcie3x1 {
180 + num-lanes = <1>;
181 + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
182 + vpcie3v3-supply = <&vcc3v3_pcie>;
183 + status = "okay";
184 +};
185 +
186 +&pcie3x2 {
187 + num-lanes = <1>;
188 + num-ib-windows = <8>;
189 + num-ob-windows = <8>;
190 + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
191 + vpcie3v3-supply = <&vcc3v3_pcie>;
192 + status = "okay";
193 +};
194 +
195 +&pinctrl {
196 + gmac0 {
197 + eth_phy0_reset_pin: eth-phy0-reset-pin {
198 + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
199 + };
200 + };
201 +
202 + gpio-leds {
203 + lan1_led_pin: lan1-led-pin {
204 + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
205 + };
206 +
207 + lan2_led_pin: lan2-led-pin {
208 + rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
209 + };
210 +
211 + power_led_pin: power-led-pin {
212 + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
213 + };
214 +
215 + wan_led_pin: wan-led-pin {
216 + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
217 + };
218 + };
219 +};
220 --- /dev/null
221 +++ b/arch/arm/dts/rk3568-nanopi-r5s.dtsi
222 @@ -0,0 +1,590 @@
223 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
224 +/*
225 + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
226 + * (http://www.friendlyelec.com)
227 + *
228 + * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
229 + */
230 +
231 +/dts-v1/;
232 +#include <dt-bindings/gpio/gpio.h>
233 +#include <dt-bindings/input/input.h>
234 +#include <dt-bindings/leds/common.h>
235 +#include <dt-bindings/pinctrl/rockchip.h>
236 +#include <dt-bindings/soc/rockchip,vop2.h>
237 +#include "rk3568.dtsi"
238 +
239 +/ {
240 + aliases {
241 + mmc0 = &sdmmc0;
242 + mmc1 = &sdhci;
243 + };
244 +
245 + chosen: chosen {
246 + stdout-path = "serial2:1500000n8";
247 + };
248 +
249 + hdmi-con {
250 + compatible = "hdmi-connector";
251 + type = "a";
252 +
253 + port {
254 + hdmi_con_in: endpoint {
255 + remote-endpoint = <&hdmi_out_con>;
256 + };
257 + };
258 + };
259 +
260 + vdd_usbc: vdd-usbc-regulator {
261 + compatible = "regulator-fixed";
262 + regulator-name = "vdd_usbc";
263 + regulator-always-on;
264 + regulator-boot-on;
265 + regulator-min-microvolt = <5000000>;
266 + regulator-max-microvolt = <5000000>;
267 + };
268 +
269 + vcc3v3_sys: vcc3v3-sys-regulator {
270 + compatible = "regulator-fixed";
271 + regulator-name = "vcc3v3_sys";
272 + regulator-always-on;
273 + regulator-boot-on;
274 + regulator-min-microvolt = <3300000>;
275 + regulator-max-microvolt = <3300000>;
276 + vin-supply = <&vdd_usbc>;
277 + };
278 +
279 + vcc5v0_sys: vcc5v0-sys-regulator {
280 + compatible = "regulator-fixed";
281 + regulator-name = "vcc5v0_sys";
282 + regulator-always-on;
283 + regulator-boot-on;
284 + regulator-min-microvolt = <5000000>;
285 + regulator-max-microvolt = <5000000>;
286 + vin-supply = <&vdd_usbc>;
287 + };
288 +
289 + vcc3v3_pcie: vcc3v3-pcie-regulator {
290 + compatible = "regulator-fixed";
291 + regulator-name = "vcc3v3_pcie";
292 + regulator-min-microvolt = <3300000>;
293 + regulator-max-microvolt = <3300000>;
294 + enable-active-high;
295 + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
296 + startup-delay-us = <200000>;
297 + vin-supply = <&vcc5v0_sys>;
298 + };
299 +
300 + vcc5v0_usb: vcc5v0-usb-regulator {
301 + compatible = "regulator-fixed";
302 + regulator-name = "vcc5v0_usb";
303 + regulator-always-on;
304 + regulator-boot-on;
305 + regulator-min-microvolt = <5000000>;
306 + regulator-max-microvolt = <5000000>;
307 + vin-supply = <&vdd_usbc>;
308 + };
309 +
310 + vcc5v0_usb_host: vcc5v0-usb-host-regulator {
311 + compatible = "regulator-fixed";
312 + enable-active-high;
313 + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
314 + pinctrl-names = "default";
315 + pinctrl-0 = <&vcc5v0_usb_host_en>;
316 + regulator-name = "vcc5v0_usb_host";
317 + regulator-always-on;
318 + regulator-boot-on;
319 + regulator-min-microvolt = <5000000>;
320 + regulator-max-microvolt = <5000000>;
321 + vin-supply = <&vcc5v0_usb>;
322 + };
323 +
324 + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
325 + compatible = "regulator-fixed";
326 + enable-active-high;
327 + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
328 + pinctrl-names = "default";
329 + pinctrl-0 = <&vcc5v0_usb_otg_en>;
330 + regulator-name = "vcc5v0_usb_otg";
331 + regulator-min-microvolt = <5000000>;
332 + regulator-max-microvolt = <5000000>;
333 + vin-supply = <&vcc5v0_usb>;
334 + };
335 +
336 + pcie30_avdd0v9: pcie30-avdd0v9-regulator {
337 + compatible = "regulator-fixed";
338 + regulator-name = "pcie30_avdd0v9";
339 + regulator-always-on;
340 + regulator-boot-on;
341 + regulator-min-microvolt = <900000>;
342 + regulator-max-microvolt = <900000>;
343 + vin-supply = <&vcc3v3_sys>;
344 + };
345 +
346 + pcie30_avdd1v8: pcie30-avdd1v8-regulator {
347 + compatible = "regulator-fixed";
348 + regulator-name = "pcie30_avdd1v8";
349 + regulator-always-on;
350 + regulator-boot-on;
351 + regulator-min-microvolt = <1800000>;
352 + regulator-max-microvolt = <1800000>;
353 + vin-supply = <&vcc3v3_sys>;
354 + };
355 +};
356 +
357 +&combphy0 {
358 + status = "okay";
359 +};
360 +
361 +&combphy1 {
362 + status = "okay";
363 +};
364 +
365 +&combphy2 {
366 + status = "okay";
367 +};
368 +
369 +&cpu0 {
370 + cpu-supply = <&vdd_cpu>;
371 +};
372 +
373 +&cpu1 {
374 + cpu-supply = <&vdd_cpu>;
375 +};
376 +
377 +&cpu2 {
378 + cpu-supply = <&vdd_cpu>;
379 +};
380 +
381 +&cpu3 {
382 + cpu-supply = <&vdd_cpu>;
383 +};
384 +
385 +&gpu {
386 + mali-supply = <&vdd_gpu>;
387 + status = "okay";
388 +};
389 +
390 +&hdmi {
391 + avdd-0v9-supply = <&vdda0v9_image>;
392 + avdd-1v8-supply = <&vcca1v8_image>;
393 + status = "okay";
394 +};
395 +
396 +&hdmi_in {
397 + hdmi_in_vp0: endpoint {
398 + remote-endpoint = <&vp0_out_hdmi>;
399 + };
400 +};
401 +
402 +&hdmi_out {
403 + hdmi_out_con: endpoint {
404 + remote-endpoint = <&hdmi_con_in>;
405 + };
406 +};
407 +
408 +&hdmi_sound {
409 + status = "okay";
410 +};
411 +
412 +&i2c0 {
413 + status = "okay";
414 +
415 + vdd_cpu: regulator@1c {
416 + compatible = "tcs,tcs4525";
417 + reg = <0x1c>;
418 + fcs,suspend-voltage-selector = <1>;
419 + regulator-name = "vdd_cpu";
420 + regulator-always-on;
421 + regulator-boot-on;
422 + regulator-min-microvolt = <800000>;
423 + regulator-max-microvolt = <1150000>;
424 + regulator-ramp-delay = <2300>;
425 + vin-supply = <&vcc5v0_sys>;
426 +
427 + regulator-state-mem {
428 + regulator-off-in-suspend;
429 + };
430 + };
431 +
432 + rk809: pmic@20 {
433 + compatible = "rockchip,rk809";
434 + reg = <0x20>;
435 + interrupt-parent = <&gpio0>;
436 + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
437 + #clock-cells = <1>;
438 + pinctrl-names = "default";
439 + pinctrl-0 = <&pmic_int>;
440 + rockchip,system-power-controller;
441 + vcc1-supply = <&vcc3v3_sys>;
442 + vcc2-supply = <&vcc3v3_sys>;
443 + vcc3-supply = <&vcc3v3_sys>;
444 + vcc4-supply = <&vcc3v3_sys>;
445 + vcc5-supply = <&vcc3v3_sys>;
446 + vcc6-supply = <&vcc3v3_sys>;
447 + vcc7-supply = <&vcc3v3_sys>;
448 + vcc8-supply = <&vcc3v3_sys>;
449 + vcc9-supply = <&vcc3v3_sys>;
450 + wakeup-source;
451 +
452 + regulators {
453 + vdd_logic: DCDC_REG1 {
454 + regulator-name = "vdd_logic";
455 + regulator-always-on;
456 + regulator-boot-on;
457 + regulator-init-microvolt = <900000>;
458 + regulator-initial-mode = <0x2>;
459 + regulator-min-microvolt = <500000>;
460 + regulator-max-microvolt = <1350000>;
461 + regulator-ramp-delay = <6001>;
462 +
463 + regulator-state-mem {
464 + regulator-off-in-suspend;
465 + };
466 + };
467 +
468 + vdd_gpu: DCDC_REG2 {
469 + regulator-name = "vdd_gpu";
470 + regulator-always-on;
471 + regulator-init-microvolt = <900000>;
472 + regulator-initial-mode = <0x2>;
473 + regulator-min-microvolt = <500000>;
474 + regulator-max-microvolt = <1350000>;
475 + regulator-ramp-delay = <6001>;
476 +
477 + regulator-state-mem {
478 + regulator-off-in-suspend;
479 + };
480 + };
481 +
482 + vcc_ddr: DCDC_REG3 {
483 + regulator-name = "vcc_ddr";
484 + regulator-always-on;
485 + regulator-boot-on;
486 + regulator-initial-mode = <0x2>;
487 +
488 + regulator-state-mem {
489 + regulator-on-in-suspend;
490 + };
491 + };
492 +
493 + vdd_npu: DCDC_REG4 {
494 + regulator-name = "vdd_npu";
495 + regulator-init-microvolt = <900000>;
496 + regulator-initial-mode = <0x2>;
497 + regulator-min-microvolt = <500000>;
498 + regulator-max-microvolt = <1350000>;
499 + regulator-ramp-delay = <6001>;
500 +
501 + regulator-state-mem {
502 + regulator-off-in-suspend;
503 + };
504 + };
505 +
506 + vcc_1v8: DCDC_REG5 {
507 + regulator-name = "vcc_1v8";
508 + regulator-always-on;
509 + regulator-boot-on;
510 + regulator-min-microvolt = <1800000>;
511 + regulator-max-microvolt = <1800000>;
512 +
513 + regulator-state-mem {
514 + regulator-off-in-suspend;
515 + };
516 + };
517 +
518 + vdda0v9_image: LDO_REG1 {
519 + regulator-name = "vdda0v9_image";
520 + regulator-min-microvolt = <950000>;
521 + regulator-max-microvolt = <950000>;
522 +
523 + regulator-state-mem {
524 + regulator-off-in-suspend;
525 + };
526 + };
527 +
528 + vdda_0v9: LDO_REG2 {
529 + regulator-name = "vdda_0v9";
530 + regulator-always-on;
531 + regulator-boot-on;
532 + regulator-min-microvolt = <900000>;
533 + regulator-max-microvolt = <900000>;
534 +
535 + regulator-state-mem {
536 + regulator-off-in-suspend;
537 + };
538 + };
539 +
540 + vdda0v9_pmu: LDO_REG3 {
541 + regulator-name = "vdda0v9_pmu";
542 + regulator-always-on;
543 + regulator-boot-on;
544 + regulator-min-microvolt = <900000>;
545 + regulator-max-microvolt = <900000>;
546 +
547 + regulator-state-mem {
548 + regulator-on-in-suspend;
549 + regulator-suspend-microvolt = <900000>;
550 + };
551 + };
552 +
553 + vccio_acodec: LDO_REG4 {
554 + regulator-name = "vccio_acodec";
555 + regulator-min-microvolt = <3300000>;
556 + regulator-max-microvolt = <3300000>;
557 +
558 + regulator-state-mem {
559 + regulator-off-in-suspend;
560 + };
561 + };
562 +
563 + vccio_sd: LDO_REG5 {
564 + regulator-name = "vccio_sd";
565 + regulator-min-microvolt = <1800000>;
566 + regulator-max-microvolt = <3300000>;
567 +
568 + regulator-state-mem {
569 + regulator-off-in-suspend;
570 + };
571 + };
572 +
573 + vcc3v3_pmu: LDO_REG6 {
574 + regulator-name = "vcc3v3_pmu";
575 + regulator-always-on;
576 + regulator-boot-on;
577 + regulator-min-microvolt = <3300000>;
578 + regulator-max-microvolt = <3300000>;
579 +
580 + regulator-state-mem {
581 + regulator-on-in-suspend;
582 + regulator-suspend-microvolt = <3300000>;
583 + };
584 + };
585 +
586 + vcca_1v8: LDO_REG7 {
587 + regulator-name = "vcca_1v8";
588 + regulator-always-on;
589 + regulator-boot-on;
590 + regulator-min-microvolt = <1800000>;
591 + regulator-max-microvolt = <1800000>;
592 +
593 + regulator-state-mem {
594 + regulator-off-in-suspend;
595 + };
596 + };
597 +
598 + vcca1v8_pmu: LDO_REG8 {
599 + regulator-name = "vcca1v8_pmu";
600 + regulator-always-on;
601 + regulator-boot-on;
602 + regulator-min-microvolt = <1800000>;
603 + regulator-max-microvolt = <1800000>;
604 +
605 + regulator-state-mem {
606 + regulator-on-in-suspend;
607 + regulator-suspend-microvolt = <1800000>;
608 + };
609 + };
610 +
611 + vcca1v8_image: LDO_REG9 {
612 + regulator-name = "vcca1v8_image";
613 + regulator-min-microvolt = <1800000>;
614 + regulator-max-microvolt = <1800000>;
615 +
616 + regulator-state-mem {
617 + regulator-off-in-suspend;
618 + };
619 + };
620 +
621 + vcc_3v3: SWITCH_REG1 {
622 + regulator-name = "vcc_3v3";
623 + regulator-always-on;
624 + regulator-boot-on;
625 +
626 + regulator-state-mem {
627 + regulator-off-in-suspend;
628 + };
629 + };
630 +
631 + vcc3v3_sd: SWITCH_REG2 {
632 + regulator-name = "vcc3v3_sd";
633 + regulator-always-on;
634 + regulator-boot-on;
635 +
636 + regulator-state-mem {
637 + regulator-off-in-suspend;
638 + };
639 + };
640 + };
641 +
642 + };
643 +};
644 +
645 +&i2c5 {
646 + status = "okay";
647 +
648 + hym8563: rtc@51 {
649 + compatible = "haoyu,hym8563";
650 + reg = <0x51>;
651 + interrupt-parent = <&gpio0>;
652 + interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
653 + #clock-cells = <0>;
654 + clock-output-names = "rtcic_32kout";
655 + pinctrl-names = "default";
656 + pinctrl-0 = <&hym8563_int>;
657 + wakeup-source;
658 + };
659 +};
660 +
661 +&i2s0_8ch {
662 + status = "okay";
663 +};
664 +
665 +&pcie30phy {
666 + data-lanes = <1 2>;
667 + status = "okay";
668 +};
669 +
670 +&pinctrl {
671 + hym8563 {
672 + hym8563_int: hym8563-int {
673 + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
674 + };
675 + };
676 +
677 + pmic {
678 + pmic_int: pmic-int {
679 + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
680 + };
681 + };
682 +
683 + usb {
684 + vcc5v0_usb_host_en: vcc5v0-usb-host-en {
685 + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
686 + };
687 +
688 + vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
689 + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
690 + };
691 + };
692 +};
693 +
694 +&pmu_io_domains {
695 + pmuio1-supply = <&vcc3v3_pmu>;
696 + pmuio2-supply = <&vcc3v3_pmu>;
697 + vccio1-supply = <&vccio_acodec>;
698 + vccio3-supply = <&vccio_sd>;
699 + vccio4-supply = <&vcc_1v8>;
700 + vccio5-supply = <&vcc_3v3>;
701 + vccio6-supply = <&vcc_1v8>;
702 + vccio7-supply = <&vcc_3v3>;
703 + status = "okay";
704 +};
705 +
706 +&saradc {
707 + vref-supply = <&vcca_1v8>;
708 + status = "okay";
709 +};
710 +
711 +&sdhci {
712 + bus-width = <8>;
713 + max-frequency = <200000000>;
714 + non-removable;
715 + pinctrl-names = "default";
716 + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
717 + status = "okay";
718 +};
719 +
720 +&sdmmc0 {
721 + max-frequency = <150000000>;
722 + no-sdio;
723 + no-mmc;
724 + bus-width = <4>;
725 + cap-mmc-highspeed;
726 + cap-sd-highspeed;
727 + disable-wp;
728 + vmmc-supply = <&vcc3v3_sd>;
729 + vqmmc-supply = <&vccio_sd>;
730 + pinctrl-names = "default";
731 + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
732 + status = "okay";
733 +};
734 +
735 +&tsadc {
736 + rockchip,hw-tshut-mode = <1>;
737 + rockchip,hw-tshut-polarity = <0>;
738 + status = "okay";
739 +};
740 +
741 +&uart2 {
742 + status = "okay";
743 +};
744 +
745 +&usb_host0_ehci {
746 + status = "okay";
747 +};
748 +
749 +&usb_host0_ohci {
750 + status = "okay";
751 +};
752 +
753 +&usb_host0_xhci {
754 + extcon = <&usb2phy0>;
755 + dr_mode = "host";
756 + status = "okay";
757 +};
758 +
759 +&usb_host1_ehci {
760 + status = "okay";
761 +};
762 +
763 +&usb_host1_ohci {
764 + status = "okay";
765 +};
766 +
767 +&usb_host1_xhci {
768 + status = "okay";
769 +};
770 +
771 +&usb2phy0 {
772 + status = "okay";
773 +};
774 +
775 +&usb2phy0_host {
776 + phy-supply = <&vcc5v0_usb_host>;
777 + status = "okay";
778 +};
779 +
780 +&usb2phy0_otg {
781 + status = "okay";
782 +};
783 +
784 +&usb2phy1 {
785 + status = "okay";
786 +};
787 +
788 +&usb2phy1_host {
789 + phy-supply = <&vcc5v0_usb_otg>;
790 + status = "okay";
791 +};
792 +
793 +&usb2phy1_otg {
794 + status = "okay";
795 +};
796 +
797 +&vop {
798 + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
799 + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
800 + status = "okay";
801 +};
802 +
803 +&vop_mmu {
804 + status = "okay";
805 +};
806 +
807 +&vp0 {
808 + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
809 + reg = <ROCKCHIP_VOP2_EP_HDMI0>;
810 + remote-endpoint = <&hdmi_in_vp0>;
811 + };
812 +};
813 --- a/board/rockchip/evb_rk3568/MAINTAINERS
814 +++ b/board/rockchip/evb_rk3568/MAINTAINERS
815 @@ -7,6 +7,14 @@ F: configs/evb-rk3568_defconfig
816 F: arch/arm/dts/rk3568-evb-boot.dtsi
817 F: arch/arm/dts/rk3568-evb.dts
818
819 +NANOPI-R5S
820 +M: Tianling Shen <cnsztl@gmail.com>
821 +S: Maintained
822 +F: configs/nanopi-r5s-rk3568_defconfig
823 +F: arch/arm/dts/rk3568-nanopi-r5s.dts
824 +F: arch/arm/dts/rk3568-nanopi-r5s.dtsi
825 +F: arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
826 +
827 RADXA-CM3
828 M: Jagan Teki <jagan@amarulasolutions.com>
829 S: Maintained
830 --- /dev/null
831 +++ b/configs/nanopi-r5s-rk3568_defconfig
832 @@ -0,0 +1,85 @@
833 +CONFIG_ARM=y
834 +CONFIG_SKIP_LOWLEVEL_INIT=y
835 +CONFIG_COUNTER_FREQUENCY=24000000
836 +CONFIG_ARCH_ROCKCHIP=y
837 +CONFIG_TEXT_BASE=0x00a00000
838 +CONFIG_SPL_LIBCOMMON_SUPPORT=y
839 +CONFIG_SPL_LIBGENERIC_SUPPORT=y
840 +CONFIG_NR_DRAM_BANKS=2
841 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
842 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
843 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s"
844 +CONFIG_ROCKCHIP_RK3568=y
845 +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
846 +CONFIG_SPL_SERIAL=y
847 +CONFIG_SPL_STACK_R_ADDR=0x600000
848 +CONFIG_TARGET_EVB_RK3568=y
849 +CONFIG_SPL_STACK=0x400000
850 +CONFIG_DEBUG_UART_BASE=0xFE660000
851 +CONFIG_DEBUG_UART_CLOCK=24000000
852 +CONFIG_SYS_LOAD_ADDR=0xc00800
853 +CONFIG_DEBUG_UART=y
854 +CONFIG_FIT=y
855 +CONFIG_FIT_VERBOSE=y
856 +CONFIG_SPL_LOAD_FIT=y
857 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb"
858 +# CONFIG_DISPLAY_CPUINFO is not set
859 +CONFIG_DISPLAY_BOARDINFO_LATE=y
860 +CONFIG_SPL_MAX_SIZE=0x40000
861 +CONFIG_SPL_PAD_TO=0x7f8000
862 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
863 +CONFIG_SPL_BSS_START_ADDR=0x4000000
864 +CONFIG_SPL_BSS_MAX_SIZE=0x4000
865 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
866 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
867 +CONFIG_SPL_STACK_R=y
868 +CONFIG_SPL_ATF=y
869 +CONFIG_CMD_GPIO=y
870 +CONFIG_CMD_GPT=y
871 +CONFIG_CMD_I2C=y
872 +CONFIG_CMD_MMC=y
873 +CONFIG_CMD_USB=y
874 +CONFIG_CMD_PMIC=y
875 +CONFIG_CMD_REGULATOR=y
876 +# CONFIG_SPL_DOS_PARTITION is not set
877 +CONFIG_SPL_OF_CONTROL=y
878 +CONFIG_OF_LIVE=y
879 +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
880 +CONFIG_SPL_DM_WARN=y
881 +CONFIG_SPL_REGMAP=y
882 +CONFIG_SPL_SYSCON=y
883 +CONFIG_SPL_CLK=y
884 +CONFIG_ROCKCHIP_GPIO=y
885 +CONFIG_SYS_I2C_ROCKCHIP=y
886 +CONFIG_MISC=y
887 +CONFIG_SUPPORT_EMMC_RPMB=y
888 +CONFIG_MMC_DW=y
889 +CONFIG_MMC_DW_ROCKCHIP=y
890 +CONFIG_MMC_SDHCI=y
891 +CONFIG_MMC_SDHCI_SDMA=y
892 +CONFIG_MMC_SDHCI_ROCKCHIP=y
893 +CONFIG_ETH_DESIGNWARE=y
894 +CONFIG_GMAC_ROCKCHIP=y
895 +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
896 +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
897 +CONFIG_POWER_DOMAIN=y
898 +CONFIG_DM_PMIC=y
899 +CONFIG_PMIC_RK8XX=y
900 +CONFIG_SPL_DM_REGULATOR_FIXED=y
901 +CONFIG_REGULATOR_RK8XX=y
902 +CONFIG_PWM_ROCKCHIP=y
903 +CONFIG_SPL_RAM=y
904 +CONFIG_BAUDRATE=1500000
905 +CONFIG_DEBUG_UART_SHIFT=2
906 +CONFIG_SYS_NS16550_MEM32=y
907 +CONFIG_SYSRESET=y
908 +CONFIG_SYSRESET_PSCI=y
909 +CONFIG_USB=y
910 +CONFIG_USB_XHCI_HCD=y
911 +CONFIG_USB_XHCI_DWC3=y
912 +CONFIG_USB_EHCI_HCD=y
913 +CONFIG_USB_EHCI_GENERIC=y
914 +CONFIG_USB_OHCI_HCD=y
915 +CONFIG_USB_OHCI_GENERIC=y
916 +CONFIG_USB_DWC3=y
917 +CONFIG_ERRNO_STR=y
Hauke Mehrtens staging tree