package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-Orange-Pi-R1-Plus.patch

   1 From 89afb631d965292aaf433806d8224b53d9e74036 Mon Sep 17 00:00:00 2001
   2 From: Tianling Shen <cnsztl@gmail.com>
   3 Date: Sat, 20 May 2023 18:50:38 +0800
   4 Subject: [PATCH] rockchip: rk3328: Add support for Orange Pi R1 Plus
   5
   6 Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong.
   7
   8 This device is similar to the NanoPi R2S, and has a 16MB
   9 SPI NOR (mx25l12805d). The reset button is changed to
  10 directly reset the power supply, another detail is that
  11 both network ports have independent MAC addresses.
  12
  13 The device tree and description are taken from kernel v6.3-rc1.
  14
  15 Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
  16 Signed-off-by: Tianling Shen <cnsztl@gmail.com>
  17 ---
  18  arch/arm/dts/Makefile                         |   1 +
  19  .../dts/rk3328-orangepi-r1-plus-u-boot.dtsi   |  46 +++
  20  arch/arm/dts/rk3328-orangepi-r1-plus.dts      | 373 ++++++++++++++++++
  21  board/rockchip/evb_rk3328/MAINTAINERS         |   6 +
  22  configs/orangepi-r1-plus-rk3328_defconfig     | 114 ++++++
  23  5 files changed, 540 insertions(+)
  24  create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
  25  create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus.dts
  26  create mode 100644 configs/orangepi-r1-plus-rk3328_defconfig
  27
  28 --- a/arch/arm/dts/Makefile
  29 +++ b/arch/arm/dts/Makefile
  30 @@ -125,6 +125,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
  31         rk3328-evb.dtb \
  32         rk3328-nanopi-r2c.dtb \
  33         rk3328-nanopi-r2s.dtb \
  34 +       rk3328-orangepi-r1-plus.dtb \
  35         rk3328-roc-cc.dtb \
  36         rk3328-rock64.dtb \
  37         rk3328-rock-pi-e.dtb
  38 --- /dev/null
  39 +++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
  40 @@ -0,0 +1,46 @@
  41 +// SPDX-License-Identifier: GPL-2.0-or-later
  42 +/*
  43 + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
  44 + * (C) Copyright 2020 David Bauer
  45 + */
  46 +
  47 +#include "rk3328-u-boot.dtsi"
  48 +#include "rk3328-sdram-ddr4-666.dtsi"
  49 +/ {
  50 +       chosen {
  51 +               u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
  52 +       };
  53 +};
  54 +
  55 +&gpio0 {
  56 +       bootph-pre-ram;
  57 +};
  58 +
  59 +&pinctrl {
  60 +       bootph-pre-ram;
  61 +};
  62 +
  63 +&sdmmc0m1_pin {
  64 +       bootph-pre-ram;
  65 +};
  66 +
  67 +&pcfg_pull_up_4ma {
  68 +       bootph-pre-ram;
  69 +};
  70 +
  71 +/* Need this and all the pinctrl/gpio stuff above to set pinmux */
  72 +&vcc_sd {
  73 +       bootph-pre-ram;
  74 +};
  75 +
  76 +&gmac2io {
  77 +       snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
  78 +       snps,reset-active-low;
  79 +       snps,reset-delays-us = <0 10000 50000>;
  80 +};
  81 +
  82 +&spi0 {
  83 +       spi_flash: spiflash@0 {
  84 +               bootph-all;
  85 +       };
  86 +};
  87 --- /dev/null
  88 +++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
  89 @@ -0,0 +1,373 @@
  90 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  91 +/*
  92 + * Based on rk3328-nanopi-r2s.dts, which is:
  93 + *   Copyright (c) 2020 David Bauer <mail@david-bauer.net>
  94 + */
  95 +
  96 +/dts-v1/;
  97 +
  98 +#include <dt-bindings/gpio/gpio.h>
  99 +#include <dt-bindings/leds/common.h>
 100 +#include "rk3328.dtsi"
 101 +
 102 +/ {
 103 +       model = "Xunlong Orange Pi R1 Plus";
 104 +       compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
 105 +
 106 +       aliases {
 107 +               ethernet1 = &rtl8153;
 108 +               mmc0 = &sdmmc;
 109 +       };
 110 +
 111 +       chosen {
 112 +               stdout-path = "serial2:1500000n8";
 113 +       };
 114 +
 115 +       gmac_clk: gmac-clock {
 116 +               compatible = "fixed-clock";
 117 +               clock-frequency = <125000000>;
 118 +               clock-output-names = "gmac_clkin";
 119 +               #clock-cells = <0>;
 120 +       };
 121 +
 122 +       leds {
 123 +               compatible = "gpio-leds";
 124 +               pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
 125 +               pinctrl-names = "default";
 126 +
 127 +               led-0 {
 128 +                       function = LED_FUNCTION_LAN;
 129 +                       color = <LED_COLOR_ID_GREEN>;
 130 +                       gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
 131 +               };
 132 +
 133 +               led-1 {
 134 +                       function = LED_FUNCTION_STATUS;
 135 +                       color = <LED_COLOR_ID_RED>;
 136 +                       gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
 137 +                       linux,default-trigger = "heartbeat";
 138 +               };
 139 +
 140 +               led-2 {
 141 +                       function = LED_FUNCTION_WAN;
 142 +                       color = <LED_COLOR_ID_GREEN>;
 143 +                       gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
 144 +               };
 145 +       };
 146 +
 147 +       vcc_sd: sdmmc-regulator {
 148 +               compatible = "regulator-fixed";
 149 +               gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
 150 +               pinctrl-0 = <&sdmmc0m1_pin>;
 151 +               pinctrl-names = "default";
 152 +               regulator-name = "vcc_sd";
 153 +               regulator-boot-on;
 154 +               vin-supply = <&vcc_io>;
 155 +       };
 156 +
 157 +       vcc_sys: vcc-sys-regulator {
 158 +               compatible = "regulator-fixed";
 159 +               regulator-name = "vcc_sys";
 160 +               regulator-always-on;
 161 +               regulator-boot-on;
 162 +               regulator-min-microvolt = <5000000>;
 163 +               regulator-max-microvolt = <5000000>;
 164 +       };
 165 +
 166 +       vdd_5v_lan: vdd-5v-lan-regulator {
 167 +               compatible = "regulator-fixed";
 168 +               enable-active-high;
 169 +               gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
 170 +               pinctrl-0 = <&lan_vdd_pin>;
 171 +               pinctrl-names = "default";
 172 +               regulator-name = "vdd_5v_lan";
 173 +               regulator-always-on;
 174 +               regulator-boot-on;
 175 +               vin-supply = <&vcc_sys>;
 176 +       };
 177 +};
 178 +
 179 +&cpu0 {
 180 +       cpu-supply = <&vdd_arm>;
 181 +};
 182 +
 183 +&cpu1 {
 184 +       cpu-supply = <&vdd_arm>;
 185 +};
 186 +
 187 +&cpu2 {
 188 +       cpu-supply = <&vdd_arm>;
 189 +};
 190 +
 191 +&cpu3 {
 192 +       cpu-supply = <&vdd_arm>;
 193 +};
 194 +
 195 +&display_subsystem {
 196 +       status = "disabled";
 197 +};
 198 +
 199 +&gmac2io {
 200 +       assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
 201 +       assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
 202 +       clock_in_out = "input";
 203 +       phy-handle = <&rtl8211e>;
 204 +       phy-mode = "rgmii";
 205 +       phy-supply = <&vcc_io>;
 206 +       pinctrl-0 = <&rgmiim1_pins>;
 207 +       pinctrl-names = "default";
 208 +       snps,aal;
 209 +       rx_delay = <0x18>;
 210 +       tx_delay = <0x24>;
 211 +       status = "okay";
 212 +
 213 +       mdio {
 214 +               compatible = "snps,dwmac-mdio";
 215 +               #address-cells = <1>;
 216 +               #size-cells = <0>;
 217 +
 218 +               rtl8211e: ethernet-phy@1 {
 219 +                       reg = <1>;
 220 +                       pinctrl-0 = <&eth_phy_reset_pin>;
 221 +                       pinctrl-names = "default";
 222 +                       reset-assert-us = <10000>;
 223 +                       reset-deassert-us = <50000>;
 224 +                       reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
 225 +               };
 226 +       };
 227 +};
 228 +
 229 +&i2c1 {
 230 +       status = "okay";
 231 +
 232 +       rk805: pmic@18 {
 233 +               compatible = "rockchip,rk805";
 234 +               reg = <0x18>;
 235 +               interrupt-parent = <&gpio1>;
 236 +               interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
 237 +               #clock-cells = <1>;
 238 +               clock-output-names = "xin32k", "rk805-clkout2";
 239 +               gpio-controller;
 240 +               #gpio-cells = <2>;
 241 +               pinctrl-0 = <&pmic_int_l>;
 242 +               pinctrl-names = "default";
 243 +               rockchip,system-power-controller;
 244 +               wakeup-source;
 245 +
 246 +               vcc1-supply = <&vcc_sys>;
 247 +               vcc2-supply = <&vcc_sys>;
 248 +               vcc3-supply = <&vcc_sys>;
 249 +               vcc4-supply = <&vcc_sys>;
 250 +               vcc5-supply = <&vcc_io>;
 251 +               vcc6-supply = <&vcc_sys>;
 252 +
 253 +               regulators {
 254 +                       vdd_log: DCDC_REG1 {
 255 +                               regulator-name = "vdd_log";
 256 +                               regulator-always-on;
 257 +                               regulator-boot-on;
 258 +                               regulator-min-microvolt = <712500>;
 259 +                               regulator-max-microvolt = <1450000>;
 260 +                               regulator-ramp-delay = <12500>;
 261 +
 262 +                               regulator-state-mem {
 263 +                                       regulator-on-in-suspend;
 264 +                                       regulator-suspend-microvolt = <1000000>;
 265 +                               };
 266 +                       };
 267 +
 268 +                       vdd_arm: DCDC_REG2 {
 269 +                               regulator-name = "vdd_arm";
 270 +                               regulator-always-on;
 271 +                               regulator-boot-on;
 272 +                               regulator-min-microvolt = <712500>;
 273 +                               regulator-max-microvolt = <1450000>;
 274 +                               regulator-ramp-delay = <12500>;
 275 +
 276 +                               regulator-state-mem {
 277 +                                       regulator-on-in-suspend;
 278 +                                       regulator-suspend-microvolt = <950000>;
 279 +                               };
 280 +                       };
 281 +
 282 +                       vcc_ddr: DCDC_REG3 {
 283 +                               regulator-name = "vcc_ddr";
 284 +                               regulator-always-on;
 285 +                               regulator-boot-on;
 286 +
 287 +                               regulator-state-mem {
 288 +                                       regulator-on-in-suspend;
 289 +                               };
 290 +                       };
 291 +
 292 +                       vcc_io: DCDC_REG4 {
 293 +                               regulator-name = "vcc_io";
 294 +                               regulator-always-on;
 295 +                               regulator-boot-on;
 296 +                               regulator-min-microvolt = <3300000>;
 297 +                               regulator-max-microvolt = <3300000>;
 298 +
 299 +                               regulator-state-mem {
 300 +                                       regulator-on-in-suspend;
 301 +                                       regulator-suspend-microvolt = <3300000>;
 302 +                               };
 303 +                       };
 304 +
 305 +                       vcc_18: LDO_REG1 {
 306 +                               regulator-name = "vcc_18";
 307 +                               regulator-always-on;
 308 +                               regulator-boot-on;
 309 +                               regulator-min-microvolt = <1800000>;
 310 +                               regulator-max-microvolt = <1800000>;
 311 +
 312 +                               regulator-state-mem {
 313 +                                       regulator-on-in-suspend;
 314 +                                       regulator-suspend-microvolt = <1800000>;
 315 +                               };
 316 +                       };
 317 +
 318 +                       vcc18_emmc: LDO_REG2 {
 319 +                               regulator-name = "vcc18_emmc";
 320 +                               regulator-always-on;
 321 +                               regulator-boot-on;
 322 +                               regulator-min-microvolt = <1800000>;
 323 +                               regulator-max-microvolt = <1800000>;
 324 +
 325 +                               regulator-state-mem {
 326 +                                       regulator-on-in-suspend;
 327 +                                       regulator-suspend-microvolt = <1800000>;
 328 +                               };
 329 +                       };
 330 +
 331 +                       vdd_10: LDO_REG3 {
 332 +                               regulator-name = "vdd_10";
 333 +                               regulator-always-on;
 334 +                               regulator-boot-on;
 335 +                               regulator-min-microvolt = <1000000>;
 336 +                               regulator-max-microvolt = <1000000>;
 337 +
 338 +                               regulator-state-mem {
 339 +                                       regulator-on-in-suspend;
 340 +                                       regulator-suspend-microvolt = <1000000>;
 341 +                               };
 342 +                       };
 343 +               };
 344 +       };
 345 +};
 346 +
 347 +&io_domains {
 348 +       pmuio-supply = <&vcc_io>;
 349 +       vccio1-supply = <&vcc_io>;
 350 +       vccio2-supply = <&vcc18_emmc>;
 351 +       vccio3-supply = <&vcc_io>;
 352 +       vccio4-supply = <&vcc_io>;
 353 +       vccio5-supply = <&vcc_io>;
 354 +       vccio6-supply = <&vcc_io>;
 355 +       status = "okay";
 356 +};
 357 +
 358 +&pinctrl {
 359 +       gmac2io {
 360 +               eth_phy_reset_pin: eth-phy-reset-pin {
 361 +                       rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
 362 +               };
 363 +       };
 364 +
 365 +       leds {
 366 +               lan_led_pin: lan-led-pin {
 367 +                       rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
 368 +               };
 369 +
 370 +               sys_led_pin: sys-led-pin {
 371 +                       rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
 372 +               };
 373 +
 374 +               wan_led_pin: wan-led-pin {
 375 +                       rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
 376 +               };
 377 +       };
 378 +
 379 +       lan {
 380 +               lan_vdd_pin: lan-vdd-pin {
 381 +                       rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
 382 +               };
 383 +       };
 384 +
 385 +       pmic {
 386 +               pmic_int_l: pmic-int-l {
 387 +                       rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
 388 +               };
 389 +       };
 390 +};
 391 +
 392 +&pwm2 {
 393 +       status = "okay";
 394 +};
 395 +
 396 +&sdmmc {
 397 +       bus-width = <4>;
 398 +       cap-sd-highspeed;
 399 +       disable-wp;
 400 +       pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
 401 +       pinctrl-names = "default";
 402 +       vmmc-supply = <&vcc_sd>;
 403 +       status = "okay";
 404 +};
 405 +
 406 +&spi0 {
 407 +       status = "okay";
 408 +
 409 +       flash@0 {
 410 +               compatible = "jedec,spi-nor";
 411 +               reg = <0>;
 412 +               spi-max-frequency = <50000000>;
 413 +       };
 414 +};
 415 +
 416 +&tsadc {
 417 +       rockchip,hw-tshut-mode = <0>;
 418 +       rockchip,hw-tshut-polarity = <0>;
 419 +       status = "okay";
 420 +};
 421 +
 422 +&u2phy {
 423 +       status = "okay";
 424 +};
 425 +
 426 +&u2phy_host {
 427 +       status = "okay";
 428 +};
 429 +
 430 +&u2phy_otg {
 431 +       status = "okay";
 432 +};
 433 +
 434 +&uart2 {
 435 +       status = "okay";
 436 +};
 437 +
 438 +&usb20_otg {
 439 +       dr_mode = "host";
 440 +       status = "okay";
 441 +};
 442 +
 443 +&usbdrd3 {
 444 +       dr_mode = "host";
 445 +       status = "okay";
 446 +       #address-cells = <1>;
 447 +       #size-cells = <0>;
 448 +
 449 +       /* Second port is for USB 3.0 */
 450 +       rtl8153: device@2 {
 451 +               compatible = "usbbda,8153";
 452 +               reg = <2>;
 453 +       };
 454 +};
 455 +
 456 +&usb_host0_ehci {
 457 +       status = "okay";
 458 +};
 459 +
 460 +&usb_host0_ohci {
 461 +       status = "okay";
 462 +};
 463 --- a/board/rockchip/evb_rk3328/MAINTAINERS
 464 +++ b/board/rockchip/evb_rk3328/MAINTAINERS
 465 @@ -18,6 +18,12 @@ F:      configs/nanopi-r2s-rk3328_defcon
 466  F:      arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
 467  F:      arch/arm/dts/rk3328-nanopi-r2s.dts
 468
 469 +ORANGEPI-R1-PLUS-RK3328
 470 +M:      Tianling Shen <cnsztl@gmail.com>
 471 +S:      Maintained
 472 +F:      configs/orangepi-r1-plus-rk3328_defconfig
 473 +F:      arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
 474 +
 475  ROC-RK3328-CC
 476  M:      Loic Devulder <ldevulder@suse.com>
 477  M:      Chen-Yu Tsai <wens@csie.org>
 478 --- /dev/null
 479 +++ b/configs/orangepi-r1-plus-rk3328_defconfig
 480 @@ -0,0 +1,114 @@
 481 +CONFIG_ARM=y
 482 +CONFIG_SKIP_LOWLEVEL_INIT=y
 483 +CONFIG_COUNTER_FREQUENCY=24000000
 484 +CONFIG_ARCH_ROCKCHIP=y
 485 +CONFIG_TEXT_BASE=0x00200000
 486 +CONFIG_SPL_GPIO=y
 487 +CONFIG_NR_DRAM_BANKS=1
 488 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 489 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
 490 +CONFIG_ENV_OFFSET=0x3F8000
 491 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
 492 +CONFIG_DM_RESET=y
 493 +CONFIG_ROCKCHIP_RK3328=y
 494 +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
 495 +CONFIG_TPL_LIBCOMMON_SUPPORT=y
 496 +CONFIG_TPL_LIBGENERIC_SUPPORT=y
 497 +CONFIG_SPL_DRIVERS_MISC=y
 498 +CONFIG_SPL_STACK_R_ADDR=0x600000
 499 +CONFIG_SPL_STACK=0x400000
 500 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
 501 +CONFIG_DEBUG_UART_BASE=0xFF130000
 502 +CONFIG_DEBUG_UART_CLOCK=24000000
 503 +CONFIG_SYS_LOAD_ADDR=0x800800
 504 +CONFIG_DEBUG_UART=y
 505 +# CONFIG_ANDROID_BOOT_IMAGE is not set
 506 +CONFIG_FIT=y
 507 +CONFIG_FIT_VERBOSE=y
 508 +CONFIG_SPL_LOAD_FIT=y
 509 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
 510 +# CONFIG_DISPLAY_CPUINFO is not set
 511 +CONFIG_DISPLAY_BOARDINFO_LATE=y
 512 +CONFIG_MISC_INIT_R=y
 513 +CONFIG_SPL_MAX_SIZE=0x40000
 514 +CONFIG_SPL_PAD_TO=0x7f8000
 515 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 516 +CONFIG_SPL_BSS_START_ADDR=0x2000000
 517 +CONFIG_SPL_BSS_MAX_SIZE=0x2000
 518 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 519 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 520 +CONFIG_SPL_STACK_R=y
 521 +CONFIG_SPL_I2C=y
 522 +CONFIG_SPL_POWER=y
 523 +CONFIG_SPL_ATF=y
 524 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 525 +CONFIG_TPL_SYS_MALLOC_SIMPLE=y
 526 +CONFIG_CMD_BOOTZ=y
 527 +CONFIG_CMD_GPT=y
 528 +CONFIG_CMD_MMC=y
 529 +CONFIG_CMD_USB=y
 530 +# CONFIG_CMD_SETEXPR is not set
 531 +CONFIG_CMD_TIME=y
 532 +CONFIG_SPL_OF_CONTROL=y
 533 +CONFIG_TPL_OF_CONTROL=y
 534 +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 535 +CONFIG_TPL_OF_PLATDATA=y
 536 +CONFIG_ENV_IS_IN_MMC=y
 537 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 538 +CONFIG_SYS_MMC_ENV_DEV=1
 539 +CONFIG_NET_RANDOM_ETHADDR=y
 540 +CONFIG_TPL_DM=y
 541 +CONFIG_REGMAP=y
 542 +CONFIG_SPL_REGMAP=y
 543 +CONFIG_TPL_REGMAP=y
 544 +CONFIG_SYSCON=y
 545 +CONFIG_SPL_SYSCON=y
 546 +CONFIG_TPL_SYSCON=y
 547 +CONFIG_CLK=y
 548 +CONFIG_SPL_CLK=y
 549 +CONFIG_FASTBOOT_BUF_ADDR=0x800800
 550 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 551 +CONFIG_ROCKCHIP_GPIO=y
 552 +CONFIG_SYS_I2C_ROCKCHIP=y
 553 +CONFIG_MMC_DW=y
 554 +CONFIG_MMC_DW_ROCKCHIP=y
 555 +CONFIG_SF_DEFAULT_SPEED=20000000
 556 +CONFIG_SPI_FLASH_GIGADEVICE=y
 557 +CONFIG_ETH_DESIGNWARE=y
 558 +CONFIG_GMAC_ROCKCHIP=y
 559 +CONFIG_PINCTRL=y
 560 +CONFIG_SPL_PINCTRL=y
 561 +CONFIG_DM_PMIC=y
 562 +CONFIG_PMIC_RK8XX=y
 563 +CONFIG_SPL_PMIC_RK8XX=y
 564 +CONFIG_SPL_DM_REGULATOR=y
 565 +CONFIG_REGULATOR_PWM=y
 566 +CONFIG_DM_REGULATOR_FIXED=y
 567 +CONFIG_SPL_DM_REGULATOR_FIXED=y
 568 +CONFIG_REGULATOR_RK8XX=y
 569 +CONFIG_PWM_ROCKCHIP=y
 570 +CONFIG_RAM=y
 571 +CONFIG_SPL_RAM=y
 572 +CONFIG_TPL_RAM=y
 573 +CONFIG_BAUDRATE=1500000
 574 +CONFIG_DEBUG_UART_SHIFT=2
 575 +CONFIG_SYS_NS16550_MEM32=y
 576 +CONFIG_ROCKCHIP_SPI=y
 577 +CONFIG_SYSINFO=y
 578 +CONFIG_SYSRESET=y
 579 +# CONFIG_TPL_SYSRESET is not set
 580 +CONFIG_USB=y
 581 +CONFIG_USB_XHCI_HCD=y
 582 +CONFIG_USB_XHCI_DWC3=y
 583 +CONFIG_USB_EHCI_HCD=y
 584 +CONFIG_USB_EHCI_GENERIC=y
 585 +CONFIG_USB_OHCI_HCD=y
 586 +CONFIG_USB_OHCI_GENERIC=y
 587 +CONFIG_USB_DWC2=y
 588 +CONFIG_USB_DWC3=y
 589 +# CONFIG_USB_DWC3_GADGET is not set
 590 +CONFIG_USB_GADGET=y
 591 +CONFIG_USB_GADGET_DWC2_OTG=y
 592 +CONFIG_SPL_TINY_MEMSET=y
 593 +CONFIG_TPL_TINY_MEMSET=y
 594 +CONFIG_ERRNO_STR=y