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generic: rtl8366rb: add support for initvals from DTS
[openwrt/staging/florian.git] / target / linux / generic / files / drivers / net / phy / rtl8366rb.c
1 /*
2 * Platform driver for the Realtek RTL8366RB ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
7 * Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/of.h>
19 #include <linux/of_platform.h>
20 #include <linux/delay.h>
21 #include <linux/skbuff.h>
22 #include <linux/rtl8366.h>
23
24 #include "rtl8366_smi.h"
25
26 #define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
27 #define RTL8366RB_DRIVER_VER "0.2.4"
28
29 #define RTL8366RB_PHY_NO_MAX 4
30 #define RTL8366RB_PHY_PAGE_MAX 7
31 #define RTL8366RB_PHY_ADDR_MAX 31
32
33 /* Switch Global Configuration register */
34 #define RTL8366RB_SGCR 0x0000
35 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
36 #define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
37 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
38 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
39 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
40 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
41 #define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
42 #define RTL8366RB_SGCR_EN_VLAN BIT(13)
43 #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
44
45 /* Port Enable Control register */
46 #define RTL8366RB_PECR 0x0001
47
48 /* Port Mirror Control Register */
49 #define RTL8366RB_PMCR 0x0007
50 #define RTL8366RB_PMCR_SOURCE_PORT(_x) (_x)
51 #define RTL8366RB_PMCR_SOURCE_PORT_MASK 0x000f
52 #define RTL8366RB_PMCR_MONITOR_PORT(_x) ((_x) << 4)
53 #define RTL8366RB_PMCR_MONITOR_PORT_MASK 0x00f0
54 #define RTL8366RB_PMCR_MIRROR_RX BIT(8)
55 #define RTL8366RB_PMCR_MIRROR_TX BIT(9)
56 #define RTL8366RB_PMCR_MIRROR_SPC BIT(10)
57 #define RTL8366RB_PMCR_MIRROR_ISO BIT(11)
58
59 /* Switch Security Control registers */
60 #define RTL8366RB_SSCR0 0x0002
61 #define RTL8366RB_SSCR1 0x0003
62 #define RTL8366RB_SSCR2 0x0004
63 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
64
65 #define RTL8366RB_RESET_CTRL_REG 0x0100
66 #define RTL8366RB_CHIP_CTRL_RESET_HW 1
67 #define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
68
69 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
70 #define RTL8366RB_CHIP_VERSION_MASK 0xf
71 #define RTL8366RB_CHIP_ID_REG 0x0509
72 #define RTL8366RB_CHIP_ID_8366 0x5937
73
74 /* PHY registers control */
75 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
76 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
77
78 #define RTL8366RB_PHY_CTRL_READ 1
79 #define RTL8366RB_PHY_CTRL_WRITE 0
80
81 #define RTL8366RB_PHY_REG_MASK 0x1f
82 #define RTL8366RB_PHY_PAGE_OFFSET 5
83 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
84 #define RTL8366RB_PHY_NO_OFFSET 9
85 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
86
87 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
88
89 /* LED control registers */
90 #define RTL8366RB_LED_BLINKRATE_REG 0x0430
91 #define RTL8366RB_LED_BLINKRATE_BIT 0
92 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007
93
94 #define RTL8366RB_LED_CTRL_REG 0x0431
95 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432
96 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433
97
98 #define RTL8366RB_MIB_COUNT 33
99 #define RTL8366RB_GLOBAL_MIB_COUNT 1
100 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
101 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
102 #define RTL8366RB_MIB_CTRL_REG 0x13F0
103 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
104 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
105 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
106 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
107 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
108
109 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
110 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
111 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
112 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
113 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
114
115
116 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
117 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
118
119
120 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
121 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
122 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
123
124 #define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)
125
126
127 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
128 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
129 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
130 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
131 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
132 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
133 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
134
135
136 #define RTL8366RB_PORT_NUM_CPU 5
137 #define RTL8366RB_NUM_PORTS 6
138 #define RTL8366RB_NUM_VLANS 16
139 #define RTL8366RB_NUM_LEDGROUPS 4
140 #define RTL8366RB_NUM_VIDS 4096
141 #define RTL8366RB_PRIORITYMAX 7
142 #define RTL8366RB_FIDMAX 7
143
144
145 #define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
146 #define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
147 #define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
148 #define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
149 #define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
150
151 #define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
152
153 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
154 RTL8366RB_PORT_2 | \
155 RTL8366RB_PORT_3 | \
156 RTL8366RB_PORT_4 | \
157 RTL8366RB_PORT_5 | \
158 RTL8366RB_PORT_CPU)
159
160 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
161 RTL8366RB_PORT_2 | \
162 RTL8366RB_PORT_3 | \
163 RTL8366RB_PORT_4 | \
164 RTL8366RB_PORT_5)
165
166 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
167 RTL8366RB_PORT_2 | \
168 RTL8366RB_PORT_3 | \
169 RTL8366RB_PORT_4)
170
171 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
172
173 #define RTL8366RB_VLAN_VID_MASK 0xfff
174 #define RTL8366RB_VLAN_PRIORITY_SHIFT 12
175 #define RTL8366RB_VLAN_PRIORITY_MASK 0x7
176 #define RTL8366RB_VLAN_UNTAG_SHIFT 8
177 #define RTL8366RB_VLAN_UNTAG_MASK 0xff
178 #define RTL8366RB_VLAN_MEMBER_MASK 0xff
179 #define RTL8366RB_VLAN_FID_MASK 0x7
180
181
182 /* Port ingress bandwidth control */
183 #define RTL8366RB_IB_BASE 0x0200
184 #define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + pnum)
185 #define RTL8366RB_IB_BDTH_MASK 0x3fff
186 #define RTL8366RB_IB_PREIFG_OFFSET 14
187 #define RTL8366RB_IB_PREIFG_MASK (1 << RTL8366RB_IB_PREIFG_OFFSET)
188
189 /* Port egress bandwidth control */
190 #define RTL8366RB_EB_BASE 0x02d1
191 #define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + pnum)
192 #define RTL8366RB_EB_BDTH_MASK 0x3fff
193 #define RTL8366RB_EB_PREIFG_REG 0x02f8
194 #define RTL8366RB_EB_PREIFG_OFFSET 9
195 #define RTL8366RB_EB_PREIFG_MASK (1 << RTL8366RB_EB_PREIFG_OFFSET)
196
197 #define RTL8366RB_BDTH_SW_MAX 1048512
198 #define RTL8366RB_BDTH_UNIT 64
199 #define RTL8366RB_BDTH_REG_DEFAULT 16383
200
201 /* QOS */
202 #define RTL8366RB_QOS_BIT 15
203 #define RTL8366RB_QOS_MASK (1 << RTL8366RB_QOS_BIT)
204 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
205 #define RTL8366RB_QOS_DEFAULT_PREIFG 1
206
207
208 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
209 { 0, 0, 4, "IfInOctets" },
210 { 0, 4, 4, "EtherStatsOctets" },
211 { 0, 8, 2, "EtherStatsUnderSizePkts" },
212 { 0, 10, 2, "EtherFragments" },
213 { 0, 12, 2, "EtherStatsPkts64Octets" },
214 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
215 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
216 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
217 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
218 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
219 { 0, 24, 2, "EtherOversizeStats" },
220 { 0, 26, 2, "EtherStatsJabbers" },
221 { 0, 28, 2, "IfInUcastPkts" },
222 { 0, 30, 2, "EtherStatsMulticastPkts" },
223 { 0, 32, 2, "EtherStatsBroadcastPkts" },
224 { 0, 34, 2, "EtherStatsDropEvents" },
225 { 0, 36, 2, "Dot3StatsFCSErrors" },
226 { 0, 38, 2, "Dot3StatsSymbolErrors" },
227 { 0, 40, 2, "Dot3InPauseFrames" },
228 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
229 { 0, 44, 4, "IfOutOctets" },
230 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
231 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
232 { 0, 52, 2, "Dot3sDeferredTransmissions" },
233 { 0, 54, 2, "Dot3StatsLateCollisions" },
234 { 0, 56, 2, "EtherStatsCollisions" },
235 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
236 { 0, 60, 2, "Dot3OutPauseFrames" },
237 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
238 { 0, 64, 2, "Dot1dTpPortInDiscards" },
239 { 0, 66, 2, "IfOutUcastPkts" },
240 { 0, 68, 2, "IfOutMulticastPkts" },
241 { 0, 70, 2, "IfOutBroadcastPkts" },
242 };
243
244 #define REG_WR(_smi, _reg, _val) \
245 do { \
246 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
247 if (err) \
248 return err; \
249 } while (0)
250
251 #define REG_RMW(_smi, _reg, _mask, _val) \
252 do { \
253 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
254 if (err) \
255 return err; \
256 } while (0)
257
258 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
259 {
260 int timeout = 10;
261 u32 data;
262
263 rtl8366_smi_write_reg_noack(smi, RTL8366RB_RESET_CTRL_REG,
264 RTL8366RB_CHIP_CTRL_RESET_HW);
265 do {
266 msleep(1);
267 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
268 return -EIO;
269
270 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
271 break;
272 } while (--timeout);
273
274 if (!timeout) {
275 printk("Timeout waiting for the switch to reset\n");
276 return -EIO;
277 }
278
279 return 0;
280 }
281
282 static int rtl8366rb_setup(struct rtl8366_smi *smi)
283 {
284 int err;
285 #ifdef CONFIG_OF
286 unsigned i;
287 struct device_node *np;
288 unsigned num_initvals;
289 const __be32 *paddr;
290
291 np = smi->parent->of_node;
292
293 paddr = of_get_property(np, "realtek,initvals", &num_initvals);
294 if (paddr) {
295 dev_info(smi->parent, "applying initvals from DTS\n");
296
297 if (num_initvals < (2 * sizeof(*paddr)))
298 return -EINVAL;
299
300 num_initvals /= sizeof(*paddr);
301
302 for (i = 0; i < num_initvals - 1; i += 2) {
303 u32 reg = be32_to_cpup(paddr + i);
304 u32 val = be32_to_cpup(paddr + i + 1);
305
306 REG_WR(smi, reg, val);
307 }
308 }
309 #endif
310
311 /* set maximum packet length to 1536 bytes */
312 REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
313 RTL8366RB_SGCR_MAX_LENGTH_1536);
314
315 /* enable learning for all ports */
316 REG_WR(smi, RTL8366RB_SSCR0, 0);
317
318 /* enable auto ageing for all ports */
319 REG_WR(smi, RTL8366RB_SSCR1, 0);
320
321 /*
322 * discard VLAN tagged packets if the port is not a member of
323 * the VLAN with which the packets is associated.
324 */
325 REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
326
327 /* don't drop packets whose DA has not been learned */
328 REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
329
330 return 0;
331 }
332
333 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
334 u32 phy_no, u32 page, u32 addr, u32 *data)
335 {
336 u32 reg;
337 int ret;
338
339 if (phy_no > RTL8366RB_PHY_NO_MAX)
340 return -EINVAL;
341
342 if (page > RTL8366RB_PHY_PAGE_MAX)
343 return -EINVAL;
344
345 if (addr > RTL8366RB_PHY_ADDR_MAX)
346 return -EINVAL;
347
348 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
349 RTL8366RB_PHY_CTRL_READ);
350 if (ret)
351 return ret;
352
353 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
354 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
355 (addr & RTL8366RB_PHY_REG_MASK);
356
357 ret = rtl8366_smi_write_reg(smi, reg, 0);
358 if (ret)
359 return ret;
360
361 ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
362 if (ret)
363 return ret;
364
365 return 0;
366 }
367
368 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
369 u32 phy_no, u32 page, u32 addr, u32 data)
370 {
371 u32 reg;
372 int ret;
373
374 if (phy_no > RTL8366RB_PHY_NO_MAX)
375 return -EINVAL;
376
377 if (page > RTL8366RB_PHY_PAGE_MAX)
378 return -EINVAL;
379
380 if (addr > RTL8366RB_PHY_ADDR_MAX)
381 return -EINVAL;
382
383 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
384 RTL8366RB_PHY_CTRL_WRITE);
385 if (ret)
386 return ret;
387
388 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
389 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
390 (addr & RTL8366RB_PHY_REG_MASK);
391
392 ret = rtl8366_smi_write_reg(smi, reg, data);
393 if (ret)
394 return ret;
395
396 return 0;
397 }
398
399 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
400 int port, unsigned long long *val)
401 {
402 int i;
403 int err;
404 u32 addr, data;
405 u64 mibvalue;
406
407 if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
408 return -EINVAL;
409
410 addr = RTL8366RB_MIB_COUNTER_BASE +
411 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
412 rtl8366rb_mib_counters[counter].offset;
413
414 /*
415 * Writing access counter address first
416 * then ASIC will prepare 64bits counter wait for being retrived
417 */
418 data = 0; /* writing data will be discard by ASIC */
419 err = rtl8366_smi_write_reg(smi, addr, data);
420 if (err)
421 return err;
422
423 /* read MIB control register */
424 err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
425 if (err)
426 return err;
427
428 if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
429 return -EBUSY;
430
431 if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
432 return -EIO;
433
434 mibvalue = 0;
435 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
436 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
437 if (err)
438 return err;
439
440 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
441 }
442
443 *val = mibvalue;
444 return 0;
445 }
446
447 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
448 struct rtl8366_vlan_4k *vlan4k)
449 {
450 u32 data[3];
451 int err;
452 int i;
453
454 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
455
456 if (vid >= RTL8366RB_NUM_VIDS)
457 return -EINVAL;
458
459 /* write VID */
460 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE,
461 vid & RTL8366RB_VLAN_VID_MASK);
462 if (err)
463 return err;
464
465 /* write table access control word */
466 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
467 RTL8366RB_TABLE_VLAN_READ_CTRL);
468 if (err)
469 return err;
470
471 for (i = 0; i < 3; i++) {
472 err = rtl8366_smi_read_reg(smi,
473 RTL8366RB_VLAN_TABLE_READ_BASE + i,
474 &data[i]);
475 if (err)
476 return err;
477 }
478
479 vlan4k->vid = vid;
480 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
481 RTL8366RB_VLAN_UNTAG_MASK;
482 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
483 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
484
485 return 0;
486 }
487
488 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
489 const struct rtl8366_vlan_4k *vlan4k)
490 {
491 u32 data[3];
492 int err;
493 int i;
494
495 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
496 vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
497 vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
498 vlan4k->fid > RTL8366RB_FIDMAX)
499 return -EINVAL;
500
501 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
502 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
503 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
504 RTL8366RB_VLAN_UNTAG_SHIFT);
505 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
506
507 for (i = 0; i < 3; i++) {
508 err = rtl8366_smi_write_reg(smi,
509 RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
510 data[i]);
511 if (err)
512 return err;
513 }
514
515 /* write table access control word */
516 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
517 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
518
519 return err;
520 }
521
522 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
523 struct rtl8366_vlan_mc *vlanmc)
524 {
525 u32 data[3];
526 int err;
527 int i;
528
529 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
530
531 if (index >= RTL8366RB_NUM_VLANS)
532 return -EINVAL;
533
534 for (i = 0; i < 3; i++) {
535 err = rtl8366_smi_read_reg(smi,
536 RTL8366RB_VLAN_MC_BASE(index) + i,
537 &data[i]);
538 if (err)
539 return err;
540 }
541
542 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
543 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
544 RTL8366RB_VLAN_PRIORITY_MASK;
545 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
546 RTL8366RB_VLAN_UNTAG_MASK;
547 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
548 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
549
550 return 0;
551 }
552
553 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
554 const struct rtl8366_vlan_mc *vlanmc)
555 {
556 u32 data[3];
557 int err;
558 int i;
559
560 if (index >= RTL8366RB_NUM_VLANS ||
561 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
562 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
563 vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
564 vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
565 vlanmc->fid > RTL8366RB_FIDMAX)
566 return -EINVAL;
567
568 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
569 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
570 RTL8366RB_VLAN_PRIORITY_SHIFT);
571 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
572 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
573 RTL8366RB_VLAN_UNTAG_SHIFT);
574 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
575
576 for (i = 0; i < 3; i++) {
577 err = rtl8366_smi_write_reg(smi,
578 RTL8366RB_VLAN_MC_BASE(index) + i,
579 data[i]);
580 if (err)
581 return err;
582 }
583
584 return 0;
585 }
586
587 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
588 {
589 u32 data;
590 int err;
591
592 if (port >= RTL8366RB_NUM_PORTS)
593 return -EINVAL;
594
595 err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
596 &data);
597 if (err)
598 return err;
599
600 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
601 RTL8366RB_PORT_VLAN_CTRL_MASK;
602
603 return 0;
604
605 }
606
607 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
608 {
609 if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
610 return -EINVAL;
611
612 return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
613 RTL8366RB_PORT_VLAN_CTRL_MASK <<
614 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
615 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
616 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
617 }
618
619 static int rtl8366rb_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
620 {
621 unsigned max = RTL8366RB_NUM_VLANS;
622
623 if (smi->vlan4k_enabled)
624 max = RTL8366RB_NUM_VIDS - 1;
625
626 if (vlan == 0 || vlan >= max)
627 return 0;
628
629 return 1;
630 }
631
632 static int rtl8366rb_enable_vlan(struct rtl8366_smi *smi, int enable)
633 {
634 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
635 (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
636 }
637
638 static int rtl8366rb_enable_vlan4k(struct rtl8366_smi *smi, int enable)
639 {
640 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
641 RTL8366RB_SGCR_EN_VLAN_4KTB,
642 (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
643 }
644
645 static int rtl8366rb_enable_port(struct rtl8366_smi *smi, int port, int enable)
646 {
647 return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, (1 << port),
648 (enable) ? 0 : (1 << port));
649 }
650
651 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
652 const struct switch_attr *attr,
653 struct switch_val *val)
654 {
655 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
656
657 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
658 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
659 }
660
661 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
662 const struct switch_attr *attr,
663 struct switch_val *val)
664 {
665 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
666 u32 data;
667
668 rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
669
670 val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
671
672 return 0;
673 }
674
675 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
676 const struct switch_attr *attr,
677 struct switch_val *val)
678 {
679 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
680
681 if (val->value.i >= 6)
682 return -EINVAL;
683
684 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
685 RTL8366RB_LED_BLINKRATE_MASK,
686 val->value.i);
687 }
688
689 static int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev,
690 const struct switch_attr *attr,
691 struct switch_val *val)
692 {
693 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
694 u32 data;
695
696 rtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data);
697 val->value.i = !data;
698
699 return 0;
700 }
701
702
703 static int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev,
704 const struct switch_attr *attr,
705 struct switch_val *val)
706 {
707 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
708 u32 portmask = 0;
709 int err = 0;
710
711 if (!val->value.i)
712 portmask = RTL8366RB_PORT_ALL;
713
714 /* set learning for all ports */
715 REG_WR(smi, RTL8366RB_SSCR0, portmask);
716
717 /* set auto ageing for all ports */
718 REG_WR(smi, RTL8366RB_SSCR1, portmask);
719
720 return 0;
721 }
722
723 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
724 int port,
725 struct switch_port_link *link)
726 {
727 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
728 u32 data = 0;
729 u32 speed;
730
731 if (port >= RTL8366RB_NUM_PORTS)
732 return -EINVAL;
733
734 rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE + (port / 2),
735 &data);
736
737 if (port % 2)
738 data = data >> 8;
739
740 link->link = !!(data & RTL8366RB_PORT_STATUS_LINK_MASK);
741 if (!link->link)
742 return 0;
743
744 link->duplex = !!(data & RTL8366RB_PORT_STATUS_DUPLEX_MASK);
745 link->rx_flow = !!(data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK);
746 link->tx_flow = !!(data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK);
747 link->aneg = !!(data & RTL8366RB_PORT_STATUS_AN_MASK);
748
749 speed = (data & RTL8366RB_PORT_STATUS_SPEED_MASK);
750 switch (speed) {
751 case 0:
752 link->speed = SWITCH_PORT_SPEED_10;
753 break;
754 case 1:
755 link->speed = SWITCH_PORT_SPEED_100;
756 break;
757 case 2:
758 link->speed = SWITCH_PORT_SPEED_1000;
759 break;
760 default:
761 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
762 break;
763 }
764
765 return 0;
766 }
767
768 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
769 const struct switch_attr *attr,
770 struct switch_val *val)
771 {
772 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
773 u32 data;
774 u32 mask;
775 u32 reg;
776
777 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
778 return -EINVAL;
779
780 if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
781 reg = RTL8366RB_LED_BLINKRATE_REG;
782 mask = 0xF << 4;
783 data = val->value.i << 4;
784 } else {
785 reg = RTL8366RB_LED_CTRL_REG;
786 mask = 0xF << (val->port_vlan * 4),
787 data = val->value.i << (val->port_vlan * 4);
788 }
789
790 return rtl8366_smi_rmwr(smi, reg, mask, data);
791 }
792
793 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
794 const struct switch_attr *attr,
795 struct switch_val *val)
796 {
797 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
798 u32 data = 0;
799
800 if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
801 return -EINVAL;
802
803 rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
804 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
805
806 return 0;
807 }
808
809 static int rtl8366rb_sw_set_port_disable(struct switch_dev *dev,
810 const struct switch_attr *attr,
811 struct switch_val *val)
812 {
813 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
814 u32 mask, data;
815
816 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
817 return -EINVAL;
818
819 mask = 1 << val->port_vlan ;
820 if (val->value.i)
821 data = mask;
822 else
823 data = 0;
824
825 return rtl8366_smi_rmwr(smi, RTL8366RB_PECR, mask, data);
826 }
827
828 static int rtl8366rb_sw_get_port_disable(struct switch_dev *dev,
829 const struct switch_attr *attr,
830 struct switch_val *val)
831 {
832 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
833 u32 data;
834
835 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
836 return -EINVAL;
837
838 rtl8366_smi_read_reg(smi, RTL8366RB_PECR, &data);
839 if (data & (1 << val->port_vlan))
840 val->value.i = 1;
841 else
842 val->value.i = 0;
843
844 return 0;
845 }
846
847 static int rtl8366rb_sw_set_port_rate_in(struct switch_dev *dev,
848 const struct switch_attr *attr,
849 struct switch_val *val)
850 {
851 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
852
853 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
854 return -EINVAL;
855
856 if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
857 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
858 else
859 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
860
861 return rtl8366_smi_rmwr(smi, RTL8366RB_IB_REG(val->port_vlan),
862 RTL8366RB_IB_BDTH_MASK | RTL8366RB_IB_PREIFG_MASK,
863 val->value.i |
864 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_IB_PREIFG_OFFSET));
865
866 }
867
868 static int rtl8366rb_sw_get_port_rate_in(struct switch_dev *dev,
869 const struct switch_attr *attr,
870 struct switch_val *val)
871 {
872 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
873 u32 data;
874
875 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
876 return -EINVAL;
877
878 rtl8366_smi_read_reg(smi, RTL8366RB_IB_REG(val->port_vlan), &data);
879 data &= RTL8366RB_IB_BDTH_MASK;
880 if (data < RTL8366RB_IB_BDTH_MASK)
881 data += 1;
882
883 val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
884
885 return 0;
886 }
887
888 static int rtl8366rb_sw_set_port_rate_out(struct switch_dev *dev,
889 const struct switch_attr *attr,
890 struct switch_val *val)
891 {
892 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
893
894 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
895 return -EINVAL;
896
897 rtl8366_smi_rmwr(smi, RTL8366RB_EB_PREIFG_REG,
898 RTL8366RB_EB_PREIFG_MASK,
899 (RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_EB_PREIFG_OFFSET));
900
901 if (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)
902 val->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;
903 else
904 val->value.i = RTL8366RB_BDTH_REG_DEFAULT;
905
906 return rtl8366_smi_rmwr(smi, RTL8366RB_EB_REG(val->port_vlan),
907 RTL8366RB_EB_BDTH_MASK, val->value.i );
908
909 }
910
911 static int rtl8366rb_sw_get_port_rate_out(struct switch_dev *dev,
912 const struct switch_attr *attr,
913 struct switch_val *val)
914 {
915 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
916 u32 data;
917
918 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
919 return -EINVAL;
920
921 rtl8366_smi_read_reg(smi, RTL8366RB_EB_REG(val->port_vlan), &data);
922 data &= RTL8366RB_EB_BDTH_MASK;
923 if (data < RTL8366RB_EB_BDTH_MASK)
924 data += 1;
925
926 val->value.i = (int)data * RTL8366RB_BDTH_UNIT;
927
928 return 0;
929 }
930
931 static int rtl8366rb_sw_set_qos_enable(struct switch_dev *dev,
932 const struct switch_attr *attr,
933 struct switch_val *val)
934 {
935 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
936 u32 data;
937
938 if (val->value.i)
939 data = RTL8366RB_QOS_MASK;
940 else
941 data = 0;
942
943 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_QOS_MASK, data);
944 }
945
946 static int rtl8366rb_sw_get_qos_enable(struct switch_dev *dev,
947 const struct switch_attr *attr,
948 struct switch_val *val)
949 {
950 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
951 u32 data;
952
953 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
954 if (data & RTL8366RB_QOS_MASK)
955 val->value.i = 1;
956 else
957 val->value.i = 0;
958
959 return 0;
960 }
961
962 static int rtl8366rb_sw_set_mirror_rx_enable(struct switch_dev *dev,
963 const struct switch_attr *attr,
964 struct switch_val *val)
965 {
966 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
967 u32 data;
968
969 if (val->value.i)
970 data = RTL8366RB_PMCR_MIRROR_RX;
971 else
972 data = 0;
973
974 return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_RX, data);
975 }
976
977 static int rtl8366rb_sw_get_mirror_rx_enable(struct switch_dev *dev,
978 const struct switch_attr *attr,
979 struct switch_val *val)
980 {
981 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
982 u32 data;
983
984 rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
985 if (data & RTL8366RB_PMCR_MIRROR_RX)
986 val->value.i = 1;
987 else
988 val->value.i = 0;
989
990 return 0;
991 }
992
993 static int rtl8366rb_sw_set_mirror_tx_enable(struct switch_dev *dev,
994 const struct switch_attr *attr,
995 struct switch_val *val)
996 {
997 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
998 u32 data;
999
1000 if (val->value.i)
1001 data = RTL8366RB_PMCR_MIRROR_TX;
1002 else
1003 data = 0;
1004
1005 return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_TX, data);
1006 }
1007
1008 static int rtl8366rb_sw_get_mirror_tx_enable(struct switch_dev *dev,
1009 const struct switch_attr *attr,
1010 struct switch_val *val)
1011 {
1012 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1013 u32 data;
1014
1015 rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
1016 if (data & RTL8366RB_PMCR_MIRROR_TX)
1017 val->value.i = 1;
1018 else
1019 val->value.i = 0;
1020
1021 return 0;
1022 }
1023
1024 static int rtl8366rb_sw_set_monitor_isolation_enable(struct switch_dev *dev,
1025 const struct switch_attr *attr,
1026 struct switch_val *val)
1027 {
1028 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1029 u32 data;
1030
1031 if (val->value.i)
1032 data = RTL8366RB_PMCR_MIRROR_ISO;
1033 else
1034 data = 0;
1035
1036 return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_ISO, data);
1037 }
1038
1039 static int rtl8366rb_sw_get_monitor_isolation_enable(struct switch_dev *dev,
1040 const struct switch_attr *attr,
1041 struct switch_val *val)
1042 {
1043 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1044 u32 data;
1045
1046 rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
1047 if (data & RTL8366RB_PMCR_MIRROR_ISO)
1048 val->value.i = 1;
1049 else
1050 val->value.i = 0;
1051
1052 return 0;
1053 }
1054
1055 static int rtl8366rb_sw_set_mirror_pause_frames_enable(struct switch_dev *dev,
1056 const struct switch_attr *attr,
1057 struct switch_val *val)
1058 {
1059 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1060 u32 data;
1061
1062 if (val->value.i)
1063 data = RTL8366RB_PMCR_MIRROR_SPC;
1064 else
1065 data = 0;
1066
1067 return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_SPC, data);
1068 }
1069
1070 static int rtl8366rb_sw_get_mirror_pause_frames_enable(struct switch_dev *dev,
1071 const struct switch_attr *attr,
1072 struct switch_val *val)
1073 {
1074 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1075 u32 data;
1076
1077 rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
1078 if (data & RTL8366RB_PMCR_MIRROR_SPC)
1079 val->value.i = 1;
1080 else
1081 val->value.i = 0;
1082
1083 return 0;
1084 }
1085
1086 static int rtl8366rb_sw_set_mirror_monitor_port(struct switch_dev *dev,
1087 const struct switch_attr *attr,
1088 struct switch_val *val)
1089 {
1090 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1091 u32 data;
1092
1093 data = RTL8366RB_PMCR_MONITOR_PORT(val->value.i);
1094
1095 return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MONITOR_PORT_MASK, data);
1096 }
1097
1098 static int rtl8366rb_sw_get_mirror_monitor_port(struct switch_dev *dev,
1099 const struct switch_attr *attr,
1100 struct switch_val *val)
1101 {
1102 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1103 u32 data;
1104
1105 rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
1106 val->value.i = (data & RTL8366RB_PMCR_MONITOR_PORT_MASK) >> 4;
1107
1108 return 0;
1109 }
1110
1111 static int rtl8366rb_sw_set_mirror_source_port(struct switch_dev *dev,
1112 const struct switch_attr *attr,
1113 struct switch_val *val)
1114 {
1115 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1116 u32 data;
1117
1118 data = RTL8366RB_PMCR_SOURCE_PORT(val->value.i);
1119
1120 return rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_SOURCE_PORT_MASK, data);
1121 }
1122
1123 static int rtl8366rb_sw_get_mirror_source_port(struct switch_dev *dev,
1124 const struct switch_attr *attr,
1125 struct switch_val *val)
1126 {
1127 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1128 u32 data;
1129
1130 rtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);
1131 val->value.i = data & RTL8366RB_PMCR_SOURCE_PORT_MASK;
1132
1133 return 0;
1134 }
1135
1136 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
1137 const struct switch_attr *attr,
1138 struct switch_val *val)
1139 {
1140 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1141
1142 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
1143 return -EINVAL;
1144
1145 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
1146 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
1147 }
1148
1149 static struct switch_attr rtl8366rb_globals[] = {
1150 {
1151 .type = SWITCH_TYPE_INT,
1152 .name = "enable_learning",
1153 .description = "Enable learning, enable aging",
1154 .set = rtl8366rb_sw_set_learning_enable,
1155 .get = rtl8366rb_sw_get_learning_enable,
1156 .max = 1
1157 }, {
1158 .type = SWITCH_TYPE_INT,
1159 .name = "enable_vlan",
1160 .description = "Enable VLAN mode",
1161 .set = rtl8366_sw_set_vlan_enable,
1162 .get = rtl8366_sw_get_vlan_enable,
1163 .max = 1,
1164 .ofs = 1
1165 }, {
1166 .type = SWITCH_TYPE_INT,
1167 .name = "enable_vlan4k",
1168 .description = "Enable VLAN 4K mode",
1169 .set = rtl8366_sw_set_vlan_enable,
1170 .get = rtl8366_sw_get_vlan_enable,
1171 .max = 1,
1172 .ofs = 2
1173 }, {
1174 .type = SWITCH_TYPE_NOVAL,
1175 .name = "reset_mibs",
1176 .description = "Reset all MIB counters",
1177 .set = rtl8366rb_sw_reset_mibs,
1178 }, {
1179 .type = SWITCH_TYPE_INT,
1180 .name = "blinkrate",
1181 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1182 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1183 .set = rtl8366rb_sw_set_blinkrate,
1184 .get = rtl8366rb_sw_get_blinkrate,
1185 .max = 5
1186 }, {
1187 .type = SWITCH_TYPE_INT,
1188 .name = "enable_qos",
1189 .description = "Enable QOS",
1190 .set = rtl8366rb_sw_set_qos_enable,
1191 .get = rtl8366rb_sw_get_qos_enable,
1192 .max = 1
1193 }, {
1194 .type = SWITCH_TYPE_INT,
1195 .name = "enable_mirror_rx",
1196 .description = "Enable mirroring of RX packets",
1197 .set = rtl8366rb_sw_set_mirror_rx_enable,
1198 .get = rtl8366rb_sw_get_mirror_rx_enable,
1199 .max = 1
1200 }, {
1201 .type = SWITCH_TYPE_INT,
1202 .name = "enable_mirror_tx",
1203 .description = "Enable mirroring of TX packets",
1204 .set = rtl8366rb_sw_set_mirror_tx_enable,
1205 .get = rtl8366rb_sw_get_mirror_tx_enable,
1206 .max = 1
1207 }, {
1208 .type = SWITCH_TYPE_INT,
1209 .name = "enable_monitor_isolation",
1210 .description = "Enable isolation of monitor port (TX packets will be dropped)",
1211 .set = rtl8366rb_sw_set_monitor_isolation_enable,
1212 .get = rtl8366rb_sw_get_monitor_isolation_enable,
1213 .max = 1
1214 }, {
1215 .type = SWITCH_TYPE_INT,
1216 .name = "enable_mirror_pause_frames",
1217 .description = "Enable mirroring of RX pause frames",
1218 .set = rtl8366rb_sw_set_mirror_pause_frames_enable,
1219 .get = rtl8366rb_sw_get_mirror_pause_frames_enable,
1220 .max = 1
1221 }, {
1222 .type = SWITCH_TYPE_INT,
1223 .name = "mirror_monitor_port",
1224 .description = "Mirror monitor port",
1225 .set = rtl8366rb_sw_set_mirror_monitor_port,
1226 .get = rtl8366rb_sw_get_mirror_monitor_port,
1227 .max = 5
1228 }, {
1229 .type = SWITCH_TYPE_INT,
1230 .name = "mirror_source_port",
1231 .description = "Mirror source port",
1232 .set = rtl8366rb_sw_set_mirror_source_port,
1233 .get = rtl8366rb_sw_get_mirror_source_port,
1234 .max = 5
1235 },
1236 };
1237
1238 static struct switch_attr rtl8366rb_port[] = {
1239 {
1240 .type = SWITCH_TYPE_NOVAL,
1241 .name = "reset_mib",
1242 .description = "Reset single port MIB counters",
1243 .set = rtl8366rb_sw_reset_port_mibs,
1244 }, {
1245 .type = SWITCH_TYPE_STRING,
1246 .name = "mib",
1247 .description = "Get MIB counters for port",
1248 .max = 33,
1249 .set = NULL,
1250 .get = rtl8366_sw_get_port_mib,
1251 }, {
1252 .type = SWITCH_TYPE_INT,
1253 .name = "led",
1254 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1255 .max = 15,
1256 .set = rtl8366rb_sw_set_port_led,
1257 .get = rtl8366rb_sw_get_port_led,
1258 }, {
1259 .type = SWITCH_TYPE_INT,
1260 .name = "disable",
1261 .description = "Get/Set port state (enabled or disabled)",
1262 .max = 1,
1263 .set = rtl8366rb_sw_set_port_disable,
1264 .get = rtl8366rb_sw_get_port_disable,
1265 }, {
1266 .type = SWITCH_TYPE_INT,
1267 .name = "rate_in",
1268 .description = "Get/Set port ingress (incoming) bandwidth limit in kbps",
1269 .max = RTL8366RB_BDTH_SW_MAX,
1270 .set = rtl8366rb_sw_set_port_rate_in,
1271 .get = rtl8366rb_sw_get_port_rate_in,
1272 }, {
1273 .type = SWITCH_TYPE_INT,
1274 .name = "rate_out",
1275 .description = "Get/Set port egress (outgoing) bandwidth limit in kbps",
1276 .max = RTL8366RB_BDTH_SW_MAX,
1277 .set = rtl8366rb_sw_set_port_rate_out,
1278 .get = rtl8366rb_sw_get_port_rate_out,
1279 },
1280 };
1281
1282 static struct switch_attr rtl8366rb_vlan[] = {
1283 {
1284 .type = SWITCH_TYPE_STRING,
1285 .name = "info",
1286 .description = "Get vlan information",
1287 .max = 1,
1288 .set = NULL,
1289 .get = rtl8366_sw_get_vlan_info,
1290 }, {
1291 .type = SWITCH_TYPE_INT,
1292 .name = "fid",
1293 .description = "Get/Set vlan FID",
1294 .max = RTL8366RB_FIDMAX,
1295 .set = rtl8366_sw_set_vlan_fid,
1296 .get = rtl8366_sw_get_vlan_fid,
1297 },
1298 };
1299
1300 static const struct switch_dev_ops rtl8366_ops = {
1301 .attr_global = {
1302 .attr = rtl8366rb_globals,
1303 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1304 },
1305 .attr_port = {
1306 .attr = rtl8366rb_port,
1307 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1308 },
1309 .attr_vlan = {
1310 .attr = rtl8366rb_vlan,
1311 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1312 },
1313
1314 .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1315 .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1316 .get_port_pvid = rtl8366_sw_get_port_pvid,
1317 .set_port_pvid = rtl8366_sw_set_port_pvid,
1318 .reset_switch = rtl8366_sw_reset_switch,
1319 .get_port_link = rtl8366rb_sw_get_port_link,
1320 };
1321
1322 static int rtl8366rb_switch_init(struct rtl8366_smi *smi)
1323 {
1324 struct switch_dev *dev = &smi->sw_dev;
1325 int err;
1326
1327 dev->name = "RTL8366RB";
1328 dev->cpu_port = RTL8366RB_PORT_NUM_CPU;
1329 dev->ports = RTL8366RB_NUM_PORTS;
1330 dev->vlans = RTL8366RB_NUM_VIDS;
1331 dev->ops = &rtl8366_ops;
1332 dev->alias = dev_name(smi->parent);
1333
1334 err = register_switch(dev, NULL);
1335 if (err)
1336 dev_err(smi->parent, "switch registration failed\n");
1337
1338 return err;
1339 }
1340
1341 static void rtl8366rb_switch_cleanup(struct rtl8366_smi *smi)
1342 {
1343 unregister_switch(&smi->sw_dev);
1344 }
1345
1346 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1347 {
1348 struct rtl8366_smi *smi = bus->priv;
1349 u32 val = 0;
1350 int err;
1351
1352 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1353 if (err)
1354 return 0xffff;
1355
1356 return val;
1357 }
1358
1359 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1360 {
1361 struct rtl8366_smi *smi = bus->priv;
1362 u32 t;
1363 int err;
1364
1365 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1366 /* flush write */
1367 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1368
1369 return err;
1370 }
1371
1372 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1373 {
1374 u32 chip_id = 0;
1375 u32 chip_ver = 0;
1376 int ret;
1377
1378 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1379 if (ret) {
1380 dev_err(smi->parent, "unable to read chip id\n");
1381 return ret;
1382 }
1383
1384 switch (chip_id) {
1385 case RTL8366RB_CHIP_ID_8366:
1386 break;
1387 default:
1388 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1389 return -ENODEV;
1390 }
1391
1392 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1393 &chip_ver);
1394 if (ret) {
1395 dev_err(smi->parent, "unable to read chip version\n");
1396 return ret;
1397 }
1398
1399 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1400 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1401
1402 return 0;
1403 }
1404
1405 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1406 .detect = rtl8366rb_detect,
1407 .reset_chip = rtl8366rb_reset_chip,
1408 .setup = rtl8366rb_setup,
1409
1410 .mii_read = rtl8366rb_mii_read,
1411 .mii_write = rtl8366rb_mii_write,
1412
1413 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1414 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1415 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1416 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1417 .get_mc_index = rtl8366rb_get_mc_index,
1418 .set_mc_index = rtl8366rb_set_mc_index,
1419 .get_mib_counter = rtl8366rb_get_mib_counter,
1420 .is_vlan_valid = rtl8366rb_is_vlan_valid,
1421 .enable_vlan = rtl8366rb_enable_vlan,
1422 .enable_vlan4k = rtl8366rb_enable_vlan4k,
1423 .enable_port = rtl8366rb_enable_port,
1424 };
1425
1426 static int rtl8366rb_probe(struct platform_device *pdev)
1427 {
1428 static int rtl8366_smi_version_printed;
1429 struct rtl8366_smi *smi;
1430 int err;
1431
1432 if (!rtl8366_smi_version_printed++)
1433 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1434 " version " RTL8366RB_DRIVER_VER"\n");
1435
1436 smi = rtl8366_smi_probe(pdev);
1437 if (!smi)
1438 return -ENODEV;
1439
1440 smi->clk_delay = 10;
1441 smi->cmd_read = 0xa9;
1442 smi->cmd_write = 0xa8;
1443 smi->ops = &rtl8366rb_smi_ops;
1444 smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1445 smi->num_ports = RTL8366RB_NUM_PORTS;
1446 smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1447 smi->mib_counters = rtl8366rb_mib_counters;
1448 smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1449
1450 err = rtl8366_smi_init(smi);
1451 if (err)
1452 goto err_free_smi;
1453
1454 platform_set_drvdata(pdev, smi);
1455
1456 err = rtl8366rb_switch_init(smi);
1457 if (err)
1458 goto err_clear_drvdata;
1459
1460 return 0;
1461
1462 err_clear_drvdata:
1463 platform_set_drvdata(pdev, NULL);
1464 rtl8366_smi_cleanup(smi);
1465 err_free_smi:
1466 kfree(smi);
1467 return err;
1468 }
1469
1470 static int rtl8366rb_remove(struct platform_device *pdev)
1471 {
1472 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1473
1474 if (smi) {
1475 rtl8366rb_switch_cleanup(smi);
1476 platform_set_drvdata(pdev, NULL);
1477 rtl8366_smi_cleanup(smi);
1478 kfree(smi);
1479 }
1480
1481 return 0;
1482 }
1483
1484 #ifdef CONFIG_OF
1485 static const struct of_device_id rtl8366rb_match[] = {
1486 { .compatible = "realtek,rtl8366rb" },
1487 {},
1488 };
1489 MODULE_DEVICE_TABLE(of, rtl8366rb_match);
1490 #endif
1491
1492 static struct platform_driver rtl8366rb_driver = {
1493 .driver = {
1494 .name = RTL8366RB_DRIVER_NAME,
1495 .owner = THIS_MODULE,
1496 .of_match_table = of_match_ptr(rtl8366rb_match),
1497 },
1498 .probe = rtl8366rb_probe,
1499 .remove = rtl8366rb_remove,
1500 };
1501
1502 static int __init rtl8366rb_module_init(void)
1503 {
1504 return platform_driver_register(&rtl8366rb_driver);
1505 }
1506 module_init(rtl8366rb_module_init);
1507
1508 static void __exit rtl8366rb_module_exit(void)
1509 {
1510 platform_driver_unregister(&rtl8366rb_driver);
1511 }
1512 module_exit(rtl8366rb_module_exit);
1513
1514 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1515 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1516 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1517 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1518 MODULE_AUTHOR("Roman Yeryomin <roman@advem.lv>");
1519 MODULE_AUTHOR("Colin Leitner <colin.leitner@googlemail.com>");
1520 MODULE_LICENSE("GPL v2");
1521 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
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